CN117676361A - Image sensor and readout circuit thereof - Google Patents
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Abstract
The invention provides an image sensor and a readout circuit thereof, wherein the readout circuit comprises a ramp voltage circuit, a comparison circuit and a counter, the comparison circuit is used for comparing an input pixel signal and a ramp voltage signal, the ramp voltage circuit outputs a first ramp voltage signal at the initial moment of an exposure sampling time period of a pixel unit, and then adaptively selects and outputs a matched ramp voltage signal from a first ramp voltage signal to an n-th ramp voltage signal according to the swing amplitude of a swing amplitude pulse signal, the swing amplitude of the output signal of the pixel unit gradually decreases along with the decrease of light intensity, the voltage range of the ramp voltage signal gradually decreases and the resolution gradually increases according to the design of an adaptive multi-sampling technology, the sampling frequency can be increased by utilizing the saved time to reduce random noise, the analog-digital conversion efficiency is improved, the resolution of the ramp signal is improved to reduce quantization noise, thereby noise of the image sensor is inhibited, and the imaging quality is improved.
Description
Technical Field
The invention belongs to the technical field of image sensors, and particularly relates to an image sensor and a reading circuit thereof.
Background
With the rapid rise of the manufacturing process, the feature size of the transistor is continuously reduced, however, the smaller size device may generate worse noise characteristics, especially the smaller size pixel source follower may generate more serious random noise. Noise from the pixels and analog readout chains is an important factor limiting imaging quality, especially at low illumination, noise can have a large impact on signal-to-noise ratio (Signal to Noise Ratio, SNR), directly affecting final imaging quality. The swing of the pixel output signal is smaller under low illumination, and the signal annihilation can be caused by excessive noise in the image sensor, so that the circuit design needs to be optimized, the noise of a pixel unit and a readout circuit is reduced, and the SNR of the image sensor is improved.
The application of correlated multisampling (Correlated Multiple Sampling, CMS) technology in a low noise monoclinic ADC (SS ADC) can well suppress noise of an image sensor and improve imaging quality.
SS ADC quantization is slow, requiring 2 for k-bit A/D conversion k With the CMS technique in SS ADCs, the total a/D conversion time increases linearly with the number of samples M, which can severely impact signal readout speed. In addition, as sampling time increases, the noise suppression capability of the CMS technique may be limited by low frequency noise (i.e., 1/f from in-pixel source follower and RTS noise). Therefore, there is a need to increase the number of samples without increasing the total conversion time, further reducing the noise level in CMOS image sensors.
Fig. 1 is a diagram illustrating a process of a/D conversion of a small swing output signal, and the swing of a pixel output signal is small in weak light, so that the effective conversion time of a ramp signal is short, and most of full-range ramp signals conventionally used are ineffective. For multiple sampling operations, the repeated use of the full range ramp signal results in greater waste, resulting in reduced analog-to-digital conversion efficiency.
Disclosure of Invention
The invention aims to provide a readout circuit of an image sensor, which aims to solve the problem that the traditional image sensor has low conversion efficiency when adopting a full-range ramp signal to perform multi-sampling.
A first aspect of an embodiment of the present invention provides a readout circuit of an image sensor, including:
a ramp voltage circuit configured to output a first ramp voltage signal at an initial time of an exposure sampling period of the pixel unit, and to select and output one of the first to nth ramp voltage signals according to a swing of a swing pulse signal, wherein a voltage range from the first to nth ramp voltage signals sequentially decreases and a ramp resolution shows a trend of increasing, where n is a positive integer greater than or equal to 2;
The first input end of the comparison circuit is connected with the pixel unit, the second input end and the output end of the comparison circuit are respectively connected with the slope voltage circuit and are configured to compare the pixel signal output by the pixel unit with the first slope voltage signal so as to output the swing pulse signal, and then compare the pixel signal output by the pixel unit with one slope voltage signal from the first slope voltage signal to the n slope voltage signal so as to output a first pulse signal corresponding to the slope voltage signal;
and the counter is connected with the output end of the comparison circuit and is configured to count the swing pulse signal and the first pulse signal so as to output a first digital code value to the control circuit, so that the control circuit determines the brightness information of the current picture according to the digital code value.
Optionally, the ramp voltage circuit is further configured to output a reset ramp voltage signal during a reset sampling period of the pixel unit;
the comparison circuit is further configured to compare a reset signal output by the pixel unit with the reset ramp voltage signal and output a second pulse signal;
the counter is further configured to count the second pulse signal and output a second digital code value;
The readout circuit of the image sensor further includes:
the first latch is connected with the counter, is configured to latch the first digital code value in an exposure sampling time period and is controlled by a first enabling signal to output the first digital code value to the control circuit;
and the second latch is connected with the counter and is configured to latch the second digital code value in a reset sampling time period and is controlled by a second enabling signal to output the second digital code value to the control circuit so that the control circuit determines the current picture brightness information according to the first digital code value and the second digital code value.
Optionally, the readout circuit of the image sensor further includes:
and the inverting amplification circuit is connected between the pixel unit and the comparison circuit and is configured to perform inverting amplification output on the pixel signal and/or the reset signal output by the pixel unit so as to output an inverting amplification value of the pixel signal and/or the reset signal output by the pixel unit to the comparison circuit.
Optionally, the inverting amplification circuit includes a first coupling capacitor, a second coupling capacitor, an operational amplifier, and a first clear switch;
The first coupling capacitor is connected between the output end of the pixel unit and the inverting input end of the operational amplifier;
the second coupling capacitor is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier;
the first zero clearing switch is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier and is controlled by a first zero clearing control signal;
and the non-inverting input end of the operational amplifier receives an input reference voltage signal, and the output end of the operational amplifier is connected with the comparison circuit.
Optionally, the comparison circuit includes a comparator, a second clear switch and a third coupling capacitor;
the second zero clearing switch is connected between the inverting input end and the output end of the comparator and is controlled by a second zero clearing control signal;
the third coupling capacitor is connected between the output end of the inverting amplification circuit and the inverting input end of the comparator;
and the non-inverting input end of the comparator receives the ramp voltage signal output by the ramp voltage circuit, and the output end of the comparator is connected with the counter.
Optionally, the ramp voltage circuit includes:
A multi-ramp generator configured to generate the first to nth ramp voltage signals;
and the slope selection circuit is respectively connected with the multi-slope generator and the comparison circuit, and outputs one of the first slope voltage signal to the nth slope voltage signal to the comparison circuit according to the swing amplitude of the swing amplitude pulse signal.
Optionally, the ramp selection circuit includes:
the switch selection circuit is connected with the multi-slope generator and is configured to be controlled by a selection signal so as to selectively output the first slope voltage signal to a corresponding one of the nth slope voltage signals;
the signal source circuit is configured to output a plurality of index signals, the periods of the index signals are equal, and the high-level time duty ratio of the index signals is changed in sequence corresponding to each slope voltage signal;
and the logic processing circuit is respectively connected with the signal source circuit and the comparison circuit at the input end, is connected with the switch selection circuit at the output end, and is configured to correspondingly generate the selection signal to the switch selection circuit based on the swing amplitude of the swing amplitude pulse signal and the index signal.
Optionally, the logic processing circuit includes:
the first end of each OR gate receives one index signal of the signal source circuit;
the D flip-flops are in one-to-one correspondence with the OR gates, the clock signal end of each D flip-flop is connected with the output end of the comparison circuit, the input end of each D flip-flop is connected with the output end of the corresponding OR gate, and the output end of each D flip-flop is connected with the second end of the corresponding OR gate;
the decoder is respectively connected with the output ends of the D triggers, is configured to convert the logic values output by the D triggers into the selection signals and output the selection signals to the switch selection circuit, and is also configured to feed back the sampling times to the control circuit.
Optionally, the switch selection circuit includes a plurality of first switches controlled by the selection signal;
the first end of each first switch is respectively connected with one of the first slope voltage signal to the n slope voltage signal, and the second end of each first switch is commonly connected with the output end of the switch selection circuit so as to output one of the first slope voltage signal to the n slope voltage signal.
Optionally, the signal source circuit includes x index signals, and n-x=1.
Optionally, the voltage range corresponding to the mth ramp voltage signal is:
wherein V is R And (3) representing the maximum quantization range of analog-to-digital conversion, wherein m is a positive integer greater than or equal to 1.
Optionally, the ramp voltage signal includes a first ramp voltage signal, a second ramp voltage signal, a third ramp voltage signal, and a fourth ramp voltage signal;
the voltage range of the first slope voltage signal isThe voltage range of the second slope voltage signal is +.>The voltage range of the third slope voltage signal is +.>The voltage range of the fourth ramp voltage signal is +.>The resolution of the first slope voltage signal is the same as that of the second slope voltage signal, the resolution of the third slope voltage signal is 1bit higher than that of the second slope voltage signal, and the resolution of the fourth slope voltage signal is 1bit higher than that of the third slope voltage signal;
wherein V is R Representing the maximum quantization range of the analog-to-digital conversion.
Optionally, the sampling frequency corresponding to the first ramp voltage signal is 2;
the sampling times corresponding to the second slope voltage signal to the nth slope voltage signal are as follows: 2 n -1。
A second aspect of an embodiment of the present invention proposes an image sensor, including a pixel array, a control circuit, and a plurality of readout circuits of the image sensor as described above, the pixel array including a plurality of pixel units arranged in an array;
the readout circuit of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits of the image sensors are also respectively connected with the control circuit.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: in the readout circuit of the image sensor, a ramp voltage circuit, a comparison circuit and a counter are provided, the comparison circuit is used for comparing an input pixel signal and a ramp voltage signal, the ramp voltage circuit outputs a first ramp voltage signal at the initial time of an exposure sampling time period of the pixel unit, and then adaptively selects and outputs a matched ramp voltage signal from the first ramp voltage signal to an nth ramp voltage signal according to the swing amplitude of the swing amplitude pulse signal, as the light intensity is reduced, the swing amplitude of the output signal of the pixel unit is gradually reduced, and according to the design of an adaptive multi-sampling technology, the voltage range of the ramp voltage signal is gradually reduced, the resolution is gradually increased, the sampling times can be increased by utilizing the saved time to reduce random noise, optimize the analog-to-digital conversion time, and improve the analog-to-digital conversion efficiency, or improve the resolution of the ramp signal to reduce quantization noise, thereby inhibiting the noise of the image sensor and improving the imaging quality.
Drawings
FIG. 1 is a schematic diagram of a multi-sampling waveform of a conventional image sensor;
fig. 2 is a schematic block diagram of an image sensor according to a fifth embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a pixel unit in a conventional image sensor;
FIG. 4 is a schematic block diagram of a readout circuit of an image sensor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of waveforms of a multi-ramp voltage signal according to a first embodiment of the present invention;
fig. 6 is a schematic block diagram of a readout circuit of an image sensor according to a second embodiment of the present invention;
fig. 7 is a schematic diagram of a first module of a readout circuit of an image sensor according to a third embodiment of the present invention;
FIG. 8 is a schematic diagram of a second module of a readout circuit of an image sensor according to a third embodiment of the present invention;
FIG. 9 is a waveform timing diagram of signals according to a third embodiment of the present invention;
fig. 10 is a schematic diagram of a first module of a readout circuit of an image sensor according to a fourth embodiment of the present invention;
FIG. 11 is a schematic diagram of a second module of a readout circuit of an image sensor according to a fourth embodiment of the present invention;
fig. 12 is a circuit schematic diagram of a logic processing circuit according to a fourth embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
In a first aspect of the present invention, as shown in fig. 2, an image sensor generally includes a control circuit 3, a pixel array 100, a readout circuit 1, and may further include a clock generator and a digital I/O port, where the pixel array 100 includes a plurality of pixel units arranged in an array, the plurality of pixel units arranged in a column are commonly connected, the control circuit 3 selects each row of pixel units through a row selection signal and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units arranged in the column are connected to the corresponding readout circuit 1, the readout circuit 1 performs analog-to-digital conversion and outputs a corresponding digital code value to the control circuit 3, so that the control circuit 3 determines image information according to the digital code value.
The pixel unit generally includes a photoelectric conversion element, a transfer transistor TX, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL, where the photoelectric conversion element includes, but is not limited to, a photodiode PD, for example, a Pin-type photodiode PD, and meanwhile, the number of the photoelectric conversion element, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL may be one or more, that is, the structure of the pixel unit may be correspondingly selected, and the specific structure is not limited, as shown in fig. 3, taking the basic pixel unit 2 as an example, the pixel unit 2 includes a photodiode PD, the transfer transistor TX, the reset transistor RST, the source follower transistor SF, and the row selection transistor SEL, where a cathode of the photodiode PD is connected to a first end of the transfer transistor TX, a second end of the reset transistor RST, and a controlled end of the source follower transistor SF are all coupled to a floating diffusion node, an anode of the photodiode PD is grounded, a second end of the reset transistor RST and a first end of the source follower transistor SF are both connected to a first end of the row selection transistor SF and a second end of the pixel element SF is connected to a first end of the row selection transistor SF, and a second end of the pixel element SF is connected to a first end of the row selection transistor SF is connected to a first end of the pixel element 2.
Wherein, corresponding to the pixel unit 2 of the corresponding structure, as shown in fig. 4, the readout circuit 1 includes:
a ramp voltage circuit 10 configured to output a first ramp voltage signal SP1 at an initial timing of an exposure sampling period of the pixel unit 2, and to select and output one of the first to n-th ramp voltage signals according to a swing of the swing pulse signal later, wherein voltage ranges of the first to n-th ramp voltage signals SP1 to SP are sequentially smaller and a ramp resolution shows a trend of becoming larger, where n is a positive integer of 2 or more;
as can be appreciated, the initial floating diffusion node voltage is the voltage after reset, and the charge generated after the photodiode PD is exposed is coupled to the floating diffusion node, which can cause the voltage of the floating diffusion node to drop to a certain extent, and the space for drop is the swing;
a comparison circuit 20 having a first input terminal connected to the pixel unit 2 and a second input terminal and an output terminal connected to the ramp voltage circuit 10, respectively, configured to compare the pixel signal output from the pixel unit 2 with the first ramp voltage signal SP1 to output a swing pulse signal, and then compare the pixel signal output from the pixel unit 2 with one of the first to n-th ramp voltage signals SP1 to output a first pulse signal corresponding to the ramp voltage signal;
The counter 30 is connected to the output end of the comparing circuit 20, and is configured to count the swing pulse signal and the first pulse signal, so as to output a first digital code value to the control circuit 3, so that the control circuit 3 determines the current picture brightness information according to the digital code value.
In this embodiment, the pixel unit 2 circularly operates in a reset sampling and an exposure sampling, wherein the photodiode acquires an optical signal through continuous exposure or intermittent exposure, and converts the optical signal into a charge signal, the transfer transistor TX is controlled to be turned on, the charge signal is transferred to the floating diffusion node, the voltage of the floating diffusion node is reduced, a pixel signal is output through the source follower transistor SF, and is output when the row select transistor SEL is turned on, the pixel signal is input to the comparison circuit 20, and is compared with the ramp voltage signal Vramp in the comparison circuit 20, and a first pulse signal is output to the counter 30, the counter 30 counts the first pulse signal in a period time after the comparison is completed according to the clock signal, and outputs a first digital code value to the control circuit 3, and stops counting after the output level of the comparison circuit 20 is turned over, and m bit data is output, wherein m is the resolution of the counter 30.
The first to nth ramp voltage signals SP1 to SP1 are provided in the ramp voltage circuit 10, or the signal input terminal of the ramp voltage circuit 10 is configured to input the first to nth ramp voltage signals SP1 to SP, wherein the voltage range of each ramp voltage signal sequentially decreases, and the ramp resolution is in a trend of increasing, that is, at least the ramp resolution of the first ramp voltage signal SP1 is greater than the ramp resolution of the nth ramp voltage signal, alternatively, the ramp resolution may be sequentially changed, or the ramp resolution of each adjacent ramp voltage signal is equal, and the specific change form of the ramp voltage signals of the second to n-1 is not limited.
After the transfer transistor TX is turned on, the charge signal of the photodiode is completely transferred to the floating diffusion node, the voltage of the floating diffusion node is reduced, and a pixel signal is output through the source follower transistor SF, the exposure sampling period sequentially includes a ramp selection stage and an analog-to-digital conversion stage, the two stages are connected together, in the ramp selection stage, the ramp voltage circuit 10 first outputs a first ramp voltage signal SP1 to the comparison circuit 20, wherein the first ramp voltage signal SP1 has a maximum voltage range and a minimum ramp resolution compared with all ramp voltage signals set in the ramp voltage circuit 10, the comparison circuit 20 compares the pixel signal and the first ramp voltage signal SP1, when the output level of the comparison circuit 20 is inverted, the ramp voltage circuit 10 selects a matched ramp voltage signal from the first ramp voltage signal SP1 to the n-th ramp voltage signal according to the received swing pulse signal, and outputs the ramp voltage signal to the comparison circuit 20 again, after the ramp selection is completed, the operation stage is switched to the analog-to-digital conversion stage, the comparison circuit 20 performs subsequent multisampling, compares the selected ramp voltage signal with the pixel signal, and correspondingly outputs a plurality of ramp voltage signals to the first ramp voltage signal, and the first ramp voltage signal is switched to the first voltage signal to the n-th ramp voltage signal, and the first signal is counted to the first level, and the current signal is counted to the first level is counted to the first signal is counted and the first signal is counted to the first level is counted and the first signal is outputted.
The magnitude of the light intensity determines the magnitude of the swing pulse signal which is output by comparison, and the magnitude of the swing pulse signal is matched with a slope voltage signal with corresponding voltage range and slope resolution. When the light intensity is high, the swing of the floating diffusion node is small, and a slope voltage signal with a small voltage range and high slope resolution is selected to be output to the comparison circuit 20; when the light intensity is strong, the swing of the floating diffusion node is large, and a ramp voltage signal with a large output voltage range and low ramp resolution is selected to the comparison circuit 20.
When the light intensity is weak, the swing pulse signal is smaller, the slope voltage signal with small output voltage range and high slope resolution is selected in a self-adaptive mode, the length of the slope voltage signal is reduced, the sampling frequency is increased, random noise is reduced, the analog-to-digital conversion time is optimized, the analog-to-digital conversion efficiency is improved, the resolution of the slope voltage signal is improved to reduce quantization noise, and therefore noise of an image sensor is restrained, and the imaging quality is improved.
Wherein the number of the ramp voltage signals, the voltage range of each ramp voltage signal and the magnitude of the ramp resolution can be specifically set according to the current ambient light intensity, wherein in order to facilitate the pixel signaling of each corresponding voltage range The numbers are compared comprehensively, and optionally, the voltage range corresponding to the m-th ramp voltage signal is as follows:
wherein V is R And (3) representing the maximum quantization range of analog-to-digital conversion, wherein m is a positive integer greater than or equal to 1.
Namely, the voltage range of the first ramp voltage signal SP1 isThe voltage range of the second ramp voltage signal SP2 is +.>The voltage range of the third ramp voltage signal SP3 is +.>The voltage range of the fourth ramp voltage signal SP4 is +.>The voltage range of the voltage signal up to the n-th ramp is +>The pixel signals in the analog-to-digital conversion stage fall within the voltage range corresponding to a ramp voltage signal, and a corresponding number of first pulse signals are output to the counter 30 for counting.
In order to consider the voltage range requirement and the line structure, and avoid the complex structure of the ramp voltage signal caused by the excessive voltage range setting and the influence of the quantization noise on the signal-to-noise ratio of the image sensor according to the light intensity, optionally, as shown in fig. 5, the ramp voltage signal includes a first ramp voltage signal SP1, a second ramp voltage signal SP2, a third ramp voltage signal SP3 and a fourth ramp voltage signal SP4;
the voltage range of the first ramp voltage signal SP1 isThe voltage range of the second ramp voltage signal SP2 is +. >The voltage range of the third ramp voltage signal SP3 is +.>The voltage range of the fourth ramp voltage signal SP4 is +.>The resolution of the first ramp voltage signal SP1 is the same as that of the second ramp voltage signal SP2, the resolution of the third ramp voltage signal SP3 is 1bit higher than that of the second ramp voltage signal SP2, and the resolution of the fourth ramp voltage signal SP4 is 1bit higher than that of the third ramp voltage signal SP 3;
wherein V is R Representing the maximum quantization range of the analog-to-digital conversion.
In this embodiment, since the signal-to-noise ratio of the image sensor is determined by random noise and quantization noise under weak light, by setting the ramp voltage signal group and adaptively changing the voltage range and gain of the ramp voltage signal according to the output swing of the pixel unit, the random noise and quantization noise can be reduced by multiple pixel signal sampling under weak light and increasing the ramp resolution under weak light, and the signal-to-noise ratio of the image sensor under weak light can be compensated without affecting the signal readout speed.
When the image sensor works in the exposure sampling period, the ramp voltage signal firstly outputs a first ramp voltage signal SP1, the comparison circuit 20 compares the pixel signal and the first ramp voltage signal SP1 to output a swing pulse signal, the counter 30 synchronously counts the swing pulse signal, when the output level of the comparison circuit 20 is inverted, the counter 30 stops counting, the ramp voltage circuit 10 selects a matched ramp voltage signal from the first ramp voltage signal SP1 to the fourth ramp voltage signal SP4 according to the received swing pulse signal and outputs the matched ramp voltage signal to the comparison circuit 20 again, after the ramp selection is completed, the operation stage is switched to the analog-to-digital conversion stage, the subsequent multi-sampling is performed, the comparison circuit 20 compares the selected ramp voltage signal and the pixel signal for a plurality of times and correspondingly outputs a plurality of first pulse signals, when the first pulse signal output by the comparison circuit 20 is switched to a high level, the counter 30 synchronously counts the first pulse signal and outputs a first digital code value to the control circuit 3 after the plurality of times of sampling is completed, so as to determine whether the current picture brightness information is determined according to the fact that the first digital code value of the first swing signal is large, and the actual digital code value of the first swing value is kept, and whether the actual digital code value of the first swing value is large or not is large.
The magnitude of the light intensity determines the magnitude of the swing pulse signal which is output by comparison, and the magnitude of the swing pulse signal is matched with a slope voltage signal with corresponding voltage range and slope resolution. When the light intensity is low, the ramp voltage circuit 10 can selectively output the fourth ramp voltage signal SP4 to the comparison circuit 20 according to the swing pulse signal, and compare the pixel signal with the fourth ramp voltage signal SP4 to output the first pulse signal, at this time, the counting result of the swing pulse signal is not required to be reserved, and the final first digital code value is determined according to the counting result of the first pulse signal; when the light intensity is strong, the ramp voltage circuit 10 can selectively output the first ramp voltage signal SP1 to the comparison circuit 20 according to the swing pulse signal, and compare the pixel signal with the first ramp voltage signal SP1 to output the first pulse signal, so that the counting result of the swing pulse signal is required to be maintained, and the final first digital code value is determined according to the counting result of the swing pulse signal and the counting result of the first pulse signal.
Meanwhile, the first ramp voltage signal SP1 is output first in each exposure sampling period, and is a default ramp voltage signal, after the swing pulse signal is output, the ramp voltage circuit 10 selects and outputs a ramp voltage signal for multiple sampling, different from the first ramp voltage signal SP1, after the ramp voltage signal is switched, other ramp voltage signals need to be reset, and the sampling frequency needs to be subtracted once, so, referring to fig. 5, according to the voltage range and the ramp resolution of each ramp voltage signal, optionally, the sampling frequency corresponding to the first ramp voltage signal SP1 is 2;
The sampling times corresponding to the remaining second to nth ramp voltage signals SP2 to n are: 2 n -1。
For example, the first ramp voltage signal SP1 has a sampling number of 2, the second ramp voltage signal SP2 has a sampling number of 3, the third ramp voltage signal SP3 has a sampling number of 7, and the fourth ramp voltage signal SP4 has a sampling number of 15.
The ramp voltage circuit 10 may be provided with a corresponding structure such as a signal selection circuit or a signal source, and the specific structure is not limited.
The comparator circuit 20 may select the corresponding comparator U1 and the peripheral auxiliary circuit, and the specific structure is not limited.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: in the readout circuit 1 of the image sensor, a ramp voltage circuit 10, a comparison circuit 20 and a counter 30 are provided, the comparison circuit 20 is used for comparing an input pixel signal with a ramp voltage signal, the ramp voltage circuit 10 outputs a first ramp voltage signal SP1 at an initial time of an exposure sampling period of the pixel unit 2, and then adaptively selects and outputs a matched ramp voltage signal from the first ramp voltage signal SP1 to an nth ramp voltage signal according to a swing amplitude of a swing amplitude pulse signal, as the light intensity decreases, the swing amplitude of the output signal of the pixel unit 2 gradually decreases, and according to the design of an adaptive multi-sampling technology, the voltage range of the ramp voltage signal gradually decreases and the resolution gradually increases, and the sampling frequency can be increased by using the saved time to reduce random noise, optimize the analog-digital conversion time, and improve the analog-digital conversion efficiency, or improve the resolution of the ramp signal to reduce quantization noise, thereby suppressing noise of the image sensor and improving the imaging quality.
Example two
Based on the optimization and refinement of the first embodiment, in order to eliminate offset voltage in the circuit and improve analog-to-digital conversion accuracy, optionally, as shown in fig. 6, the ramp voltage circuit 10 is further configured to output a reset ramp voltage signal during a reset sampling period of the pixel unit 2;
a comparison circuit 20 further configured to compare the reset signal and the reset ramp voltage signal output from the pixel unit 2 and output a second pulse signal;
a counter 30 further configured to count the second pulse signal and output a second digital code value;
the readout circuit 1 of the image sensor further includes:
a first latch 40 connected to the counter 30, the first latch 40 being configured to latch the first digital code value during the exposure sampling period and to output the first digital code value to the control circuit 3 under the control of a first enable signal EN 1;
the second latch 50 is connected to the counter 30, and the second latch 50 is configured to latch the second digital code value in a reset sampling period and is controlled by the second enable signal EN2 to output the second digital code value to the control circuit 3, so that the control circuit 3 determines the current picture brightness information according to the first digital code value and the second digital code value.
In this embodiment, the pixel unit 2 circularly works in the reset sampling and the exposure sampling, the reset sampling period, the pixel unit 2, the comparison circuit 20 and the counter 30 are reset correspondingly, the offset voltage and the reset noise of each stage are stored in the circuit of the next stage, then the reset signal is compared with the reset ramp voltage signal to complete the quantization of the reset voltage, the sampling of the reset signal is performed for N times, wherein the sampling of the reset signal can be one time or multiple times, and when the second pulse signal output by the comparison circuit 20 is at the high level, the counter 30 starts to count synchronously. Finally, the reset voltage sample data in the counter 30 is stored into the second latch 50 by the second enable signal EN 2. Considering the offset voltage of the circuit, the output value of the second latch 50 corresponds to the sampling data of the N times of reset voltage and offset voltage, and the output value Dout1 of the second latch 50 is expressed as:
D out1 ＝D rst,N +D offset,N
wherein Drst, N is the sampling data of N times of reset signals, doffset, N is the offset voltage stored after N times of reset signal sampling.
Then, working in the exposure sampling phase, the conversion of the exposure signal is divided into two phases: the ramp selection stage and the analog-to-digital conversion stage are connected together, and in the ramp selection stage, the first ramp signal is connected to the comparison circuit 20 by default. When the output of the comparison circuit 20 is turned over, the matching ramp voltage signal is selected to be connected to the comparison circuit 20 according to the swing pulse signal. After the ramp selection is completed, the operation phase moves to an analog-to-digital conversion phase, and a subsequent multi-sampling function is executed. Also, when the output of the comparison circuit 20 is at a high level, the counter 30 starts synchronous counting. Finally, the exposure signal sampling data in the counter 30 is stored in the first latch 40 by the first enable signal EN 1. The output value Dout2 of the first latch 40 is expressed as:
D out2 ＝D sig,M +D offset,M
Wherein Dsig, M is sampling data of M exposure signals, doffset, M is offset voltage stored after sampling the M exposure signals.
The final data processing is completed by the outputs of Dout1, dout2 and the ramp voltage circuit 10 together, and the output of the ramp voltage circuit 10 determines the number M of transitions of the exposure signal, i.e., the number of samples, so that the final output Dout of each pixel is expressed as:
as can be seen from the above formula, the offset voltage is finally eliminated by a digital correlated double sampling (Digital Correlated Double Sampling, D-CDS) technique. In the present design, the switching time of the exposure signal Vsig does not increase with an increase in the number of samples. Only the ramp voltage circuit 10 configuration needs to be changed and the adaptive CMS technique can be implemented by a conventional SS ADC configuration.
The core idea of the adaptive CMS technique is to automatically select an appropriate ramp voltage signal according to the light intensity to access the comparison circuit 20, so as to complete the subsequent analog-to-digital conversion. For the dim light pixel unit 2 with smaller signal swing, a small-range and high-gain ramp signal is used for multiple times to reduce random noise and quantization noise and compensate the signal to noise ratio under the dim light. Therefore, before quantizing the exposure signal Vsig, it is necessary to detect the swing of the signal and complete the selective switching of the ramp voltage signal.
Example III
Based on the optimization and refinement of the second embodiment, optionally, as shown in fig. 7, the readout circuit 1 of the image sensor further includes:
the inverting amplification circuit 60, which is connected between the pixel unit 2 and the comparison circuit 20, is configured to perform inverting amplification output on the pixel signal and/or the reset signal output from the pixel unit 2 to output an inverting amplification value of the pixel signal and/or the reset signal output from the pixel unit 2 to the comparison circuit 20.
In this embodiment, the inverting amplifying circuit 60 is configured to amplify the pixel signal and/or the reset signal output by the pixel unit 2 in an inverting manner, so as to suppress noise input to a subsequent circuit, where the inverting amplifying circuit 60 may select a corresponding amplifier structure, and optionally, as shown in fig. 8, the inverting amplifying circuit 60 includes a first coupling capacitor C1, a second coupling capacitor C2, an operational amplifier OP1, and a first clear switch SA;
the first coupling capacitor C1 is connected between the output end of the pixel unit 2 and the inverting input end of the operational amplifier OP 1;
the second coupling capacitor C2 is connected between the inverting input end of the operational amplifier OP1 and the output end of the operational amplifier OP 1;
the first zero clearing switch SA is connected between the inverting input end of the operational amplifier OP1 and the output end of the operational amplifier OP1 and is controlled by a first zero clearing control signal;
The noninverting input terminal of the operational amplifier OP1 receives the input reference voltage signal, and the output terminal of the operational amplifier OP1 is connected to the comparator circuit 20.
In this embodiment, by changing the ratio of the first coupling capacitor C1 to the second coupling capacitor C2, programmable amplification of the output signal of the pixel unit 2 can be achieved.
With continued reference to fig. 8, the comparing circuit 20 optionally includes a comparator U1, a second clear switch SC, and a third coupling capacitor C3;
the second zero clearing switch SC is connected between the inverting input end and the output end of the comparator U1 and is controlled by a second zero clearing control signal;
the third coupling capacitor C3 is connected between the output terminal of the inverting amplifier circuit 60 and the inverting input terminal of the comparator U1;
the non-inverting input terminal of the comparator U1 receives the ramp voltage signal output by the ramp voltage circuit 10, and the output terminal of the comparator U1 is connected to the counter 30.
In this embodiment, referring to fig. 8 and 9, the pixel unit 2 is cyclically operated in the reset sampling and the exposure sampling, the reset sampling period, the floating diffusion node in the pixel unit 2 is reset, and the operational amplifier OP1 and the comparator U1 are also reset in sequence. The reset transistor RST, the first clear switch SA and the second clear switch SC are sequentially closed to store the offset voltage and the reset noise of each stage into the capacitor of the subsequent stage, and the counter 30 also completes the reset operation. And then, comparing the amplified reset signal with a reset ramp voltage signal, wherein the reset ramp voltage signal is a first ramp voltage signal SP1, and the quantification of the reset voltage is completed. For N samples of the reset signal, the counter 30 starts to count synchronously when the output Vcomp of the comparator U1 is high. Finally, the reset voltage sample data in the counter 30 is stored into the second latch 50 by the second enable signal EN 2. Considering the offset voltage of the circuit, the output Dout1 of the second latch 50 corresponds to sampling data of the N times of reset voltage and offset voltage, and may be expressed as:
D out1 ＝D rst,N +D offset,N
Wherein Drst, N is the sampling data of N times of reset signals, doffset, N is the offset voltage stored after N times of reset signal sampling.
After the transfer transistor TX is turned on, the photo-charges in the PD are completely transferred to the floating diffusion node, and the output voltage Vamp of the amplifier rises to the amplified exposure signal level. The conversion of the exposure signal is divided into two phases: the ramp selection stage and the analog-to-digital conversion stage are connected together for saving time, and in the selection stage, the maximum ramp voltage signal (first ramp voltage signal SP 1) is connected to the comparator U1 by default. When the output of the comparator U1 is overturned, a matched ramp voltage signal is selected to be connected into the comparator U1 according to the output result of the ramp selector. After the ramp selection is completed, the operation phase moves to an analog-to-digital conversion phase, and a subsequent multi-sampling function is executed. Correspondingly, when the output Vcomp of the comparator U1 is high, the counter 30 starts to count synchronously. Finally, the exposure signal sampling data in the counter 30 is stored in the first latch 40 by the first enable signal EN 1. The output Dout2 of the second latch 50 can be expressed as:
D out2 ＝D sig,M +D offset,M
wherein Dsig, M is sampling data of M exposure signals, doffset, M is offset voltage stored after sampling the M exposure signals.
The final data processing is done jointly by Dout1, dout2 and the output of the ramp selector.
Optionally, the comparing circuit may further include a fourth coupling capacitor connected between the non-inverting input terminal of the comparator and the ramp voltage circuit; the comparison circuit can also comprise a third zero clearing switch which is connected between the non-inverting input end and the output end of the comparator and is controlled by a third zero clearing control signal.
Example IV
Refinement and optimization are performed on the basis of the first embodiment, and as shown in fig. 10, the ramp voltage circuit 10 optionally includes:
a multi-ramp generator 11 configured to generate first to nth ramp voltage signals SP1 to SP;
the ramp selection circuit 12 is respectively connected with the multi-ramp generator 11 and the comparison circuit 20, and the ramp selection circuit 12 outputs one of the first to nth ramp voltage signals SP1 to 20 according to the swing of the swing pulse signal.
In this embodiment, the multi-ramp generator 11 is used as a signal source, outputs the first to nth ramp voltage signals SP1 to the ramp selection circuit 12, the ramp selection circuit 12 selects and outputs a matched ramp voltage signal according to the magnitude of the received swing pulse signal, after the ramp selection is completed, the operation phase is switched to the analog-to-digital conversion phase, the subsequent multi-sampling is performed, the comparison circuit 20 compares the selected ramp voltage signal with the pixel signal for a plurality of times and correspondingly outputs a plurality of first pulse signals, and when the first pulse signal output by the comparison circuit 20 is switched to a high level, the counter 30 synchronously counts the first pulse signal and outputs a first digital code value to the back-end control circuit 3 to determine the current picture brightness information.
The multi-ramp generator 11 may select a corresponding signal source or signal generator, and the specific structure is not limited, and the resolution and voltage range of each ramp voltage signal correspondingly vary.
The ramp selection circuit 12 selects and outputs a corresponding ramp voltage signal to the comparison circuit 20 by performing a logic operation or comparison on the magnitude of the swing pulse signal, and the ramp selection circuit 12 may select a corresponding switching circuit, the control circuit 3, or the like, as shown in fig. 11 and 12, and the ramp selection circuit 12 may optionally include:
a switch selection circuit 121 connected to the multi-ramp generator 11 and configured to be controlled by a selection signal to selectively output a corresponding one of the first to nth ramp voltage signals SP1 to SP;
the signal source circuit 122 is configured to output a plurality of index signals, the periods of the plurality of index signals are equal, and the high-level time duty ratio is changed in turn corresponding to each ramp voltage signal;
the logic processing circuit 123 has an input terminal connected to the signal source circuit 122 and the comparison circuit 20, and an output terminal connected to the switch selection circuit 121, and is configured to correspondingly generate a selection signal to the switch selection circuit 121 based on the swing of the swing pulse signal and the index signal.
In this embodiment, the index signals, for example index1, index2, index3, have periods with the same size, and the high-level duty ratio thereof sequentially becomes larger or smaller, specifically, is correspondingly selected according to the amplitude of the amplitude pulse signal, and the logic processing circuit 123 generates corresponding logic values according to the comparison between the amplitude of the amplitude pulse signal and each index signal, and generates corresponding selection signals according to the logic values, so as to selectively output the ramp voltage signals matched with the logic values.
Wherein, the switch selection circuit 121 may select a single multiple-input single-output switching device, or a multiple-switch circuit connected by a plurality of switches is adopted, as shown in fig. 12, alternatively, the switch selection circuit 121 includes a plurality of first switches K1 controlled by a selection signal;
the first end of each first switch K1 is connected to one of the first to n-th ramp voltage signals SP1, and the second end of each first switch K1 is commonly connected to the output end of the switch selection circuit 121, so as to output one of the first to n-th ramp voltage signals SP1, and the selection signal output by the logic processing circuit 123 selects one of the first switches K1 to be turned on each time, and triggers the remaining first switches K1 to maintain an off state, thereby selectively outputting the desired ramp voltage signal.
With continued reference to fig. 12, optionally, the logic processing circuit 123 includes:
a plurality of or gates U2, wherein a first end of each or gate U2 receives an index signal of the signal source circuit 122;
the plurality of D flip-flops DFF are in one-to-one correspondence with the plurality of OR gates U2, the clock signal end of each D flip-flop DFF is connected with the output end of the comparison circuit 20, the input end of each D flip-flop DFF is connected with the output end of the corresponding OR gate U2, and the output end of each D flip-flop DFF is connected with the second end of the corresponding OR gate U2;
the decoder U3 is connected to the output terminals of the D flip-flops DFF, and the decoder U3 is configured to convert the logic values output from the D flip-flops DFF into selection signals and output the selection signals to the switch selection circuit 121, and is further configured to feed back the sampling times to the control circuit 3.
In this embodiment, the logic processing circuit 123 and its timing are designed as shown in fig. 12, and Vamp and Vcomp are the inverting amplifier circuit 60 and the comparator circuit 20, respectively. The designed logic processing circuit 123 detects the signal swing using a plurality of index signals (e.g., index1, index2, and index 3), the index signal width being related to the duration of the plurality of ramp voltage signals. The maximum ramp voltage signal is first connected to the comparator U1 by resetting the D flip-flop DFF. When the comparator U1 output is flipped from "L" to "H", the generated rising edge signal causes the D flip-flop DFF to latch the levels of the plurality of index signals at this time, for example, as shown in fig. 12, the logic value "011" is latched by the D flip-flop DFF. The logic value is then fed back to the decoder U3, and the decoder U3 decodes and outputs a corresponding selection signal to the corresponding first switch K1, so that it controls the appropriate ramp voltage signal to be connected to the comparator U1. In addition, the outputs of the plurality of D flip-flops DFF are reversely connected back to the input through the OR gate U2 to latch the ramp selection result, so that the flip-flop DFF is prevented from being triggered to be rewritten during the multiple sampling period of Vsig. When the outputs of the plurality of D flip-flops DFF are 000, 001, 011 and 111, or 0000, 0001, 0011, 0111 and 1111, since the previous pixel signal is inversely amplified by the inverting amplifying circuit 60, the signals are in an inverted ratio, the selected ramp voltage signals are the first ramp voltage signal SP1, the second ramp voltage signal SP2, the third ramp voltage signal SP3 and the fourth ramp voltage signal SP4, respectively, or the selected ramp voltage signals are the first ramp voltage signal SP1, the second ramp voltage signal SP2, the third ramp voltage signal SP3, the fourth ramp voltage signal SP4, the fifth ramp voltage signal, etc., respectively, and the output values of the plurality of D flip-flops DFF show the number M of times the exposure signal is converted in the analog-digital conversion stage. Logic processing circuit 123 is implemented using simple digital logic circuits and some additional switches so that ramp select circuit 12 has substantially no effect on the area and power consumption of sense circuit 1.
The or gates U2, D flip-flop DFF are determined according to the number of index signals, and at the same time, the number of index signals and the number of ramp voltage signals differ by 1, that is, optionally, the signal source circuit 122 includes x index signals, and n-x=1.
For example, as shown in fig. 12, the logic processing circuit 123 detects the signal swing using three index signals (e.g., index1, index2, and index 3), the index signal width being related to the duration of the plurality of ramp voltage signals. The maximum ramp voltage signal is first connected to the comparator U1 by resetting the D flip-flop DFF. When the comparator U1 output is flipped from "L" to "H", the generated rising edge signal causes the D flip-flop DFF to latch the levels of the plurality of index signals at this time, for example, as shown in fig. 12, the logic value "011" is latched by the D flip-flop DFF. The logic value is then fed back to the decoder U3, and the decoder U3 decodes and outputs a corresponding selection signal to the corresponding first switch K1, so that it controls the appropriate ramp voltage signal to be connected to the comparator U1. In addition, the outputs of the plurality of D flip-flops DFF are reversely connected back to the input through the OR gate U2 to latch the ramp selection result, so that the flip-flop DFF is prevented from being triggered to be rewritten during the multiple sampling period of Vsig. When the outputs of the three D flip-flops DFF are 000, 001, 011 and 111, since the previous pixel signal is inversely amplified by the inverting amplifying circuit 60, the signals are in an inverted proportion, and the selected ramp voltage signals are the first ramp voltage signal SP1, the second ramp voltage signal SP2, the third ramp voltage signal SP3 and the fourth ramp voltage signal SP4, respectively, and the output values of the other three D flip-flops DFF show the number M of times the exposure signal is converted in the analog-to-digital conversion stage.
Example five
The present invention also proposes an image sensor, as shown in fig. 2, which includes a pixel array 100, a control circuit 3 and a plurality of readout circuits 1 of the image sensor, where the specific structure of the readout circuits 1 of the image sensor refers to the above embodiments, and since the image sensor adopts all the technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are not described herein. The pixel array 100 includes a plurality of pixel units 2 arranged in an array;
the readout circuit 1 of each image sensor is respectively connected with a plurality of pixel units 2 arranged in a column, and the readout circuit 1 of each image sensor is also respectively connected with the control circuit 3.
The pixel array 100 includes a plurality of pixel units 2 arranged in an array, the plurality of pixel units 2 arranged in a column are commonly connected, the control circuit 3 selects each row of pixel units 2 through a row selection signal and sequentially outputs pixel signals of each row to the readout circuit 1, the plurality of pixel units 2 arranged in the column are connected with the corresponding readout circuit 1, the readout circuit 1 performs analog-digital conversion, and outputs a corresponding digital code value to the control circuit 3, so that the control circuit 3 determines image information according to the digital code value.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (14)
1. A readout circuit of an image sensor, comprising:
a ramp voltage circuit configured to output a first ramp voltage signal at an initial time of an exposure sampling period of the pixel unit, and to select and output one of the first to nth ramp voltage signals according to a swing of a swing pulse signal, wherein a voltage range from the first to nth ramp voltage signals sequentially decreases and a ramp resolution shows a trend of increasing, where n is a positive integer greater than or equal to 2;
the first input end of the comparison circuit is connected with the pixel unit, the second input end and the output end of the comparison circuit are respectively connected with the slope voltage circuit and are configured to compare the pixel signal output by the pixel unit with the first slope voltage signal so as to output the swing pulse signal, and then compare the pixel signal output by the pixel unit with one slope voltage signal from the first slope voltage signal to the n slope voltage signal so as to output a first pulse signal corresponding to the slope voltage signal;
And the counter is connected with the output end of the comparison circuit and is configured to count the swing pulse signal and the first pulse signal so as to output a first digital code value to the control circuit, so that the control circuit determines the brightness information of the current picture according to the digital code value.
2. The readout circuit of the image sensor of claim 1, wherein the ramp voltage circuit is further configured to output a reset ramp voltage signal during a reset sampling period of the pixel cell;
the comparison circuit is further configured to compare a reset signal output by the pixel unit with the reset ramp voltage signal and output a second pulse signal;
the counter is further configured to count the second pulse signal and output a second digital code value;
the readout circuit of the image sensor further includes:
the first latch is connected with the counter, is configured to latch the first digital code value in an exposure sampling time period and is controlled by a first enabling signal to output the first digital code value to the control circuit;
and the second latch is connected with the counter and is configured to latch the second digital code value in a reset sampling time period and is controlled by a second enabling signal to output the second digital code value to the control circuit so that the control circuit determines the current picture brightness information according to the first digital code value and the second digital code value.
3. The readout circuit of the image sensor of claim 2, wherein the readout circuit of the image sensor further comprises:
and the inverting amplification circuit is connected between the pixel unit and the comparison circuit and is configured to perform inverting amplification output on the pixel signal and/or the reset signal output by the pixel unit so as to output an inverting amplification value of the pixel signal and/or the reset signal output by the pixel unit to the comparison circuit.
4. The readout circuit of the image sensor of claim 3, wherein the inverting amplification circuit comprises a first coupling capacitor, a second coupling capacitor, an operational amplifier, and a first clear switch;
the first coupling capacitor is connected between the output end of the pixel unit and the inverting input end of the operational amplifier;
the second coupling capacitor is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier;
the first zero clearing switch is connected between the inverting input end of the operational amplifier and the output end of the operational amplifier and is controlled by a first zero clearing control signal;
and the non-inverting input end of the operational amplifier receives an input reference voltage signal, and the output end of the operational amplifier is connected with the comparison circuit.
5. The readout circuit of the image sensor of claim 4, wherein the comparison circuit comprises a comparator, a second clear switch, and a third coupling capacitance;
the second zero clearing switch is connected between the inverting input end and the output end of the comparator and is controlled by a second zero clearing control signal;
the third coupling capacitor is connected between the output end of the inverting amplification circuit and the inverting input end of the comparator;
and the non-inverting input end of the comparator receives the ramp voltage signal output by the ramp voltage circuit, and the output end of the comparator is connected with the counter.
6. The readout circuit of the image sensor of claim 1, wherein the ramp voltage circuit comprises:
a multi-ramp generator configured to generate the first to nth ramp voltage signals;
and the slope selection circuit is respectively connected with the multi-slope generator and the comparison circuit, and outputs one of the first slope voltage signal to the nth slope voltage signal to the comparison circuit according to the swing amplitude of the swing amplitude pulse signal.
7. The readout circuit of the image sensor of claim 6, wherein the ramp selection circuit comprises:
the switch selection circuit is connected with the multi-slope generator and is configured to be controlled by a selection signal so as to selectively output the first slope voltage signal to a corresponding one of the nth slope voltage signals;
the signal source circuit is configured to output a plurality of index signals, the periods of the index signals are equal, and the high-level time duty ratio of the index signals is changed in sequence corresponding to each slope voltage signal;
and the logic processing circuit is respectively connected with the signal source circuit and the comparison circuit at the input end, is connected with the switch selection circuit at the output end, and is configured to correspondingly generate the selection signal to the switch selection circuit based on the swing amplitude of the swing amplitude pulse signal and the index signal.
8. The readout circuit of the image sensor of claim 7, wherein the logic processing circuit comprises:
the first end of each OR gate receives one index signal of the signal source circuit;
the D flip-flops are in one-to-one correspondence with the OR gates, the clock signal end of each D flip-flop is connected with the output end of the comparison circuit, the input end of each D flip-flop is connected with the output end of the corresponding OR gate, and the output end of each D flip-flop is connected with the second end of the corresponding OR gate;
The decoder is respectively connected with the output ends of the D triggers, is configured to convert the logic values output by the D triggers into the selection signals and output the selection signals to the switch selection circuit, and is also configured to feed back the sampling times to the control circuit.
9. The readout circuit of the image sensor of claim 7, wherein the switch selection circuit includes a plurality of first switches controlled by the selection signal;
the first end of each first switch is respectively connected with one of the first slope voltage signal to the n slope voltage signal, and the second end of each first switch is commonly connected with the output end of the switch selection circuit so as to output one of the first slope voltage signal to the n slope voltage signal.
10. The readout circuit of the image sensor according to claim 7, wherein the signal source circuit includes x index signals, and n-x=1.
11. The readout circuit of the image sensor of claim 1, wherein the voltage range corresponding to the mth ramp voltage signal is:
wherein V is R And (3) representing the maximum quantization range of analog-to-digital conversion, wherein m is a positive integer greater than or equal to 1.
12. The readout circuit of the image sensor of claim 1, wherein the ramp voltage signal comprises a first ramp voltage signal, a second ramp voltage signal, a third ramp voltage signal, and a fourth ramp voltage signal;
the voltage range of the first slope voltage signal isThe voltage range of the second ramp voltage signal isThe voltage range of the third slope voltage signal is +.>The voltage range of the fourth ramp voltage signal is +.>The resolution of the first slope voltage signal is the same as that of the second slope voltage signal, the resolution of the third slope voltage signal is 1bit higher than that of the second slope voltage signal, and the resolution of the fourth slope voltage signal is 1bit higher than that of the third slope voltage signal;
wherein V is R Representing the maximum quantization range of the analog-to-digital conversion.
13. The readout circuit of an image sensor according to claim 11 or 12, wherein,
the sampling frequency corresponding to the first slope voltage signal is 2;
the sampling times corresponding to the second slope voltage signal to the nth slope voltage signal are as follows: 2 n -1。
14. An image sensor comprising a pixel array, a control circuit and a plurality of readout circuits of the image sensor according to any one of claims 1 to 13, the pixel array comprising a plurality of pixel cells arranged in an array;
The readout circuit of each image sensor is respectively connected with a plurality of pixel units arranged in a column, and the readout circuits of the image sensors are also respectively connected with the control circuit.
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