CN116644707B - Semiconductor layout design method and semiconductor layout - Google Patents
Semiconductor layout design method and semiconductor layout Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 87
- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000013461 design Methods 0.000 title abstract description 33
- 238000002955 isolation Methods 0.000 claims abstract description 118
- 239000000758 substrate Substances 0.000 claims abstract description 110
- 230000000694 effects Effects 0.000 claims abstract description 29
- 230000003247 decreasing effect Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 27
- 230000007547 defect Effects 0.000 abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 53
- 238000010586 diagram Methods 0.000 description 25
- 239000000463 material Substances 0.000 description 8
- 238000011161 development Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000002310 reflectometry Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/60—Substrates
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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Abstract
The embodiment of the disclosure provides a semiconductor layout design method and a semiconductor layout. The semiconductor layout is divided into a center region and an edge region, the semiconductor layout including a mask layer including a plurality of cell exposure patterns and a substrate layer including an isolation region and a plurality of active regions, the method comprising: and adjusting the area of the unit exposure pattern of the mask layer and/or adjusting the area of the active region and the area of the isolation region of the substrate layer so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect. Thus, the embodiment of the disclosure can improve the defocusing defect during exposure treatment and can also improve the process window of the exposure process.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor layout design method and a semiconductor layout.
Background
With the rapid development of ultra-large-scale integration technology, complementary metal oxide semiconductor (Complementary Metal-Oxide Semiconductor, CMOS) image sensors (CMOS Image Sensor, CIS) can integrate functions such as analog-to-digital conversion (Analogue to Digital conversion, a/D conversion), signal processing, automatic gain control, precision amplification and storage in a single chip, so that system complexity is greatly reduced, and cost is reduced, and development is rapid in recent years.
In CIS devices, a grid-shaped photoresist is mainly used as a barrier layer of a transmission gate (TX tube) N-type well, and a column-shaped photoresist is used as a barrier layer of a TX tube P-type well. With the rapid development of CIS devices, in order to obtain higher image quality and meet the severe requirements of device modules on size, the pixel (pixel) integration level is higher and the pixel pitch size is smaller. However, with the miniaturization of the size, a defocus problem of the edge region of the chip is brought about, affecting the performance of the CIS device.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor layout design method and a semiconductor layout.
In a first aspect, an embodiment of the present disclosure provides a method for designing a semiconductor layout, the semiconductor layout being divided into a center region and an edge region, the semiconductor layout including a mask layer including a plurality of unit exposure patterns and a substrate layer including an isolation region and a plurality of active regions, the method comprising:
and adjusting the area of the unit exposure pattern of the mask layer and/or adjusting the area of the active region and the area of the isolation region of the substrate layer so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect.
In some embodiments, the mask layer is in a grid shape, the unit exposure pattern comprises an exposure area and a reserved area, and the reserved area surrounds the exposure area in a ring shape; adjusting the area of the unit exposure pattern of the mask layer comprises the following steps:
the areas of the exposure area and the reserved area in the edge area are adjusted so that the area of the exposure area in the edge area is larger than the area of the exposure area in the central area.
In some embodiments, adjusting the areas of the exposed and reserved areas at the edge region includes:
increasing the area of the exposure area from an initial exposure area to a target exposure area within the unit exposure pattern located at the edge area; and reducing the area of the reserved area from the initial mask area to a target mask area; such that the area of the exposed area at the edge region is greater than the area of the exposed area at the center region.
In some embodiments, the area of the exposure area is increased from an initial exposure area to a target exposure area; and reducing the area of the reserved area from an initial mask area to a target mask area, comprising:
Increasing the width of the exposure area from the initial exposure area width to the first exposure area width, and decreasing the width of the reserved area from the initial mask width to the first mask width;
wherein the range in which the width of the exposure region is increased and the range in which the width of the reserve region is decreased are: 5-100 nm.
In some embodiments, adjusting the areas of the exposed and reserved areas at the edge region includes:
increasing the width of the reserved area in the edge area from an initial mask width to a target mask width; and increasing the width of the exposure area located in the edge area from an initial exposure area width to a target exposure area width; such that the area of the exposed area at the edge region is greater than the area of the exposed area at the center region.
In some embodiments, adjusting the area of the active region and the area of the isolation region of the substrate layer includes:
increasing the area of the isolation region from an initial isolation area to a target isolation area; and reducing the areas of the plurality of active regions from an initial active area to a target active area such that a ratio of the area of the isolation region to the area of the plurality of active regions in the substrate layer is greater than a preset value.
In some embodiments, the substrate layer includes only isolation regions at edge regions of the substrate layer.
In some embodiments, the isolation region divides the substrate layer into the plurality of active regions; increasing the area of the isolation region from an initial isolation area to a target isolation area; and reducing the area of the plurality of active regions from an initial active area to a target active area, comprising:
reducing the width of the active region from an initial active width to a target active width;
increasing the width of the isolation region from an initial isolation width to a target isolation width;
the width of the isolation region is the width of the isolation region between two adjacent active regions.
In a second aspect, an embodiment of the present disclosure provides a semiconductor layout divided into a center region and an edge region, the semiconductor layout including a mask layer and a substrate layer, the mask layer including a plurality of unit exposure patterns, the mask layer being in a grid shape, the unit exposure patterns including an exposure region and a reserved region, and the reserved region being annularly surrounding the exposure region, the substrate layer including an isolation region and a plurality of active regions, wherein:
In the mask layer, the area of the exposure area positioned in the edge area is larger than that of the exposure area positioned in the central area;
and/or, in the substrate layer, a ratio of an area of the isolation region and an area of the plurality of active regions in the substrate layer is greater than a preset value.
In some embodiments, the area of the exposure area located in the edge region is a target exposure area, the area of the exposure area located in the center region is an initial exposure area, the area of the reserved area located in the edge region is a target mask area, and the area of the reserved area located in the center region is an initial mask area; wherein:
the target exposure area is larger than the initial exposure area, and the target mask area is smaller than the initial mask area.
In some embodiments, the width of the reserved area in the edge area is a first mask width, the width of the reserved area in the central area is an initial mask width, the width of the exposed area in the edge area is a first exposed area width, and the width of the exposed area in the central area is an initial exposed area width; wherein:
The first mask width is smaller than the initial mask width, and the first exposure area width is larger than the initial exposure area width;
wherein a range in which the first mask width is smaller than the initial mask width and a range in which the first exposure region width is larger than the initial exposure region width are: 5-100 nm.
In some embodiments, the width of the reserved area in the edge area is a target mask width, the width of the reserved area in the central area is an initial mask width, the width of the exposed area in the edge area is a target exposed area width, and the width of the exposed area in the central area is an initial exposed area width; wherein:
the target mask width is greater than the initial mask width, and the target exposure area width is greater than the initial exposure area width.
In some embodiments, the substrate layer includes only isolation regions at edge regions of the substrate layer.
In some embodiments, the widths of the active regions in the central region and the edge region of the substrate layer are both target active widths, and the widths of the isolation regions in the central region and the edge region of the substrate layer are both target isolation widths; wherein:
The target active width is smaller than the initial active width, and the target isolation width is larger than the initial isolation width;
the width of the isolation region is the width of the isolation region between two adjacent active regions.
The embodiment of the disclosure provides a semiconductor layout design method and a semiconductor layout, wherein the semiconductor layout is divided into a central area and an edge area, the semiconductor layout comprises a mask layer and a substrate layer, the mask layer comprises a plurality of unit exposure patterns, the substrate layer comprises an isolation area and a plurality of active areas, and the method comprises the following steps: and adjusting the area of the unit exposure pattern of the mask layer and/or adjusting the area of the active region and the area of the isolation region of the substrate layer so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect. In this way, the embodiment of the disclosure improves the design of the mask layer and/or the substrate layer, readjusts the layout, the size and the like of the layout, improves the defocus problem, improves the exposure uniformity of the center region and the edge region, and enables the exposure effect of the center region and the edge region to be basically uniform, so that the process window of the exposure process can be further improved, the realization of the process flow is facilitated, and finally, the performance and the product yield of the CIS device can be further improved.
Drawings
FIG. 1 is a schematic diagram of a layout of a large pitch grid-shaped photoresist;
FIG. 2 is a schematic diagram of a large pitch semiconductor structure;
FIG. 3 is a schematic diagram of a layout of a fine pitch grid-shaped photoresist;
FIG. 4 is a schematic diagram of a small pitch semiconductor structure;
fig. 5 is a flow chart of a method for designing a semiconductor layout according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram I of a substrate layer according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a semiconductor layout according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram ii of a semiconductor layout according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram III of a semiconductor layout according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram II of a substrate layer according to an embodiment of the present disclosure;
fig. 11 is a schematic diagram fourth of a semiconductor layout provided in an embodiment of the disclosure;
FIG. 12 is a schematic diagram III of a substrate layer provided in an embodiment of the present disclosure;
fig. 13 is a schematic diagram five of a semiconductor layout according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the related disclosure and not limiting thereof. It should be further noted that, for convenience of description, only the portions related to the disclosure are shown in the drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.
Fig. 1 shows a schematic diagram of a layout of a large-pitch grid-shaped photoresist, and fig. 2 is a schematic diagram of a semiconductor structure obtained by performing exposure processing according to the layout shown in fig. 1. As shown in fig. 1, the semiconductor layout includes a substrate layer 101 and a mask layer 102, and the mask layer 102 is located on an upper layer of the substrate layer 101, the mask layer 102 includes a plurality of unit exposure patterns 103 arranged in an array, and the unit exposure patterns 103 include a reserved area 1031 and an exposure area 1032, wherein the reserved area 1031 corresponds to an area remained after exposure treatment of a Photoresist (PR), and the exposure area 1032 represents an area removed after exposure treatment of the Photoresist to expose the substrate. In the example shown in fig. 1, the reserved area 1031 includes four sides, and it is understood that adjacent unit exposure patterns 103 share one side of the reserved area 1031.
In the disclosed embodiment, with reference to FIG. 1, several critical dimensions are defined as follows: mask width (line CD, l); exposure area width (space CD, s); pitch size (p, the sum of l and s).
The exposure (PH) is to project the pattern on the mask onto the photoresist by using the illumination after passing through the optical system, so as to realize the pattern transfer, which is one of the important procedures of the photolithography process in the integrated circuit manufacturing. Under the irradiation of light, the molecules undergo chemical reaction, and the pattern left after development is shown in fig. 2.
Taking fig. 1 and 2 as an example, the exposure process is: a photoresist layer is formed over the substrate 201, and then the photoresist layer is exposed according to the mask layer 102 shown in fig. 1, so that the photoresist at the corresponding position of the reserved area 1031 is reserved, and the photoresist at the corresponding position of the exposed area 1032 is removed, thereby obtaining the photoresist layer 202. Here, the photoresist layer 202 is divided into a plurality of photoresist patterns 203 corresponding to fig. 1, the photoresist patterns 203 including a photoresist region 2031 corresponding to the reserved area 1031 and a blank region 2032 corresponding to the exposure area 1032, and one unit exposure pattern 103 corresponding to one photoresist pattern 203.
As shown in fig. 2, for the latticed layout of large pitch (pitch size greater than or equal to 1.0 um), the exposure effect between the portions is uniform during the exposure, and no defect (defect) of defocusing (defocusing) exists in both the edge region and the center region of the chip (chip, mainly referred to herein as substrate). At this time, the photoresist line width is at both the center region and the edge region Blank area width->And photoresist pitch dimension->The design requirements of the layout are basically met.
Fig. 3 is a schematic diagram of a layout of a fine pitch grid-shaped photoresist, and fig. 4 is a schematic diagram of a semiconductor structure obtained by performing exposure processing according to the layout shown in fig. 3. Fig. 3 has a similar composition to fig. 1, and fig. 4 has a similar composition to fig. 2, and will not be described again.
It will be appreciated that fig. 1 and 3 show a schematic view of a portion of a semiconductor layout, and fig. 2 and 4 show a schematic view of a portion of a semiconductor structure, mainly referred to herein as the lower left corner portion. In general, the definition of the edge area of the chip refers to the cell photoresist pattern 203 of 1-20 turns at the outermost periphery of the chip, and as can be seen from fig. 4, defocusing defects are particularly serious at 1-2 turns at the periphery of the semiconductor structure for this example.
As shown in fig. 4, in the lattice-like layout design of small pitch size (pitch size smaller than 1.0 um), in the semiconductor structure obtained after the exposure process, the density of the blank region 2032 (space density) located at the edge region of the chip is smaller than that located at the center region of the chip. Under the same exposure conditions, there is no defocus problem in the center region of the chip with a larger space density, and there is a line CD in the edge region of the chip with a smaller space density (here, refer to the photoresist line width in FIG. 4 ) Gradually increasing, space CD (here refers to blank area width ++in FIG. 4>) Gradually decreasing, it will be appreciated that the photoresist pitch dimension +.>Also, the amount of light entering the edge area is reduced, and there is a defect of defocus.
That is, as the pixel integration of the CIS device is increased, the pitch size of the grid-shaped photoresist is gradually reduced from more than 1um to 0.6um or less, which causes a problem of defocusing at the edge region of the chip, thereby adversely affecting the performance of the CIS device.
Based on this, an embodiment of the present disclosure provides a method for designing a semiconductor layout divided into a center region and an edge region, the semiconductor layout including a mask layer including a plurality of cell exposure patterns and a substrate layer including an isolation region and a plurality of active regions, the method comprising: and adjusting the area of the unit exposure pattern of the mask layer and/or adjusting the area of the active region and the area of the isolation region of the substrate layer so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect. In this way, the embodiment of the disclosure improves the design of the mask layer and/or the substrate layer, readjusts the layout, the size and the like of the layout, improves the defocus problem, improves the exposure uniformity of the center region and the edge region, and enables the exposure effect of the center region and the edge region to be basically uniform, so that the process window of the exposure process can be further improved, the realization of the process flow is facilitated, and finally, the performance and the product yield of the CIS device can be further improved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
In an embodiment of the present disclosure, referring to fig. 5, a flow chart of a method for designing a semiconductor layout according to an embodiment of the present disclosure is shown, as shown in fig. 5, the method may include:
s301: and adjusting the area of the unit exposure pattern of the mask layer and/or adjusting the area of the active region and the area of the isolation region of the substrate layer so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect.
It should be noted that, the method provided by the embodiment of the present disclosure is mainly applied to the design of a latticed layout of a small pitch (for example, the pitch size is smaller than 1 um), and is applied to the earlier process of a CIS device, which may be specifically a front-side illuminated (FSI) CMOS image sensor. By adjusting the semiconductor layout, the edge area of the chip is ensured to be exposed when the exposure treatment is carried out, the required exposure effect is achieved, and the defocusing defect is improved.
Fig. 6 and 7 are schematic diagrams showing a conventional semiconductor layout forming process. Fig. 6 is a schematic diagram of a first substrate layer 40 according to an embodiment of the present disclosure, and fig. 7 is a schematic diagram of a semiconductor layout obtained after forming a mask layer 50 on the basis of fig. 6. In fig. 7 and the following figures, the semiconductor layout is shown by reference numeral 60, and will not be described again.
As shown in fig. 6, the substrate layer 40 includes an active region 401 and an isolation region 402, and other portions, the isolation region 402 divides the substrate layer 40 into a plurality of active regions 401, and the plurality of active regions 401 are arranged in an array. In the drawings of the embodiments of the present disclosure, the plurality of active regions 401 are arranged in a regular array along a first direction and a second direction perpendicular to each other, but the included angle between the first direction and the second direction may be other than 90 ° and not parallel, and the active regions 401 of two adjacent rows may be arranged in a staggered manner, which is only illustrated as an example, but not limited in any way.
In the embodiment of the present disclosure, when the substrate of the real chip is formed according to the substrate layer 40 of the semiconductor layout, the substrate may be a silicon substrate or other suitable substrate material such as a doped or undoped monocrystalline silicon substrate, a polycrystalline silicon substrate, or the like, which is exemplified herein by a silicon substrate. In general, the substrate may be insulated by shallow trench isolation structures (Shallow Trench Isolation, STI) to divide the substrate into a plurality of active areas; the material of the STI may be an insulating oxide such as silicon oxide.
That is, in this embodiment, for an actual semiconductor structure corresponding to a semiconductor layout, the substrate layer 40 corresponds to a substrate of a chip, the active region 401 in the substrate layer 40 corresponds to an active region in the substrate, and the isolation region 402 in the substrate layer 40 may correspond to an STI (or other types of isolation structures are also possible, and only STI is taken as an example here).
In the drawings of the embodiments of the present disclosure, only a part of the semiconductor layout is shown (in fig. 6 and the subsequent drawings, the upper right corner is mainly shown), and in order to clearly describe the solution of the embodiments of the present disclosure, only the position corresponding to the unit exposure pattern 403 of the outermost 5 circles is taken as an edge region of the semiconductor layout, and the position within the unit exposure pattern 403 of the outermost 5 circles is taken as a central region of the semiconductor layout as an example. It can be understood that the edge area may also refer to the position corresponding to the unit exposure pattern 403 with 2-20 circles at the outermost periphery, or may also be the position corresponding to the unit exposure pattern 403 with other circles, which may be specifically determined by combining the requirements and the process in the actual chip design, and the like, and is not limited in any way.
As shown in fig. 6 and 7, for this conventional design, the active region 401 is uniformly distributed in the substrate 40 in both the center region and the edge region of the substrate 40, and the isolation region 402 is uniformly distributed in both the center region and the edge region of the substrate; in the mask layer 50, the distribution of the unit exposure patterns 403 is also uniform in the center region and the edge region.
When a semiconductor structure is prepared according to the semiconductor layout, a substrate is first provided, and an active region and STI are correspondingly formed in the substrate according to the substrate layer 40, then a photoresist (typically, a photoresist, but may also be other mask materials, not specifically limited herein, and only a photoresist is illustrated as an example) is formed over the substrate, and then an exposure process is performed according to the mask layer 50, thereby forming a pattern of the mask layer 50 in the photoresist, and obtaining a photoresist having a mask pattern. For small-pitch grid-shaped layouts below 1um, in the exposure process, the edge area has a defocusing problem (refer to fig. 4), so that the light entering quantity of the edge area is small, the actually obtained pattern does not accord with expectations, the device has defects, and the device with defects cannot normally flow. It will be appreciated that fig. 7 is the same semiconductor layout as fig. 3, except that fig. 7 shows the upper left corner and fig. 3 shows the lower left corner.
Thus, in response to the shortcomings of such conventional designs, embodiments of the present disclosure provide new design solutions to improve the defocus problem by tuning the semiconductor layout.
Note that in the embodiment of the present disclosure, the semiconductor layout is divided into a center region and an edge region, and the semiconductor layout includes the mask layer 50 and the substrate layer 40. The adjustment of the semiconductor layout comprises adjustment of the mask layer 50 and/or adjustment of the substrate layer 40, so that the edge area can achieve the same exposure effect as the central area when the exposure treatment is performed, the defocusing defect of the edge area is improved, and the design requirement is met.
Next, a detailed description will be given of an adjustment scheme of the mask layer 50.
In some embodiments, adjusting the area of the unit exposure pattern 403 of the mask layer 50 may include:
the areas of the exposure region 4032 and the reserve region 4031 located at the edge region are adjusted so that the area of the exposure region 4032 located at the edge region is larger than the area of the exposure region 4032 located at the center region.
It should be noted that, in the embodiment of the disclosure, the mask layer 50 is generally in a grid shape, as shown in fig. 7, the mask layer 50 is composed of a plurality of unit exposure patterns 403, each unit exposure pattern 403 includes an exposure region 4032 and a reserved region 4031, where, when the photoresist in the semiconductor structure is exposed, the photoresist at the corresponding position of the reserved region 4031 is reserved after the exposure, and the photoresist at the corresponding position of the exposure region 4032 is removed after the exposure, so that the photoresist has the mask pattern after the exposure.
It can be seen that the reserved area 4031 surrounds the exposure area 4032, and in the embodiment of the disclosure, the mask layer 50 is in a regular array grid shape along the first direction and the second direction perpendicular to each other, but may also be changed along with the arrangement of the substrate layer 40, where the arrangement of the mask layer 50 is correspondingly changed, and is not limited herein specifically.
It is understood that the reserved area 4031 herein includes 4 sides, and the adjacent unit exposure patterns 403 share 1 side of the reserved area 4031.
As can be seen from the foregoing, the light entering amount of the exposure region 4032 of the edge region is small, resulting in occurrence of a defocus defect. The area of the exposure region 4032 of the edge region may be increased to further increase the light incoming amount of the edge region, so that the edge region may be exploded at the time of performing the exposure process, thereby achieving the same exposure effect (referred to as a preset exposure effect) as the center region to improve the defocus defect.
Here, the preset exposure effect may mean that, in the mask pattern obtained by exposure, the widths of the photoresist lines, the widths of the blank regions, and the photoresist pitch sizes of the center region and the edge region are all substantially the same, or an allowable error range is satisfied, or that the sizes of the blank regions satisfy the uniformity within the error range.
In one implementation, adjusting the areas of the exposed region 4032 and the reserved region 4031 located in the edge region may include:
increasing the area of the exposure region 4032 from the initial exposure area to the target exposure area within the unit exposure pattern 403 located at the edge region; and reducing the area of the reserved region 4031 from the initial mask area to the target mask area; so that the area of the exposure area 4032 at the edge area is larger than the area of the exposure area 4032 at the center area.
Fig. 8 is a schematic diagram ii of a semiconductor layout according to an embodiment of the disclosure on the basis of fig. 6. In this implementation, as shown in fig. 8, in order to increase the area of the exposure regions 4032 located at the edge region, a scheme is adopted in which the basic layout of the unit exposure patterns 403 is unchanged, the reserve regions 4031 are thinned, so that the width of the exposure regions 4032 between the reserve regions 4031 increases, and thus the area of the exposure regions 4032 increases.
Specifically, the area of the exposure area is increased from the initial exposure area to the target exposure area; and reducing the area of the reserved area from the initial mask area to the target mask area may include:
increasing the width of the exposure area from the initial exposure area width to the first exposure area width, and decreasing the width of the reserved area from the initial mask width to the first mask width;
wherein the range in which the width of the exposure region is increased and the range in which the width of the reserve region is decreased are: 5-100 nm.
As an example, as shown in fig. 8, the outline of the unit exposure pattern 403 and the outline of the exposure region 4032 are both square. For the unit exposure pattern 403 located in the center area, it has the same size information as that in the conventional design: the mask width is the initial mask width l0 (the value of which can be about 200-1800 nm), the exposure region width is the initial exposure region width s0 (the value of which can be about 50-500 nm), and the pitch size is the initial pitch size . The area of the unit exposure pattern 403 is the initial pattern area: />The area of the exposure region 4032 is the initial exposure area: />The area of the reserved region 4031 is the initial mask area: />。
For the unit exposure pattern 403 located in the edge region, it has been adjusted to have different size information from the unit exposure pattern 403 in the conventional design: the mask width is a first mask width l1, and the first mask width l1 is smaller than the initial mask width l0 (about 5-100 nm); the width of the exposure area is the first exposure area width s1, and the first exposure area width s1 is larger than the initial exposure area width s0 (about 5-100 nm); the pitch size is a first pitch size. The area of the unit exposure pattern 403 is the target pattern area: />The area of the exposure region 4032 is the target exposureLight area: />The area of the reserved region 4031 is the target mask area: />。
It can be seen that after the adjustment, the area of the exposure region 4032 located in the edge region is larger than that of the exposure region 4032 located in the center region, that is, the position of the reserved region 4031 is unchanged at this time, but the width of the reserved region 4031 is narrowed, so that the area of the exposure region 4032 between the reserved regions 4031 becomes larger. Therefore, when the exposure treatment is carried out, the light inlet quantity of the edge area can be increased, the edge area can be exposed, the exposure effect basically consistent with that of the central area is achieved, and the defocusing defect is improved.
In addition, in fig. 8, the side lengths of the four sides of the exposure region 4032 are all increased, and the area of the exposure region 4032 may be increased by increasing the side lengths of only two sides adjacent to or opposite to each other, and it is understood that the layout of the unit exposure pattern 403 is unchanged, and the area of the reserved region 4031 naturally decreases accordingly. Alternatively, the shapes of the unit exposure patterns 403 and the exposure areas 4032 may be rectangular, parallelogram or other shapes, and the unit exposure patterns 403 and the exposure areas 4032 may have the same or different shapes, and at this time, the area of the exposure areas 4032 may be increased by adjusting the exposure areas 4032 to improve the defocus defect, and the specific adjustment manner is not described again.
In another implementation, adjusting the areas of the exposed region 4032 and the reserved region 4031 located in the edge region may include:
increasing the width of the remaining region 4031 located in the edge region from the initial mask width to the target mask width; and increasing the width of the exposure region 4032 located in the edge region from the initial exposure region width to the target exposure region width; so that the area of the exposure region 4032 located in the edge region is larger than the area of the exposure region 4032 located in the center region;
The width of the reserved area 4031 is the width of the reserved area 4031 located between two adjacent exposure areas 4032.
It should be noted that fig. 9 is a schematic diagram III of a semiconductor layout provided in the embodiment of the present disclosure on the basis of fig. 6. As shown in fig. 9, in this implementation, in order to increase the area of the exposure region 4032 located at the edge region, both the size of the exposure region 4032 and the size of the reserve region 4031 are increased, and also an increase in the area of the exposure region 4032 can be achieved to improve the defocus defect.
As an example, as shown in fig. 9, the outline of the unit exposure pattern 403 and the outline of the exposure region 4032 are both square. The unit exposure pattern 403 located in the center area has the same size information as the unit exposure pattern 403 in the conventional design, and will not be described again.
For the unit exposure pattern 403 located in the edge region, it has been adjusted to have different size information from the unit exposure pattern 403 in the conventional design: the mask width is a target mask width l2, and the target mask width l2 is larger than the initial mask width l0; the exposure area width is a target exposure area width s2, and the target exposure area width s2 is larger than the initial exposure area width s0 (the range where s2 is increased compared with s0 may be about 5 to 100 nm); the pitch size is the target pitch size It will be appreciated that the target pitch dimension p2 is also greater than the initial pitch dimension p0. The area of the unit exposure pattern 403 is: />The area of the exposure region 4032 is: />The area of the reserved area 4031 is: />。
It can be seen that in this implementation, after adjustment, not only the area of the exposure region 4032 at the edge region is larger than the area of the exposure region 4032 at the center region, but also the area of the reserved region 4031 at the edge region is larger than the area of the reserved region 4031 at the center region, and it can be understood that the area of the unit exposure pattern 403 at the edge region is also larger than the area of the unit exposure pattern 403 at the center region. Therefore, when the exposure treatment is carried out, the light inlet quantity of the edge area can be increased, the edge area can be exposed, the exposure effect basically consistent with that of the central area is achieved, and the defocusing defect is improved.
In fig. 9, the side lengths of the four sides of the exposure region 4032 are increased, and the area of the exposure region 4032 may be increased by increasing the side lengths of only two sides adjacent to or opposite to each other, and the same applies to the remaining region 4031. Alternatively, the shapes of the unit exposure patterns 403 and the exposure areas 4032 may be rectangular, parallelogram or other shapes, and the unit exposure patterns 403 and the exposure areas 4032 may have the same or different shapes, and at this time, the area of the exposure areas 4032 may be increased by adjusting the exposure areas 4032 and the reserved areas 4031, so as to improve the defocus defect, and the specific manner will not be repeated.
In addition, in the implementation shown in fig. 8 or 9, when the area of the exposure region 4032 is increased, the width of the exposure region 4032 may be increased by about 5-100nm, and the edge region may be used as a redundant (dummy) portion of the semiconductor layout. The photoresist in the semiconductor structure may be a thick photoresist.
It can be seen that, when the mask layer 50 is modified, the area of the exposure region 4032 may be increased by narrowing the width of the reserved region 4031, or the area of the exposure region 4032 may be increased by increasing both the width of the exposure region 4032 and the width of the reserved region 4031.
In this way, the embodiment of the disclosure increases the area of the exposure region 4032 located in the edge region by adjusting the mask layer 50, so that the light incoming amount of the edge region can be increased, so that the edge region and the center region can achieve a substantially uniform exposure effect when performing exposure processing, thereby improving defocus defects.
Further, in the substrate of the semiconductor structure, the material of the active region is typically silicon, the material of the STI is typically silicon oxide, and as can be seen from examining the data, the reflectivity of silicon to light is typically between 30% and 40% in different wavelength ranges; meanwhile, the reflectivity of silicon oxide to light is basically more than 70% in different wavelength ranges. It can be seen that silicon oxide has a greater reflectivity for light than silicon. The exposure process is that under the irradiation of light, molecules in the photoresist are subjected to chemical reaction, a pattern is left after development, the stronger the light reflecting capability of the material is, the more light is reflected to the photoresist, and thus the thinner the photoresist is left after development; conversely, the weaker the reflective power of the material to light, the less light is reflected onto the photoresist, and thus the thicker the photoresist left after development.
Based on the different characteristics of the different materials for the reflective effects of light, embodiments of the present disclosure may also be adjusted by designing the substrate layer 40 to meet the exposure effect.
Next, a detailed description will be made regarding an adjustment scheme of the substrate layer 40.
In some embodiments, adjusting the area of the active region 401 and the area of the isolation region 402 of the substrate layer 40 may include:
increasing the area of isolation region 402 from the initial isolation area to the target isolation area; and reducing the area of the plurality of active regions 401 from the initial active area to the target active area such that a ratio of the area of the isolation region 402 in the substrate layer 40 to the area of the plurality of active regions 401 is greater than a preset value.
It should be noted that, in the embodiment of the disclosure, the proportion of the isolation region 402 in the substrate layer 40 may be increased, so that, in the semiconductor structure, the reflective capability of the STI corresponding to the isolation region 402 to light is greater than that of the active region, so that, in the edge region during exposure, since the proportion of the STI is increased, more light can be reflected to the photoresist, and the remaining photoresist is thinner than that of the conventional design, so that the edge region can be successfully exposed, thereby satisfying the exposure effect.
It should be further noted that, the initial isolation area refers to the total area of the isolation regions 402 in the semiconductor layout of the conventional design (e.g., fig. 6), and the initial active area refers to the total area of the plurality of active regions 401 in the semiconductor layout of the conventional design.
Here, the test may be performed under an actual exposure environment to determine a preset value that is a ratio of the area of the isolation region 402 to the area of the plurality of active regions 401 in the substrate layer 40 when the edge region reaches an exposure effect substantially identical to the center region.
It should be noted that the adjustment of the substrate layer 40 may be an adjustment of only the edge area or an adjustment of the entire substrate layer 40.
In one implementation, substrate layer 40 includes only isolation regions 402 at the edge regions of substrate layer 40.
It should be noted that fig. 10 is a schematic diagram ii of a substrate layer 40 according to an embodiment of the disclosure. As shown in fig. 10, the central region of the substrate 40 remains in the same layout as the conventional design, but the active region 401 is no longer included in the edge region of the substrate 40, but only the isolation region 402 is included, thereby increasing the duty cycle of the isolation region 402 in the substrate 40, as compared to fig. 6. Fig. 11 is a schematic diagram fourth of a semiconductor layout according to an embodiment of the present disclosure, where the mask layer 50 shown in fig. 11 has the same structure as the mask layer 50 in the conventional design.
Thus, in this implementation, the mask layer 50 is unchanged, but the edge regions of the substrate layer 40 are all provided as isolation layers 402. Therefore, when exposure treatment is carried out, the central area maintains the same exposure effect as the conventional design, and at the edge area, the STI can reflect more light due to stronger reflectivity of light, so that the photoresist is removed much, the remained photoresist is thinner than the photoresist remained at the edge area in the conventional design, the edge area can achieve the exposure effect basically the same as the central area, the edge area is exposed, and the defocusing defect is improved.
In another implementation, the area of isolation region 402 is increased from an initial isolation area to a target isolation area; and reducing the area of the plurality of active regions 401 from the initial active area to the target active area may include:
reducing the width of the active region 401 from an initial active width to a target active width;
increasing the width of isolation region 402 from an initial isolation width to a target isolation width;
wherein the width of the isolation region 402 is the width of the isolation region between two adjacent active regions 401.
It should be noted that, in the embodiment of the present disclosure, a square with the active regions 401 arranged in a regular array is taken as an example, and it is understood that the active regions may be in other shapes or other arrangements, which is not limited in any way.
In the conventional arrangement shown in fig. 6, the width (or side length) of the active regions 401 is referred to as an initial active width a0, and the width of the isolation regions 402 between adjacent active regions 401 is referred to as an initial isolation width h0 of the isolation regions.
Referring to fig. 12, a schematic diagram of a substrate layer 40 obtained by adjusting an active region 401 and an isolation region 402 is shown in fig. 13, and a schematic diagram of a semiconductor layout according to an embodiment of the present disclosure is shown in fig. 12. In this implementation, as shown in fig. 12, both the isolation region 402 and the active region 401 in the substrate layer 40 are tuned, specifically, the width of the active region 401 is reduced and the width of the isolation region 402 is increased. Wherein the width (or side length) of the active region 401 is referred to as a target active width a1, and the target active width a1 is smaller than the initial active width a0; the width of the isolation region 402 between adjacent active regions 401 is taken as a target isolation width h1, and the target isolation width h1 is greater than the initial isolation width h0. It will be appreciated that the area or other suitable unit of measure may also be used as a unit for measuring the dimensions of the active region and the isolation region, and is not particularly limited herein.
In this way, under the condition that the sum of the area of the isolation region 402 and the areas of the plurality of active regions 401 is unchanged, the area of the single active region 401 is reduced, and meanwhile, the area of the isolation region 402 is naturally increased, so that the characteristic that the reflection capacity of the STI to light is larger than that of the active region is utilized, the edge region can be ensured to be successfully exposed, and the required exposure effect is achieved.
In addition, the active region 401 may also have a rectangular, parallelogram or other shape, and at this time, it is only necessary to adjust its size in a similar manner, which will not be described herein.
That is, when the substrate layer 40 is modified to increase the area ratio of the isolation region 402, the central region may be maintained as it is, and the edge regions may be all provided as the isolation region 402; the active region 401 and the isolation region 402 in the substrate layer 40 may be adjusted as a whole, and the area of each active region 401 may be reduced, and the area of the isolation region 402 may be increased to increase the area ratio of the isolation region 402.
Further, the foregoing provides improvements to substrate layer 40 or to mask layer 50, respectively, and a variety of different implementations may be included for either substrate layer 40 or mask layer 50 alone. In practice, only one or more modified implementations for substrate layer 40 may be selected, or only one or more modified implementations for mask layer 50 may be selected, or both one or more modified implementations for substrate layer 40 and one or more modified implementations for mask layer 50 may also be selected, without limitation.
Briefly, an embodiment of the present disclosure provides a method for designing a semiconductor layout, which in one implementation includes: there is a larger area in the device edge area than the device center area space (i.e., the exposure area); specific embodiments thereof include, but are not limited to: (1) increasing pitch size; (2) increasing space CD; (3) enlarging the space area. Wherein increasing pitch size refers to increasing space and line CD simultaneously, and increasing space refers to increasing space CD only. It will be appreciated that (1) and (2) remain substantially enlarged space areas. In another implementation, it includes: the large-area STI region exists at the edge of the device; specific embodiments thereof include, but are not limited to: (1) increasing the area of the STI region; 2) The Area of AA (Active Area) is reduced. Wherein, under the condition that the total area is unchanged, the AA area is reduced and the STI area is increased necessarily; under the condition of unchanged overall layout, the effect of improving defocusing can still be achieved by increasing the size of STI and reducing the size of AA.
In this way, the embodiment of the disclosure can improve the defocusing defect, improve the process window (window) of the PH process, and enable the wafer flow in the process to be normally performed, so that the device performance and the product yield can be improved.
In another embodiment of the present disclosure, on the basis of the foregoing design method, the embodiment of the present disclosure further provides a semiconductor layout, where the semiconductor layout is any one of the semiconductor layouts designed according to the design method provided in the foregoing embodiment.
In some embodiments, a semiconductor layout is divided into a center region and an edge region, the semiconductor layout including a mask layer and a substrate layer, the mask layer including a plurality of unit exposure patterns, the mask layer being in a grid shape, the unit exposure patterns including an exposure region and a reserved region, and the reserved region being in a ring shape surrounding the exposure region, the substrate layer including an isolation region and a plurality of active regions, wherein:
in the mask layer, the area of an exposure area positioned in the edge area is larger than that of an exposure area positioned in the central area;
and/or, in the substrate layer, a ratio of an area of the isolation region and an area of the plurality of active regions in the substrate layer is greater than a preset value.
As shown in fig. 8, in some embodiments, the area of the exposure region 4032 located in the edge region is the target exposure area, the area of the exposure region 4032 located in the center region is the initial exposure area, the area of the reserved region 4031 located in the edge region is the target mask area, and the area of the reserved region 4031 located in the center region is the initial mask area; wherein:
The target exposure area is larger than the initial exposure area, and the target mask area is smaller than the initial mask area.
It should be noted that, taking the example shown in fig. 8 as an example, a specific implementation manner of "the target exposure area is larger than the initial exposure area" may be to taper the width of the reserved area 4031 of the edge area relative to the width of the reserved area 4031 of the central area, so that the width of the exposure area 4032 between the reserved areas 4031 of the edge area becomes larger.
Specifically, the width of the reserved area in the edge area is the first mask width, the width of the reserved area in the central area is the initial mask width, the width of the exposure area in the edge area is the first exposure area width, and the width of the exposure area in the central area is the initial exposure area width; wherein:
the first mask width is smaller than the initial mask width, and the first exposure area width is larger than the initial exposure area width;
wherein, the range of the first mask width smaller than the initial mask width and the range of the first exposure area width larger than the initial exposure area width are: 5-100 nm.
Wherein, the initial exposure area is:the target exposure area is: />The initial mask area is: />The target mask area is: / >，/>，/>Therefore, the target exposure area is larger than the initial exposure area, and the edge area can be exposed when the exposure treatment is carried out, so that the exposure effect basically same as that of the central area is achieved, and the defocusing defect is improved.
It should be further noted that, in the embodiment of the present disclosure, the first mask width may be set to be about 5 to 100nm narrower than the initial mask width, and at the same time, the first exposure area width may be about 5 to 100nm wider than the initial exposure area width. In the adjustment range, the light entering amount in the exposure area is sufficient, and the edge area can be ensured to be successfully exposed.
As shown in fig. 9, in other embodiments, the width of the reserved area 4031 located in the edge area is the target mask width, the width of the reserved area 4031 located in the center area is the initial mask width, the width of the exposed area 4032 located in the edge area is the target exposed area width, and the width of the exposed area 4032 located in the center area is the initial exposed area width; wherein:
the target mask width is greater than the initial mask width and the target exposure area width is greater than the initial exposure area width.
It should be noted that, taking the example shown in fig. 9 as an example, a specific implementation manner of "the target exposure area is larger than the initial exposure area" may be to increase the width of the exposure region 4032 and the width of the reserved region 4031 in the edge region relative to the width of the exposure region 4032 and the width of the reserved region 4031 in the center region, so that the area of the exposure region 4032 in the edge region can be also larger than the area of the exposure region 4032 in the center region.
The initial exposure area width is as follows: s0, the target exposure area width is: s1, the initial mask width is: l0, the target mask width is: l1 is a group of the components,，/>therefore, the target exposure area is larger than the initial exposure area, and the edge area can be exposed when the exposure treatment is carried out, so that the exposure effect basically same as that of the central area is achieved, and the defocusing defect is improved.
Here, the target exposure area width may have the same size as the first exposure area width described above, that is, the target exposure area width may be about 5 to 100nm wider than the initial exposure area width, so as to ensure the light incoming amount of the exposure area, and enable the edge area to be successfully exposed.
As shown in fig. 10 and 11, in some embodiments, substrate layer 40 includes only isolation regions 402 at the edge regions of substrate layer 40.
It should be noted that, the central area of the substrate layer 40 maintains the original layout, and the edge area only includes the isolation area 402, so that when the exposure process is performed, since the reflectivity of the STI to light is stronger, the STI can reflect more light, so that the photoresist is removed much, the remaining photoresist is thinner than the photoresist remaining in the edge area in the conventional design, the edge area can achieve the exposure effect substantially the same as that of the central area, the edge area is exposed, and the defocus defect is improved.
As shown in fig. 12 and 13, in some embodiments, the widths of the active regions 401 at the center region and the edge region of the substrate layer 40 are both target active widths, and the widths of the isolation regions 402 at the center region and the edge region of the substrate layer 40 are both target isolation widths; wherein:
the target active width is smaller than the initial active width, and the target isolation width is larger than the initial isolation width;
wherein the width of the isolation region 402 is the width of the isolation region between two adjacent active regions 401.
It should be noted that, in this implementation manner, the sum of the area of the isolation region 402 and the areas of the plurality of active regions 401 is unchanged, the area of the single active region 401 is reduced, and the area of the isolation region 402 is increased, so that the characteristic that the light reflection capability of the STI is greater than that of the active region is utilized, and the edge region can be ensured to be successfully exposed, so as to achieve the required exposure effect.
For details not disclosed in the embodiments of the present disclosure, please refer to the description of the foregoing embodiments for understanding, and details are not repeated herein.
Briefly, the embodiment of the disclosure is a grid PR layout design based on FSI, and chip edge design is adjusted so as to eliminate defects. Wherein, scheme one (shown in fig. 8 and 9): the novel mask (mask) layout design increases space CD of the chip edge, and increases the light incoming quantity, so that the chip edge can be exposed. Scheme two (fig. 10, 11, 12, and 13): the chip edge is on the STI, and the light reflection is strong by using the STI, so that the chip edge can be exposed. The embodiment of the disclosure can eliminate the defect of the chip edge and improve the process window of PH process.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure.
It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.
The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.
Claims (12)
1. A method of designing a semiconductor layout, wherein the semiconductor layout is divided into a center region and an edge region, the semiconductor layout comprising a mask layer and a substrate layer, the mask layer comprising a plurality of cell exposure patterns, the substrate layer comprising an isolation region and a plurality of active regions, the method comprising:
the area of the unit exposure pattern of the mask layer is adjusted, and the area of the active region and the area of the isolation region of the substrate layer are adjusted, so that when the mask pattern is formed by exposure treatment according to the mask layer, the edge region and the central region both meet the preset exposure effect;
the mask layer is in a grid shape, the unit exposure pattern comprises an exposure area and a reserved area, and the reserved area surrounds the exposure area in a ring shape; adjusting the area of the unit exposure pattern of the mask layer comprises the following steps:
Adjusting the areas of the exposure area and the reserved area in the edge area so that the area of the exposure area in the edge area is larger than the area of the exposure area in the central area;
wherein adjusting the area of the active region and the area of the isolation region of the substrate layer comprises:
increasing the area of the isolation region from an initial isolation area to a target isolation area; and reducing the areas of the plurality of active regions from an initial active area to a target active area such that a ratio of the area of the isolation region to the area of the plurality of active regions in the substrate layer is greater than a preset value.
2. The method of claim 1, wherein adjusting the areas of the exposed and reserved areas at the edge region comprises:
increasing the area of the exposure area from an initial exposure area to a target exposure area within the unit exposure pattern located at the edge area; and reducing the area of the reserved area from the initial mask area to a target mask area; such that the area of the exposed area at the edge region is greater than the area of the exposed area at the center region.
3. The method of claim 2, wherein the area of the exposure area is increased from an initial exposure area to a target exposure area; and reducing the area of the reserved area from an initial mask area to a target mask area, comprising:
increasing the width of the exposure area from the initial exposure area width to the first exposure area width, and decreasing the width of the reserved area from the initial mask width to the first mask width;
wherein the range in which the width of the exposure region is increased and the range in which the width of the reserve region is decreased are: 5-100 nm.
4. The method of claim 1, wherein adjusting the areas of the exposed and reserved areas at the edge region comprises:
increasing the width of the reserved area in the edge area from an initial mask width to a target mask width; and increasing the width of the exposure area located in the edge area from an initial exposure area width to a target exposure area width; such that the area of the exposed area at the edge region is greater than the area of the exposed area at the center region.
5. The method of claim 1, wherein the substrate layer comprises only isolation regions at edge regions of the substrate layer.
6. The method of claim 1, wherein the isolation region divides the substrate layer into the plurality of active regions; increasing the area of the isolation region from an initial isolation area to a target isolation area; and reducing the area of the plurality of active regions from an initial active area to a target active area, comprising: reducing the width of the active region from an initial active width to a target active width;
increasing the width of the isolation region from an initial isolation width to a target isolation width;
the width of the isolation region is the width of the isolation region between two adjacent active regions.
7. A semiconductor layout, characterized in that the semiconductor layout is divided into a central area and an edge area, the semiconductor layout comprises a mask layer and a substrate layer, the mask layer comprises a plurality of unit exposure patterns, the mask layer is in a grid shape, the unit exposure patterns comprise an exposure area and a reserved area, the reserved area surrounds the exposure area in a ring shape, and the substrate layer comprises an isolation area and a plurality of active areas, wherein:
In the mask layer, an area of the exposure region located at the edge region is larger than an area of the exposure region located at the center region, and in the substrate layer, a ratio of an area of the isolation region and an area of the plurality of active regions in the substrate layer is larger than a preset value.
8. The semiconductor layout according to claim 7, wherein an area of the exposure region located at the edge region is a target exposure area, an area of the exposure region located at the center region is an initial exposure area, an area of the reserved region located at the edge region is a target mask area, and an area of the reserved region located at the center region is an initial mask area; wherein:
the target exposure area is larger than the initial exposure area, and the target mask area is smaller than the initial mask area.
9. The semiconductor layout according to claim 8, wherein the width of the reserved area located in the edge area is a first mask width, the width of the reserved area located in the center area is an initial mask width, the width of the exposure area located in the edge area is a first exposure area width, and the width of the exposure area located in the center area is an initial exposure area width; wherein:
The first mask width is smaller than the initial mask width, and the first exposure area width is larger than the initial exposure area width;
wherein a range in which the first mask width is smaller than the initial mask width and a range in which the first exposure region width is larger than the initial exposure region width are: 5-100 nm.
10. The semiconductor layout according to claim 7, wherein the width of the reserved area located in the edge area is a target mask width, the width of the reserved area located in the center area is an initial mask width, the width of the exposure area located in the edge area is a target exposure area width, and the width of the exposure area located in the center area is an initial exposure area width; wherein:
the target mask width is greater than the initial mask width, and the target exposure area width is greater than the initial exposure area width.
11. The semiconductor layout according to claim 7, wherein the substrate layer comprises only isolation regions at an edge region of the substrate layer.
12. The semiconductor layout according to claim 7, wherein the widths of the active regions at the center region and the edge region of the substrate layer are both target active widths, and the widths of the isolation regions at the center region and the edge region of the substrate layer are both target isolation widths; wherein:
The target active width is smaller than the initial active width, and the target isolation width is larger than the initial isolation width; the width of the isolation region is the width of the isolation region between two adjacent active regions.
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