CN116184755A

CN116184755A - Method for forming spliced chip layout and semiconductor structure

Info

Publication number: CN116184755A
Application number: CN202211669152.1A
Authority: CN
Inventors: 臧恺岩
Original assignee: Shanghai IC R&D Center Co Ltd
Current assignee: Shanghai IC R&D Center Co Ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-05-30

Abstract

The invention provides a spliced chip layout and a method for forming a semiconductor structure, which are applied to the technical field of semiconductors. In the spliced chip layout provided by the invention, the spliced patterns with gradually changed line widths are respectively added on two spliced areas (repeated exposure areas) between two adjacent non-spliced areas, then, in the repeated exposure process of positive or negative etching determined by the polarity of the spliced chip layout, the mode of changing the area of the overlapped area after exposure by using the spliced patterns with gradually changed line widths is utilized to offset the problem that the critical dimension of the patterns after development of the spliced patterns with uniform sizes in the conventional process is suddenly changed at the edge of the spliced area, so that the photoetching splicing process of smooth interconnection is realized.

Description

Method for forming spliced chip layout and semiconductor structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a spliced chip layout and a method for forming a semiconductor structure.

Background

In semiconductor integrated circuit processes, chip size is often limited by the single exposure field of view of the lithography machine, which also limits further improvements in chip performance. With the rapid development of applications such as artificial intelligence and vehicle-mounted chips in recent years, higher requirements are being put on high performance and high integration of chips, and the required chip size is also increasing.

Currently, one of the methods for increasing the chip size is to increase the single exposure size of a lithography machine, for example, performing a process using a lithography machine with a larger field of view; the other method is to realize interconnection between adjacent fields by splicing exposure fields based on the original photoetching machine, so that the limitation of single exposure size is broken through, namely, when the chip size exceeds the maximum size of 26mm×33mm of the photomask (the single maximum exposure size of the photoetching machine), the chip size cannot be obtained by a conventional single-step photoetching process, and the chip size is realized by a multi-time zonal photoetching splicing process. Compared with the large-view-field photoetching machine, the scheme of splicing photoetching by adopting the original photoetching machine not only saves the purchase cost, but also has the advantage of keeping the high precision of the photoetching machine.

However, for conventional uniform critical dimension line patterns, the overlapping exposure causes overlapping of the light intensity of the overlapping portions, and as the photosensitive substance or photoacid in the photoresist diffuses, the critical dimension CD of the developed pattern must be increased significantly, especially at the edges of the overlapping portions of the overlapping exposure, which shows abrupt increases in critical dimension CD. For electrical interconnection, as long as the overlapping part and the adjacent distance are ensured to be large enough, the metal wire is in a conducting state, and the CD change of the metal wire only brings about local change of resistance, so that the realization of the electrical interconnection is not influenced. For other forms of interconnects, such as optical waveguides, however, abrupt changes in critical dimensions can result in significant losses in the conducted signals, which is unacceptable for the process.

Disclosure of Invention

The invention aims to provide a novel spliced chip layout and a method for forming a semiconductor structure by using the spliced chip layout, which are used for solving the problem that in the prior art, the key size of a developed pattern is increased and distorted due to the fact that photosensitive substances or photoacid in photoresist are diffused in the photoetching splicing process of a large-size chip.

In order to solve the above technical problems, the present invention provides a spliced chip layout, including:

a plurality of non-spliced regions;

a plurality of splicing areas arranged between two adjacent non-splicing areas;

and the splicing patterns are arranged on each splicing area, and one end of each splicing pattern is connected with the line pattern in the non-splicing area at the junction of the splicing area where the splicing pattern is positioned and the adjacent non-splicing area.

Further, the non-stitching regions may be single-exposure regions, and the stitching regions may be repeated-exposure regions between the single-exposure regions.

Further, the sum of lengths of the plurality of stitching regions disposed between the adjacent two non-stitching regions may be greater than the interval between the exposure positions corresponding to the adjacent two non-stitching regions.

Further, the spliced graph comprises a line graph with gradually changed line width, the line width of the spliced graph at the junction is the same as the line width of the line graph in the non-spliced area connected with the spliced graph, and the line width of the spliced graph is gradually increased or gradually reduced from the junction along the direction away from the line graph in the non-spliced area connected with the spliced graph.

Further, when the polarity of the spliced chip layout is clear, the spliced pattern is a first line pattern which is formed by gradually reducing the line width from the junction along the direction away from the line pattern in the non-spliced area connected with the first line pattern and has a trapezoid shape; and when the polarity of the spliced chip layout is dark, the spliced pattern is a second line pattern which is formed by gradually increasing the line width from the junction along the direction away from the line pattern in the non-spliced area connected with the spliced pattern and has a trapezoid shape.

Further, the line width of the line obtained after the gradual reduction of the first line pattern may be not smaller than a preset mask rule value.

Further, the line width of the line obtained after the gradual increase of the second line pattern may be more than 2 times the line width of the line pattern in the non-spliced region connected thereto.

Further, the graph included angle of the spliced graph can be smaller than 1urad, wherein the graph included angle is the ratio of the line width to the length of the line graph.

Further, the non-splicing areas and the splicing areas are positioned on the same chip layout or on different chip layouts; when the non-spliced areas are positioned on the same chip layout, the non-spliced areas are positioned at two ends of the chip layout, and when the non-spliced areas are positioned on different chip layouts, each chip layout at least comprises a non-spliced area and a spliced area.

In addition, based on the spliced chip layout, the invention also provides a method for forming the semiconductor structure, which comprises the following steps:

providing a semiconductor substrate, and sequentially forming a pattern dielectric layer and a photoresist layer on the surface of the semiconductor substrate;

performing a photoetching splicing process comprising multiple regional exposure based on the spliced chip layout to form an actual layout of the spliced chip corresponding to the spliced chip layout on the photoresist layer;

and etching the pattern dielectric layer and the semiconductor substrate by taking the photoresist layer with the actual layout as a mask so as to transfer the patterns on the spliced chip layout to the semiconductor substrate in a smooth interconnection manner.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

in the spliced chip layout provided by the invention, splicing patterns (repeated exposure areas) with gradually changed line widths are respectively added to two splicing areas positioned between two adjacent non-splicing areas, then, in the repeated exposure process of positive or negative etching determined by the polarity of the spliced chip layout, the mode of changing the area of the overlapped area after exposure by using the splicing patterns with gradually changed line widths is utilized to offset the problem that the critical dimension of the patterns after development of the splicing patterns with uniform sizes in the conventional process is suddenly changed at the edge of the splicing area, so that the photoetching splicing process of smooth interconnection is realized.

Furthermore, in the spliced chip layout provided by the invention, splicing patterns in different gradual change modes are set for spliced chip layouts with different polarities, so that a smooth interconnection pattern can be formed by applying a photoetching splicing process for different diffusion effects (inward diffusion or outward diffusion) of photosensitive substances or photoacid, and the application of the photoetching splicing process is enlarged.

Drawings

Fig. 1 is a schematic diagram of a spliced chip layout when the polarity of the chip layout is clear according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of the spliced chip layout corresponding to fig. 1 after a photolithography splicing process.

Fig. 3 is a schematic diagram of a spliced chip layout when the polarity of the chip layout is dark according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of the spliced chip layout corresponding to fig. 3 after a photolithography splicing process.

Fig. 5 is a flowchart illustrating a method for forming a semiconductor structure based on the spliced chip layout shown in fig. 1 or fig. 3 according to an embodiment of the present invention.

Detailed Description

In order to solve the problems, the invention provides a novel spliced chip layout and a method for forming a semiconductor structure by using the spliced chip layout, so as to solve the problem that in the prior art, the key size of a developed pattern is increased and distorted due to the fact that photosensitive substances or photoacid in photoresist are diffused in the photoetching splicing process of a large-size chip.

The following describes in further detail a new spliced chip layout and a method for forming a semiconductor structure using the spliced chip layout according to the present invention with reference to fig. 1 to 5 and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus. In describing embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present invention herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

The spliced chip layout provided by the invention is first described below.

In practical application, during the process of exposing and developing the photoresist layer by using the chip layout, it can be generally determined according to the type of the photoresist layer, such as positive photoresist or negative photoresist, and the polarity of the chip layout, such as clear and dark, which patterns on the chip layout correspond to the photoresist to expose the photoresist or remove the photoresist.

Based on the above, in the process of providing a spliced chip layout for forming a semiconductor structure of a large-size chip, the inventor can set splicing patterns with different gradual change sizes (line widths) according to the polarity of the chip layout, so as to realize diffusion effects (inward diffusion or outward diffusion) of different photosensitive substances or photoacid, and can apply a photoetching splicing process to form smooth interconnection patterns. Illustratively, in the embodiment of the present invention, the photoresist is positive photoresist, and when the polarity of the chip layout is clear, the light-transmitting area (blank area) in the chip layout represents the area of the photoresist to be removed, and the light-non-transmitting area (shadow area) is the area of the photoresist to be reserved; when the polarity of the chip layout is dark, the transparent and opaque parts of the graph are opposite to the clear polarity. FIG. 1 is a schematic diagram of a spliced chip layout when the polarity of the chip layout is clear according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a structure of the spliced chip layout corresponding to FIG. 1 after a photolithography splicing process; FIG. 3 is a schematic diagram of a spliced chip layout when the polarity of the chip layout is dark according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of the spliced chip layout corresponding to fig. 3 after a photolithography splicing process.

Referring specifically to fig. 1 and fig. 2, as shown in fig. 1, when the polarity of the spliced chip layout is clear, the spliced chip layout provided by the present invention may specifically include:

a plurality of non-spliced regions; illustratively, a first non-stitched area A1 and a second non-stitched area A2 as in fig. 1.

A plurality of splicing areas arranged between two adjacent non-splicing areas; illustratively, as in the first and second spliced regions B1 and B2 of fig. 1, the first spliced region B1 is connected to the first non-spliced region A1, the second spliced region B2 is connected to the second non-spliced region A2, and the first and second spliced regions B1 and B2 are located between the first and second non-spliced regions A1 and A2.

The splicing patterns are arranged on each splicing area, and one end of each splicing pattern is connected with the line pattern in the non-splicing area at the junction of the splicing area where the splicing pattern is positioned and the adjacent non-splicing area; exemplary are a pattern 11 located in the first stitching region B1 and a pattern 12 located in the second stitching region B2 in fig. 1.

Wherein the non-spliced areas such as A1 and A2 are single exposure areas, and the spliced areas such as B1 and B2 are repeated exposure areas between the single exposure areas A1 and A2. Also, the size of a single spliced region B1 or B2 disposed between adjacent two of the non-spliced regions A1 and A2 should be smaller than the interval between the adjacent non-spliced regions A1 and A2, and the sum of the lengths of a plurality of spliced regions B1 and B2 disposed between adjacent two of the non-spliced regions A1 and A2 should be larger than the interval between the exposure positions corresponding to the adjacent two non-spliced regions A1 and A2.

The

spliced patterns

11 and 12 are line patterns with gradually changed line widths, specifically, the

spliced pattern

11 or 12 is a first line pattern which is formed by gradually reducing the line width in a trapezoid shape from the junction between the A1 and the B1 or the A2 and along the direction away from the line pattern in the non-spliced area A1 or the A2, namely, the line width of the

spliced pattern

11 or 12 at the junction is the same as the line width of the line pattern in the non-spliced area A1 or the A2 connected with the same, and the line width of the

spliced pattern

11 or 12 is gradually reduced from the junction along the direction away from the junction. The line width a1 of the line obtained after the gradual reduction of the

first line pattern

11 or 12 is not smaller than a preset mask rule value, preferably, the line width a1 is equal to the preset mask rule value, and the ratio (the pattern included angle size) of the line width a1 of the

first line pattern

11 or 12 to the length b1 is smaller than 1urad.

In this embodiment, each of the non-spliced regions may include at least one linear pattern, such as rectangular patterns A1 and A2 shown in fig. 1; in order to form a smooth interconnection pattern composed of linear patterns in a plurality of non-spliced regions on a photoresist and a semiconductor substrate after multiple partition exposure, the inventor proposes that a spliced pattern with gradually changed line width, such as a

first line pattern

11 or 12, is added on two spliced regions between two adjacent non-spliced regions, and since the

first line patterns

11 and 12 are subjected to pattern superposition during multiple partition exposure, a superposition pattern (in two dotted lines of a superposition region AB) with a hexagonal shape is formed in a blank region as shown in fig. 2, and therefore, the exposure dose of the superposition pattern (in the photoresist, corresponding to the region to be removed) is twice as large as that of other regions, which causes that photosensitive substances or photoacid in the region where the superposition pattern is located can diffuse from high to low along with the concentration gradient; however, in the process of developing the

first line patterns

11 and 12, the closer to the center line position of the superimposed patterns, such as the center line a 'B' in fig. 2, the larger the overlapping region of the patterns is, the larger the concentration gradient of the exposure dose, which causes the diffusion of the photosensitive substance or photoacid to immediately increase the line width of the superimposed patterns, while as the overlapping region is away from the center line, the overlapping region of the patterns is gradually decreased, the concentration gradient of the exposure dose is also gradually decreased, and gradually away from the line edges, which causes the diffusion of the photosensitive substance or photoacid to gradually decrease, and the influence on the line width variation of the line patterns is also reduced, so that the developed

first line patterns

11 and 12 form a concave line pattern, such as the one shown on the right of fig. 2.

Referring specifically to fig. 3 and fig. 4, as shown in fig. 3, when the polarity of the spliced chip layout is dark, the spliced chip layout provided by the present invention may specifically include:

a plurality of non-spliced regions; illustratively, a first non-splice area C1 and a second non-splice area C2 as in fig. 3.

A plurality of splicing areas arranged between two adjacent non-splicing areas; illustratively, as in fig. 3, the first stitching region D1 is connected to the first non-stitching region C1, the second stitching region D2 is connected to the second non-stitching region C2, and the first stitching region D1 and the second stitching region D2 are located between the first non-stitching region C1 and the second non-stitching region C2.

The splicing patterns are arranged on each splicing area, and one end of each splicing pattern is connected with the line pattern in the non-splicing area at the junction of the splicing area where the splicing pattern is positioned and the adjacent non-splicing area; illustratively, a pattern 21 located in the first stitching region D1 and a pattern 22 located in the second stitching region D2 are shown in fig. 3.

Wherein the non-stitching regions such as C1 and C2 are single exposure regions, and the stitching regions such as D1 and D2 are repeat exposure regions between the single exposure regions C1 and C2. And, the size of a single stitching region D1 or D2 disposed between adjacent two of the non-stitching regions C1 and C2 should be smaller than the interval between the adjacent non-stitching regions C1 and C2, and the sum of the lengths of a plurality of stitching regions D1 and D2 disposed between adjacent two of the non-stitching regions C1 and C2 should be greater than the interval between the exposure positions corresponding to the adjacent two non-stitching regions C1 and C2.

The

stitching patterns

21 and 22 are line patterns with gradually changing line widths, and in particular, the

stitching patterns

21 and 22 are second line patterns with trapezoid shapes, which are formed by gradually increasing line widths from the junction between the C1 and the D1 or between the C2 and the D2, along the direction away from the line patterns in the non-stitching region C1 or the C2. The line width c1 of the line obtained after the gradual increase of the

second line pattern

21 or 22 is more than 2 times that of the line pattern in the non-spliced area connected with the line pattern, that is, may be more than 2 times, 2.1 times, 3 times, 3.12 times, 4 times, and the like, and as a preferable example, the value of N is 3, and the ratio (the size of the pattern included angle) of the line width c2 of the

second line pattern

21 or 22 to the length d2 is less than 1urad.

In this embodiment, since the

second line patterns

22 and 22 are superimposed during the multiple-partition exposure of the chip layout, and thus a superimposed pattern (particularly, two dotted lines in the overlapping area CD) with a hexagonal shape is formed, in which the sharp corners in the shadow area are eliminated by the exposure in the opposite positions as shown in fig. 4, and at this time, since the blank areas in fig. 3 and 4 are exposure development areas, the exposure dose in the blank areas on both sides of the superimposed pattern may be diffused in the line inner directions of the superimposed pattern, so that the sharp corners of the superimposed pattern in the shadow area are compressed inwards to become smooth arcs, that is, the developed

second line patterns

21 and 22 form an outward convex line pattern, as shown in fig. 4.

It will be understood that the spliced chip layouts shown in fig. 1 and fig. 3 are exemplary in which a non-spliced region, a plurality of spliced regions, and a spliced pattern are formed on different chip layouts, and in other embodiments, the spliced chip layout provided by the present invention in which a spliced pattern with gradually-changed line width is added to two spliced regions between two adjacent non-spliced regions may also be located on the same chip layout, which will not be described in detail.

In addition, the invention further specifically provides a spliced chip layout containing the spliced graph shown in fig. 1 or fig. 3 formed on the original spliced chip layout, which specifically comprises the following steps:

step S1, providing an original spliced chip layout, and determining different functional areas on the original spliced chip layout to form a plurality of non-spliced areas and a plurality of spliced areas, such as a first non-spliced area, a first spliced area, a second non-spliced area and a second spliced area.

And S2, confirming the line width of the line patterns in the non-splicing area and the maximum angle of the allowed pattern included angle of the splicing patterns which can be formed in the splicing area.

And S3, forming a splicing pattern with gradually changed line width on each splicing area according to splicing requirements, wherein the line width of the splicing pattern at the junction is the same as the line width of the line pattern in the non-splicing area connected with the splicing pattern, and the line width of the splicing pattern is gradually increased or gradually reduced from the line width at the junction in the direction away from the line pattern in the non-splicing area connected with the splicing pattern.

The maximum angle of the pattern included angle allowed by the spliced pattern is the maximum angle allowed by the expected spliced chip, and the maximum angle allowed by the expected spliced chip is larger than or equal to the inclination angle formed by the line width reduction of the spliced pattern on a photoetching plate (spliced chip layout) and larger than or equal to the inclination angle of two sides of a line formed by the actual splicing on a silicon wafer (semiconductor substrate).

In this embodiment, when the polarity of the spliced chip layout is clear, the spliced pattern is a first line pattern with a trapezoid shape, which is formed by gradually reducing the line width from the junction along a direction away from the line pattern in the non-spliced area connected with the spliced pattern, and the line width of the line obtained after the gradual reduction of the first line pattern should be designed to be the minimum feature size allowed by the design rule (design rule), namely, a mask rule value; when the polarity of the spliced chip layout is dark, the spliced pattern is a second line pattern which is formed by gradually increasing the line width from the junction and along the direction away from the line pattern in the non-spliced area connected with the junction, and the line width of the line obtained after the gradual increase of the second line pattern is 3 times of the line width of the line pattern in the non-spliced area connected with the second line pattern.

And the size of the included angle of the first line pattern or the second line pattern is smaller than the allowable maximum angle, namely 1urad.

Furthermore, in the spliced chip layout based on the above-mentioned fig. 1 and 3, the invention also provides a method for forming a semiconductor structure by using the spliced chip layout.

Referring specifically to fig. 5, fig. 5 is a flowchart illustrating a method for forming a semiconductor structure using the spliced chip version shown in fig. 1 or fig. 3 according to an embodiment of the present invention. As shown in fig. 5, the forming method includes the steps of:

step S501, providing a semiconductor substrate, and sequentially forming a pattern dielectric layer and a photoresist layer on the surface of the semiconductor substrate;

step S502, performing photoetching splicing process comprising multiple regional exposure based on the spliced chip layout as described in the above figure 1 or figure 3 to form an actual layout of the spliced chip corresponding to the spliced chip layout on the photoresist layer;

and step S503, etching the pattern dielectric layer and the semiconductor substrate by taking the photoresist layer with the actual layout as a mask, so as to transfer the patterns on the spliced chip layout to the semiconductor substrate in a smooth interconnection manner.

The actual layout size of the spliced chip is larger than 26mm multiplied by 33mm.

In this embodiment, the photolithography stitching process performs exposure on each exposure area of the stitched chip layout one by one, so as to sequentially transfer the patterns of each exposure area in the stitched chip layout to a target wafer, and stitch the patterns of adjacent exposure areas in the corresponding area on the semiconductor substrate, thereby forming an actual layout of the stitched chip with the stitching, as shown in fig. 2 or fig. 4.

It should be noted that, in the step S501, a photoresist layer may be formed on the surface of the semiconductor substrate, or an etching intermediate layer and a photoresist anti-reflection layer may be deposited and formed before the photoresist layer is formed as required, and then the non-spliced pattern and the spliced pattern are sequentially transferred to the photoresist layer, the pattern dielectric layer and the semiconductor substrate by using the designed spliced chip layout to perform photolithography and etching processes; thereafter, the photoresist layer and other possible auxiliary layers on the patterned dielectric layer are removed.

In summary, in the spliced chip layout provided by the invention, the spliced patterns (repeated exposure areas) with gradually changed line widths are respectively added to two spliced areas between two adjacent non-spliced areas, and then, in the multiple exposure process of positive or negative etching determined by the polarity of the spliced chip layout, the mode of changing the area of the overlapped area after exposure by using the spliced patterns with gradually changed line widths is utilized to offset the problem that the critical dimension of the patterns after development of the spliced patterns with uniform size in the conventional process is suddenly changed at the edge of the spliced area, so that the photoetching splicing process of smooth interconnection is realized.

It should be noted that although the present invention has been disclosed in the preferred embodiments, the above embodiments are not intended to limit the present invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.

It should be further understood that the terms "first," "second," "third," and the like in this specification are used merely for distinguishing between various components, elements, steps, etc. in the specification and not for indicating a logical or sequential relationship between the various components, elements, steps, etc., unless otherwise indicated.

It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses, and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood as having the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates the contrary. Furthermore, implementation of the methods and/or apparatus in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. The utility model provides a splice chip territory which characterized in that includes:

a plurality of non-spliced regions;

a plurality of splicing areas arranged between two adjacent non-splicing areas;

2. The stitched chip layout of claim 1, wherein the non-stitched regions are single exposure regions and the stitched regions are repeat exposure regions between the single exposure regions.

3. The spliced chip layout according to claim 2, wherein a sum of lengths of a plurality of spliced regions disposed between two adjacent non-spliced regions is larger than a space between exposure positions corresponding to the two adjacent non-spliced regions.

4. The spliced chip layout according to claim 1, wherein the spliced pattern includes a line pattern in which a line width is gradually changed, the line width of the spliced pattern at the boundary is the same as the line width of the line pattern in the non-spliced region connected thereto, and the line width of the spliced pattern is gradually increased or gradually decreased from the boundary in a direction away from the line pattern in the non-spliced region connected thereto.

5. The spliced chip layout according to claim 4, wherein when the polarity of the spliced chip layout is clear, the spliced pattern is a first line pattern which is formed by gradually reducing the line width from the junction along a direction away from the line pattern in a non-spliced area connected with the junction and has a trapezoid shape; and when the polarity of the spliced chip layout is dark, the spliced pattern is a second line pattern which is formed by gradually increasing the line width from the junction along the direction away from the line pattern in the non-spliced area connected with the spliced pattern and has a trapezoid shape.

6. The spliced chip layout according to claim 5, wherein the line width of the line obtained after the gradual reduction of the first line pattern is not smaller than a preset mask rule value.

7. The spliced chip layout according to claim 5, wherein the line width of the line obtained after the gradual increase of the second line pattern is more than 2 times the line width of the line pattern in the non-spliced region connected thereto.

8. The spliced chip layout according to claim 6 or 7, wherein a pattern included angle of the spliced pattern is smaller than 1urad, wherein the pattern included angle is a ratio of a line width to a length of a line pattern.

9. The stitched chip layout of claim 1, wherein the plurality of non-stitched regions and the plurality of stitched regions are located on the same chip layout or on different chip layouts; when the non-spliced areas are positioned on the same chip layout, the non-spliced areas are positioned at two ends of the chip layout, and when the non-spliced areas are positioned on different chip layouts, each chip layout at least comprises a non-spliced area and a spliced area.

10. A method of forming a semiconductor structure, comprising the steps of:

performing a photolithographic stitching process comprising a plurality of regional exposures based on the stitched chip layout of any one of claims 1-9 to form an actual layout of a stitched chip on a photoresist layer corresponding to the stitched chip layout;