CN116450570B

CN116450570B - 32-bit RISC-V processor based on FPGA and electronic equipment

Info

Publication number: CN116450570B
Application number: CN202310725778.8A
Authority: CN
Inventors: 杨海波; 姜贺亮; 赵承心; 牛晓阳; 李先勤; 韩维佳; 谢昊青
Original assignee: Guangdong Provincial Laboratory Of Advanced Energy Science And Technology; Institute of Modern Physics of CAS
Current assignee: Guangdong Provincial Laboratory Of Advanced Energy Science And Technology; Institute of Modern Physics of CAS
Priority date: 2023-06-19
Filing date: 2023-06-19
Publication date: 2023-10-17
Anticipated expiration: 2043-06-19
Also published as: CN116450570A

Abstract

The application discloses a 32-bit RISC-V processor based on FPGA and an electronic device, wherein the processor comprises: at least one soft core having a 32-bit RISC-V architecture; the bus is in communication connection with the soft core and is used for carrying out connection communication with external equipment; the soft core comprises an instruction fetching module, a decoding module, an executing module, a memory accessing module and a write-back module which are sequentially connected and form a five-stage pipeline control mode; the bus comprises a bus controller, and the bus controller enables the soft core to be connected and communicated with external equipment through the bus in a bus control mode based on one master and multiple slaves. The application can improve the data processing efficiency of the RISC-V processor from the whole system angle, and after the 32-bit five-stage pipeline soft core processor adopting the RISC-V open source instruction architecture is deployed on the FPGA chip, the SOC can be quickly built through the interaction of the bus and the on-board resources, thereby improving the research and development efficiency.

Description

32-bit RISC-V processor based on FPGA and electronic equipment

Technical Field

The application relates to the field of computing architecture, in particular to a 32-bit RISC-V processor based on FPGA and electronic equipment.

Background

In recent years, with the development of fields such as aerospace, automobile electronics and the like, the use of microcontrollers is becoming more and more widespread. In addition to open sources, RISC-V instruction architecture developers and maintainers, after summarizing the reduced instruction set development over the past decades, have refined the modular, incremental, de-redundant RISC-V instruction set specification, which is another significant advantage of RISC-V instruction architecture.

However, the existing RISC-V open source instruction architecture usually adopts single cycle control, and because the whole flow from instruction fetch to write-back of an instruction is mostly combinational logic, a certain delay is generated in the data flow. Meanwhile, because the bus control of the processor of the architecture is relatively complex, the bus transmission delay is larger, and the system restriction occurs due to the further limitation of the bus speed under the existing instruction processing mode, so that the overall data processing speed of the processor adopting the RISC-V open source instruction architecture is difficult to improve.

Disclosure of Invention

The application provides a 32-bit RISC-V processor based on an FPGA and electronic equipment, which can improve the data processing efficiency of the 32-bit RISC-V processor based on the FPGA.

In a first aspect, the present application discloses a 32-bit RISC-V processor based on an FPGA, the processor comprising: at least one soft core having a 32-bit RISC-V architecture; and

the bus is in communication connection with the soft core and is used for carrying out connection communication with external equipment;

the soft core comprises a fetching module, a decoding module, an executing module, a memory access module and a write-back module which are sequentially connected and form a five-stage pipeline control mode;

the bus comprises a bus controller, and the bus controller enables the soft core to be connected and communicated with external equipment through the bus in a bus control mode based on one master and multiple slaves; the bus control mode at least comprises the following steps:

predefining an external device address for an external device, wherein the external device address is used as a unique access identifier of the external device;

the method comprises the steps of obtaining a bus address signal, and matching the bus address signal with an external device address;

determining corresponding target external equipment according to the external equipment address successfully matched;

accessing the target external equipment and realizing data transmission.

In an embodiment, the finger fetching module further comprises:

and the prefetching instruction submodule is used for preprocessing an instruction which is read and enters the soft core.

In an embodiment, the pre-fetching sub-module is specifically configured to:

acquiring bit information of a preset position in a preprocessing instruction, and judging whether the preprocessing instruction is a branch jump instruction or not according to the bit information;

if yes, generating a jumped instruction address corresponding to the preprocessing instruction, and pre-reading the next preprocessing instruction.

In an embodiment, the soft core further comprises:

and the pipeline control module is used for carrying out pipeline control through the independent hot code.

In an embodiment, the instruction fetching module, the decoding module, the executing module, the memory accessing module and the write-back module are all provided with enabling ends;

the assembly line control module is connected with the enabling end and is used for controlling the on-off of the instruction fetching module, the decoding module, the executing module, the memory access module and the write-back module by taking the independent thermal code as an enabling signal.

In an embodiment, the bus address signal is provided with a flag bit, and the matching the bus address signal with an address of an external device includes:

and matching the marking bit in the bus address signal with an external device address.

In one embodiment, the bus address signal is an 8-bit signal and the tag bit is the upper four bits.

In an embodiment, the accessing the target external device and implementing data transmission includes:

when the target external device is a RAM, transmitting a write enable signal of the soft core as a write enable signal of the RAM;

and assigning the data returned by the RAM to a bus as output to be transferred to the soft core.

In an embodiment, the bus further comprises a multiplexer, and the soft core is connected to the external device through the multiplexer.

In an embodiment, the external device comprises at least one of ROM, RAM, UART and GPIO.

In an embodiment, the soft core further comprises an arithmetic operation unit.

The application also includes an FPGA-based electronic device comprising an FPGA-based 32-bit RISC-V processor as described in any of the above.

From the above, the 32-bit RISC-V processor and the electronic device based on the FPGA can improve the data processing efficiency of the RISC-V processor from the whole system angle by the improved design of the soft core matching of the five-stage pipeline control mode to the bus control, and the 32-bit five-stage pipeline soft core processor adopting the RISC-V open source instruction architecture is deployed on the FPGA chip and then interacted with the on-board resources through the bus, so that the SOC can be quickly built and the research and development efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of an architecture of an FPGA-based 32-bit RISC-V processor according to an embodiment of the present application.

FIG. 2 is a schematic diagram of another architecture of an FPGA-based 32-bit RISC-V processor according to an embodiment of the present application.

Fig. 3 is a partial bus structure diagram according to an embodiment of the present application.

Fig. 4 is a timing diagram of a bus control method according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical scheme of the application is further described below with reference to the accompanying drawings and examples.

Referring to fig. 1, an architecture of a 32-bit RISC-V processor based on FPGA according to an embodiment of the present application is shown.

The 32-bit RISC-V processor based on the FPGA comprises at least one soft core 1 and a bus 2 which is in communication connection with the soft core 1.

The soft core 1 can have a 32-bit RISC-V architecture, and particularly can adopt a soft core 1 designed by a RISC-V open source instruction architecture subset RV32I instruction set; the soft core 1 is based on FPGA hardware, and the purpose of quickly constructing the SOC is realized by utilizing the interaction between the bus 2 and the on-board resources on the basis of the FPGA hardware.

The bus 2 is used for connection communication with external devices; the external device may include at least one of a ROM (Read-Only Memory), a RAM (random access Memory ), a UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter), and a GPIO (General-purpose input/output port), among others. The general external device at least includes ROM and RAM, and may further be equipped with other communication interfaces or communication modules, or other functional modules, which is not limited herein.

The soft core 1 includes a fetching module 11, a decoding module 12, an executing module 13, a memory access module 14 and a write-back module 15, which are sequentially connected and form a five-stage pipeline control mode, wherein instructions are transferred to the fetching part through the bus 2 by means of the five-stage pipeline control mode, and then are translated by the decoding module 12, and then are executed to determine whether memory access and write-back are needed. The application decomposes the processing period to obtain higher processing speed of the instructions or the data, and reduces the problem of overlarge delay caused by different occupation of resources of different instructions or data. Specifically, in the instruction processing process, if the first instruction is fetched by the instruction fetching module 11, the instruction fetching module 11 may switch to the decoding module 12 to execute the decoding stage, and then the instruction fetching module 11 may perform the instruction fetching operation on the next instruction. By the hierarchical mode, the processing efficiency of the instruction can be improved under the condition of limited hardware resources.

Referring to FIG. 2, another architecture of an FPGA-based 32-bit RISC-V processor provided by an embodiment of the present application is shown.

As shown in FIG. 2, the pipeline of the soft core 1 mainly comprises a finger fetching module, a decoding module, an executing module, a memory accessing module and a writing back module, and meanwhile, a register file, a control status register, each inter-stage buffer, a conflict arbitration module, a multiplexer, a program counter and a pipeline control module for controlling pipeline blocking are also involved in the soft core 1 of the processor, and an interrupt module for performing interrupt control arbitration is also provided.

The inter-level cache comprises an instruction fetching decoding inter-level cache, an instruction decoding executing inter-level cache, an access storage inter-level cache and an access storage write-back inter-level cache, wherein different inter-level caches are used for storing instruction information obtained after processing by the previous module.

In one embodiment, the pipeline control module is configured to pipeline control via a single hot code. The pipeline control mode is used for respectively carrying out on-off control on each pipeline stage in a form of a single thermal code, the single thermal code can reduce the error probability of a signal jump process, and a pipeline control module is arranged to coordinate the work of each pipeline stage, so that the processing efficiency of instructions is improved.

Furthermore, the instruction fetching module, the decoding module, the executing module, the access memory module and the write-back module are all provided with enabling ends, and the pipeline control module is connected with the enabling ends and used for respectively controlling the on-off of the instruction fetching module, the decoding module, the executing module, the access memory module and the write-back module by taking the independent hot code as an enabling signal. Compared with the traditional design that the enabling signals for controlling the on-off of the pipeline stages are independently added in each stage of pipeline, the occupation of hardware resources can be reduced by arranging the pipeline control module.

In another embodiment, the instruction fetch module may further include a prefetch instruction sub-module for preprocessing instructions fetched into the soft core 1. The preprocessing here includes pre-reading the next instruction, and also includes pre-generating the instruction address to be skipped. The pre-fetching instruction sub-module can pre-process the branch jump instruction of the instruction in advance, so that the processing and executing efficiency of the subsequent instruction can be further improved, and the processing efficiency of the processor is further improved.

Specifically, the prefetch finger submodule is specifically configured to: acquiring bit information of a preset position in the preprocessing instruction, and judging whether the preprocessing instruction is a branch jump instruction according to the bit information; if yes, generating a jumped instruction address corresponding to the preprocessing instruction, and pre-reading the next preprocessing instruction.

In the soft core 1 of the processor with the five-stage pipeline structure, at least five clock cycles are required for executing one instruction, for a branch jump instruction, if the next instruction is fetched after waiting for the execution, a plurality of clocks are obviously wasted, and by introducing the pre-fetching instruction sub-module, whether the branch jump occurs or not, the next instruction is read out of the instruction register in advance and is used by the next pipeline stage, so that the throughput rate of the pipeline is improved.

In one embodiment, the bus 2 includes a bus controller that enables the soft core 1 to communicate with external devices through the bus 2 by way of a master-multi-slave based bus 2 control. The bus 2 control method at least comprises:

predefining an external device address for the external device, the external device address being used as a unique access identifier for the external device; the acquired bus 2 address signal is matched with an external device address; determining corresponding target external equipment according to the external equipment address successfully matched; accessing the target external device and realizing data transmission.

Wherein the external device may include ROM, RAM, UART and at least one of GPIOs. For example, the common external device includes at least ROM and RAM, and may further mount other communication interfaces or communication modules, or other functional modules, which is not limited herein.

The bus 2 control mode of one master and multiple slaves, namely the soft core 1 of the processor is used as a master, and other external devices are used as slaves. The soft core 1 of the processor has control over the bus 2 and accesses to specific external devices are completed by assigning unique and fixed addresses to the external devices.

Specifically, the external device address may be predefined for the external device, and after the external device is connected to the processor for communication, the processor executes a corresponding program to assign an external device address that can be used for communication to the external device, for example: 0x0000_0000 corresponds to ROM in the peripheral device; 0x1000_0000 corresponds to the RAM in the peripheral device; 0x2000_0000 corresponds to UART in peripheral device; 0x3000—0000 corresponds to GPIO in a peripheral device. The above manner is merely an example, and actually, address setting may be performed as needed, and binding of the address with an external device may be performed.

In some embodiments, the bit width of the custom bus 2 is 16 bits, and the address of the slave device controlled by the processor is represented by the upper four bits, while in this embodiment, four external devices may be mounted, and in actual use, according to specific situations, additional peripheral addresses may be allocated to complete the control of other external devices. The specific external device control mode is that the soft core 1 of the RISC-V processor passes through the system customized bus 2, and various peripheral devices can only respond to various commands sent from the soft core 1 of the processor, so that each peripheral device needs to define a fixed address in advance as a specific access identifier of the soft core 1 of the processor to the specific peripheral device.

In this embodiment, with reference to fig. 3 to 4, a timing sequence of a part of a bus structure and a bus control method provided by the embodiment of the present application is shown.

The bus structure may be implemented in a control manner of a Multiplexer (MUX), as shown in fig. 3, including an input multiplexer and an output multiplexer, where the input multiplexer is connected to a soft-core input channel and to a read-only memory (ROM), a Random Access Memory (RAM), a universal asynchronous receiver/transmitter (UART), and a general purpose input/output port (GPIO). The output multiplexer is connected to the soft-core output channel and to a Read Only Memory (ROM), a Random Access Memory (RAM), a Universal Asynchronous Receiver Transmitter (UART), and a general purpose input/output port (GPIO). Of course, other bus structures may be used and the application is not limited in this regard.

The custom bus allocates address space for the external device: 0x0000_0000 corresponds to ROM in the peripheral device; 0x1000_0000 corresponds to the RAM in the peripheral device; 0x2000_0000 corresponds to UART in peripheral device; 0x3000—0000 corresponds to GPIO in a peripheral device. As can be seen clearly from the address space allocation, the bus can distinguish the specific external device accessed by the processor's soft core from the upper four bits of the address.

As shown in fig. 4, where the system signal includes a system clock signal (sys_clk) and a system bus address signal (cpu_sysbus_addr), when the upper four bits input from the soft core of the 32-bit processor of the bus arbitration module to the system bus address signal (cpu_sysbus_addr) are 4' h0000, the peripheral device to be accessed is a ROM, and at this time, the data (rom_data) returned by the ROM is assigned to the system bus data output signal (cpu_sysbus_data_o) as an output; when the upper four bits of the input soft core to system bus address signal (cpu_sysbus_addr) of the 32-bit processor of the bus arbitration module are 4'h0001 (or are written as 32' h 0001), the accessed peripheral device is a RAM, at this time, the processor write enable signal (cpu_sysbus_ wen) of the soft core is transferred to the random access memory write enable signal (ram_ wen) of the RAM, and at the same time, the random access memory data signal (ram_data) returned by the RAM is assigned to the system bus data output signal (cpu_sysbus_data_o) as an output; when the upper four bits of the input from the soft core of the 32-bit processor of the bus arbitration module to the system bus address signal (cpu_sysbus_addr) are 4'h0002 and 4' h0003, the control modes of the UART and the GPIO are respectively the same as the control modes of the two external devices, and are not repeated. Furthermore, because the peripheral specifically accessed by the 16-bit custom bus address is determined by the highest four bits, the custom bus can realize expansion of 16 slave devices at most.

It can be understood that the above-mentioned identification and matching method of the instruction address is only one implementation method, and those skilled in the art can customize the above-mentioned parameters according to actual situations, so as to ensure that the bus address signal matches with the peripheral address of the external device. According to the bus design and bus control method, the integrated circuit of the custom bus in practical application has the characteristics of small area, resource saving and redundancy elimination through simple input and output and control by only simple combination logic, and can save enough FPGA on-chip resources to realize other functions in practical application.

In addition, the soft core of the processor is fetched from the instruction register and needs to be interacted through the bus, and because the processor is built on the FPGA, the FPGA-mounted ROM is used as the instruction register, the FPGA-mounted RAM is used as the cache of the soft core of the processor, and in order to complete the interaction communication between the soft core of the processor and the outside, the UART controller is mounted on the bus, so that the parallel data of the CPU bus can be conveniently converted into serial data, and then the serial data is sent to the UART receiving end of other equipment. Because the SOC area is relatively small in the application, in some industrial control fields, soft cores of a plurality of processors can be deployed on one FPGA chip, and data interaction among multiple cores can be performed by means of serial ports on a bus.

From the above, the 32-bit RISC-V processor based on the FPGA can improve the data processing efficiency of the RISC-V processor from the whole system angle by the improved design of the soft core matching of the five-stage pipeline control mode to the bus control, and the 32-bit five-stage pipeline soft core processor adopting the RISC-V open source instruction architecture is deployed on the FPGA chip and then interacted with the on-board resources through the bus, so that the SOC can be quickly built and the research and development efficiency is improved.

Referring to fig. 5, a structure of an electronic device according to an embodiment of the present application is shown, where the electronic device 100 includes the FPGA-based 32-bit RISC-V processor 10 according to any one of the above.

The FPGA-based 32-bit RISC-V processor 10 may perform various appropriate actions and processes according to a program stored in a Memory, that is, a program stored in a Read-Only Memory (ROM) or a program loaded from a storage part into a random access Memory (Random Access Memory, RAM), for example, performing the method in the above-described embodiment:

predefining an external device address for an external device, wherein the external device address is used as a unique access identifier of the external device; the method comprises the steps of obtaining a bus address signal, and matching the bus address signal with an external device address; determining corresponding target external equipment according to the external equipment address successfully matched; accessing the target external equipment and realizing data transmission.

In the RAM, various programs and data required for the system operation are also stored. The FPGA-based 32-bit RISC-V processor 10, memory and are connected to each other by a bus. An Input/Output (I/O) interface is also connected to the bus.

In some embodiments, the following components may be connected to the I/O interface: an input section including a keyboard, a mouse, etc.; an output section including a liquid crystal display (Liquid Crystal Display, LCD) or the like and a speaker or the like; a storage section including a hard disk or the like; and a communication section including a network interface card such as a LAN (Local AreaNetwork ) card, a modem, or the like. The communication section performs communication processing via a network such as the internet.

From the above, the electronic device based on the FPGA can improve the data processing efficiency of the RISC-V processor from the whole system, and the 32-bit five-stage pipeline soft core processor adopting the RISC-V open source instruction architecture is deployed on the FPGA chip, and the SOC can be quickly built through the interaction of the bus and the on-board resources, so that the research and development efficiency is improved.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.

It should be understood that the above-described embodiments of the present application are merely examples for clearly illustrating the present application, and are not intended to limit the manner in which the present application may be constructed. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary or exhaustive of all ways in which construction may be accomplished. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are desired to be protected by the following claims.

Claims

1. A FPGA-based 32-bit RISC-V processor, the processor comprising:

at least one soft core having a 32-bit RISC-V architecture; and

the soft core comprises a fetching module, a decoding module, an executing module, a memory access module and a write-back module which are sequentially connected and form a five-stage pipeline control mode; the soft core further comprises: the pipeline control module is used for carrying out pipeline control through the independent hot code; the instruction fetching module, the decoding module, the execution module, the access module and the write-back module are all provided with enabling ends; the assembly line control module is connected with the enabling end and is used for respectively controlling the on-off of the instruction fetching module, the decoding module, the execution module, the memory access module and the write-back module by taking the independent thermal code as an enabling signal;

accessing the target external equipment and realizing data transmission.

2. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the finger module further comprises:

3. The FPGA-based 32-bit RISC-V processor of claim 2, wherein the prefetch finger submodule is specifically configured to:

4. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the tag bits are provided in the bus address signals, the matching the bus address signals to external device addresses comprising:

5. The FPGA-based 32-bit RISC-V processor of claim 4 wherein the bus address signal is an 8-bit signal and the tag bit is the upper four bits.

6. The FPGA-based 32-bit RISC-V processor of claim 5, wherein the accessing the target external device and enabling data transfer comprises:

7. An FPGA-based 32-bit RISC-V processor as claimed in any one of claims 4-6 wherein said bus further comprises a multiplexer through which said soft core is connected to said external device.

8. An FPGA-based 32-bit RISC-V processor as claimed in any one of claims 4-6 wherein the external device comprises at least one of ROM, RAM, UART and GPIO.

9. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the soft core further comprises an arithmetic operation unit.

10. An FPGA-based electronic device comprising an FPGA-based 32-bit RISC-V processor as claimed in any one of claims 1-9.