CN116450570A - 32-bit RISC-V processor based on FPGA and electronic equipment - Google Patents

Abstract

The application discloses 32 bit RISC-V processor and electronic equipment based on FPGA, this processor includes: at least one soft core having a 32-bit RISC-V architecture; the bus is in communication connection with the soft core and is used for carrying out connection communication with external equipment; the soft core comprises an instruction fetching module, a decoding module, an executing module, a memory accessing module and a write-back module which are sequentially connected and form a five-stage pipeline control mode; the bus comprises a bus controller, and the bus controller enables the soft core to be connected and communicated with external equipment through the bus in a bus control mode based on one master and multiple slaves. The data processing efficiency of the RISC-V processor can be improved from the whole system angle, and the 32-bit five-stage pipeline soft core processor adopting the RISC-V open source instruction architecture is deployed behind the FPGA chip, and the SOC can be quickly built through bus and on-board resource interaction, so that the research and development efficiency is improved.

Description

FPGA-based 32-bit RISC-V processor and electronic equipment

technical field

This application relates to the field of computing architecture, in particular to FPGA-based 32-bit RISC-V processors and electronic equipment.

Background technique

In recent years, with the development of aerospace, automotive electronics and other fields, the use of microcontrollers has become more and more extensive. In addition to open source, the developers and maintainers of the RISC-V instruction architecture have refined the modular, incremental, and de-redundant RISC-V instruction set specification after summarizing the development of the simplified instruction set over the past few decades. , which is another major advantage of the RISC-V instruction architecture.

However, the existing RISC-V open source instruction architecture usually adopts single-cycle control. Since the entire process of an instruction from fetching to writing back is mostly combinational logic, the data flow will cause a certain delay. At the same time, because the bus control of the processor with this architecture is relatively complex, and the bus transmission delay is relatively large, the existing instruction processing method is further restricted by the bus speed and there are systematic constraints, resulting in the adoption of RISC-V open source instruction architecture. The overall data processing rate of the processor is difficult to increase.

Contents of the invention

The application provides an FPGA-based 32-bit RISC-V processor and electronic equipment, which can improve the data processing efficiency of the FPGA-based 32-bit RISC-V processor.

In a first aspect, the present application discloses an FPGA-based 32-bit RISC-V processor, the processor comprising: at least one soft core with a 32-bit RISC-V architecture; and

A bus, connected to the soft core for communication with external devices;

Wherein, the soft core includes an instruction fetch module, a decoding module, an execution module, a memory access module and a write-back module connected in sequence to form a five-stage pipeline control mode;

The bus includes a bus controller, and the bus controller enables the soft core to communicate with external devices through the bus through a bus control method based on one master and multiple slaves; the bus control method at least includes:

Predefining an external device address for the external device, where the external device address is used as a unique access identifier for the external device;

The obtained bus address signal is matched with the address of the external device;

Determine the corresponding target external device according to the successfully matched external device address;

Accessing the target external device and implementing data transfer.

In one embodiment, the fetching module further includes:

The prefetching submodule is used for preprocessing the instructions read into the soft core.

In one embodiment, the prefetching submodule is specifically used for:

Obtaining bit information at a preset position in the preprocessing instruction, and judging whether the preprocessing instruction is a branch jump instruction according to the bit information;

If yes, generate the jump instruction address corresponding to the preprocessing instruction, and prefetch the next preprocessing instruction.

In one embodiment, the soft core also includes:

Pipeline control module for pipeline control through one-hot encoding.

In one embodiment, the instruction fetching module, the decoding module, the execution module, the memory access module and the write-back module are all provided with enabling terminals;

The pipeline control module is connected to the enabling terminal, and is used for using the one-hot code as an enabling signal to respectively control the on-off of the instruction fetch module, the decoding module, the execution module, the memory access module and the write-back module.

In one embodiment, the bus address signal is provided with a flag bit, and the matching of the bus address signal with the external device address includes:

A flag bit in the bus address signal is matched with an external device address.

In one embodiment, the bus address signal is an 8-bit signal, and the flag bit is the upper four bits.

In an embodiment, the accessing the target external device and implementing data transmission includes:

When the target external device is RAM, the write enable signal of the soft core is transferred as the write enable signal of RAM;

The data returned by the RAM is assigned to the bus as an output to be passed to the soft core.

In an embodiment, the bus further includes a multiplexer, and the soft core is connected to the external device through the multiplexer.

In an embodiment, the external device at least includes at least one of ROM, RAM, UART and GPIO.

In an embodiment, the soft core further includes an arithmetic operation unit.

The present application also includes an FPGA-based electronic device, which includes the FPGA-based 32-bit RISC-V processor described in any one of the above.

It can be seen from the above that the FPGA-based 32-bit RISC-V processor and electronic equipment in this application can improve the RISC-V processing from the perspective of the whole system through the soft core of the five-stage pipeline control mode and the improved design of the bus control. In addition, the 32-bit five-stage pipeline soft-core processor adopting the RISC-V open source instruction architecture is deployed behind the FPGA chip, and through the interaction between the bus and onboard resources, the SOC can be quickly built and the research and development efficiency can be improved.

Description of drawings

FIG. 1 is a schematic diagram of an architecture of an FPGA-based 32-bit RISC-V processor provided in an embodiment of the present application.

FIG. 2 is a schematic diagram of another architecture of an FPGA-based 32-bit RISC-V processor provided by an embodiment of the present application.

FIG. 3 is a partial bus structure diagram provided by the embodiment of the present application.

FIG. 4 is a schematic timing diagram of a bus control method provided by an embodiment of the present application.

FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solution of the present application will be further described below in conjunction with the drawings and embodiments.

Please refer to FIG. 1 , which shows the architecture of an FPGA-based 32-bit RISC-V processor provided by an embodiment of the present application.

Wherein, the FPGA-based 32-bit RISC-V processor includes at least one soft core 1 and a bus 2 communicating with the soft core 1 .

The soft core 1 may have a 32-bit RISC-V architecture, specifically the soft core 1 designed using the RISC-V open source instruction architecture subset RV32I instruction set; the soft core 1 is based on the FPGA hardware, by using Bus 2 interacts with onboard resources to achieve the purpose of rapidly building an SOC.

The bus 2 is used to connect and communicate with external devices; where the external devices can include ROM (Read-Only Memory, read-only memory), RAM (random access memory, random access memory), UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous Transceiver) and at least one of GPIO (General-purpose input/output, general-purpose input/output port). Among them, common external devices include at least ROM and RAM, and other communication interfaces or communication modules, or other functional modules may also be mounted, which are not limited in this application.

Among them, the soft core 1 includes an instruction fetch module 11, a decoding module 12, an execution module 13, a memory access module 14, and a write-back module 15 that are sequentially connected to form a five-stage pipeline control mode. In the control mode, the instruction is transmitted to the instruction fetching part through the bus 2, and then translated by the decoding module 12, and after execution, it is determined whether memory access and write-back are required. The present application decomposes the processing cycle to obtain higher instruction or data processing speed and reduce the problem of excessive delay caused by different instruction or data resource occupation. Specifically, in the process of processing instructions, if the first instruction is fetched by the instruction fetching module 11, it can be transferred to the decoding module 12 to perform the actions in the decoding stage. Perform finger fetching action. Through the above-mentioned hierarchical manner, the processing efficiency of instructions can be improved under limited hardware resources.

Please refer to FIG. 2 , which shows another architecture of the FPGA-based 32-bit RISC-V processor provided by the embodiment of the present application.

As shown in Figure 2, the pipeline of soft core 1 is mainly composed of five modules: instruction fetch module, decoding module, execution module, memory access module and write back, and the register file is also involved in the formation of soft core 1 of the processor. , control status register, each inter-stage cache, conflict arbitration module, multiplexer, program counter, pipeline control module for controlling pipeline blocking, and interrupt module for interrupt control arbitration.

Among them, the inter-level cache includes instruction fetch and decoding inter-level cache, decoding execution inter-level cache, execution memory access inter-level cache, and memory access and write-back inter-level cache. Different inter-level caches are used to store data processed by the previous module. command information obtained later.

In one embodiment, the pipeline control module is used for pipeline control through one-hot encoding. The pipeline control method uses one-hot code to control the on-off of each pipeline stage respectively. The one-hot code can reduce the error probability of the signal jump process, and the pipeline control module can be set up to coordinate the work of each pipeline stage. Improve the processing efficiency of instructions.

Further, the instruction fetching module, the decoding module, the execution module, the memory access module and the write-back module are all provided with an enabling terminal, and the pipeline control module is connected to the enabling terminal for using the one-hot code as an enabling terminal. The signals respectively control the on-off of the instruction fetch module, the decoding module, the execution module, the memory access module and the write-back module. Compared with the traditional design of separately adding the enable signal of the on-off control of the pipeline level in each level of pipeline, the occupation of hardware resources can be reduced by setting the pipeline control module.

In another embodiment, the instruction fetching module may further include a prefetching submodule for preprocessing the instructions read into the soft core 1 . Wherein, the preprocessing here includes pre-reading the next instruction, and also includes pre-generating the address of the instruction that needs to jump. The pre-fetching sub-module can preprocess the branch and jump instructions of the instruction in advance, which can further improve the processing and execution efficiency of subsequent instructions, thereby improving the processing efficiency of the processor.

Specifically, the prefetching submodule is specifically used to: obtain bit information of a preset position in the preprocessing instruction, and judge whether the preprocessing instruction is a branch jump instruction according to the bit information; if so, generate a jump instruction The instruction address corresponding to the preprocessing instruction, and prefetch the next preprocessing instruction.

Among them, in the soft core 1 of the processor of the five-stage pipeline structure, the execution of an instruction needs at least five clock cycles. For the branch jump instruction, if you wait for the execution to finish and then fetch the next instruction, it will obviously waste a lot of time. By introducing the prefetch sub-module, regardless of whether a branch jump occurs, the next instruction will be read from the instruction register in advance and handed over to the next pipeline stage for use, thereby improving the throughput of the pipeline.

In an embodiment, the bus 2 includes a bus controller, and the bus controller enables the soft core 1 to communicate with external devices through the bus 2 through a bus 2 control method based on a master and multiple slaves. The bus 2 control method at least includes:

Predefine the external device address for the external device, which is used as the unique access identifier of the external device; obtain the bus 2 address signal, match the bus 2 address signal with the external device address; determine according to the successfully matched external device address The corresponding target external device; accessing the target external device and realizing data transmission.

Wherein, the external device may include at least one of ROM, RAM, UART and GPIO. For example, common external devices include at least ROM and RAM, and can also be mounted with other communication interfaces or communication modules, or other functional modules, which are not limited in this application.

The one-master-multiple-slave bus 2 control mode, that is, the soft core 1 of the processor acts as the master, and other external devices act as slaves. The soft core 1 of the processor has control over the bus 2, and completes access to specific external devices by assigning unique and fixed addresses to the external devices.

Specifically, the external device address is predefined for the external device. After the external device communicates with the processor, the processor executes the corresponding program to assign an external device address that can be used for communication to the external device, for example: 0x0000_0000 corresponds to the peripheral ROM in the device; 0x1000_0000 corresponds to the RAM in the peripheral; 0x2000_0000 corresponds to the UART in the peripheral; 0x3000_0000 corresponds to the GPIO in the peripheral. The above method is only used as an example, in fact, the address can be set as required, and the address can be bound with the external device.

In some embodiments, the bit width of the custom bus 2 is 16 bits, and the upper four bits are used to represent the address of the slave device controlled by the processor. In this embodiment, four external devices can be mounted. In actual use, the Specifically, allocate additional peripheral addresses to complete the control of other external devices. The specific external device control method is that the soft core 1 of the RISC-V processor passes through the system-defined bus 2, and various peripheral devices can and can only respond to various commands issued from the soft core 1 of the processor. Each peripheral device must pre-define a fixed address as the specific access identification of the designated peripheral device by the soft core 1 of the processor.

In this embodiment, with reference to FIGS. 3-4 , the figures show a part of the bus structure and the timing sequence of the bus control method provided by the embodiment of the present application.

Among them, as shown in Figure 3, the bus structure can be realized by using a multiplexer (MUX) control method, including an input multiplexer and an output multiplexer, wherein the input multiplexer and the soft-core input channel Connect and interface with read-only memory (ROM), random-access memory (RAM), universal asynchronous transceiver (UART), and general-purpose input/output ports (GPIO). The output multiplexer interfaces with the soft core output channels and interfaces with read-only memory (ROM), random-access memory (RAM), universal asynchronous transceiver (UART), and general-purpose input/output ports (GPIO). Of course, other bus structures may also be used, which is not limited in this application.

The address space allocated by the custom bus for external devices: 0x0000_0000 corresponds to the ROM in the peripheral device; 0x1000_0000 corresponds to the RAM in the peripheral device; 0x2000_0000 corresponds to the UART in the peripheral device; 0x3000_0000 corresponds to the GPIO in the peripheral device. According to the allocation of address space, it can be clearly seen that the bus can distinguish the specific external device accessed by the soft core of the processor according to the value of the upper four bits of the address.

As shown in Figure 4, the system signals include the system clock signal (sys_clk) and the system bus address signal (cpu_sysbus_addr), when the soft core of the 32-bit processor of the bus arbitration module enters the high four When the bit is 4'h0000, the accessed peripheral device is ROM. At this time, the data returned by ROM (rom_data) is assigned to the system bus data output signal (cpu_sysbus_data_o) as output; when the soft core of the 32-bit processor of the bus arbitration module arrives When the upper four bits of the system bus address signal (cpu_sysbus_addr) input are 4'h0001 (or written as 32'h0001), the peripheral device to be accessed is RAM, and the processor write enable signal (cpu_sysbus_wen) of the soft core is passed to The random access memory write enable signal (ram_wen) of the RAM, and at the same time assign the random access memory data signal (ram_data) returned by the RAM to the system bus data output signal (cpu_sysbus_data_o) as an output; when the 32-bit processor of the bus arbitration module When the upper four bits of the soft core to the system bus address signal (cpu_sysbus_addr) input are 4'h0002 and 4'h0003, they control the UART and GPIO respectively. The control method is exactly the same as the above two external devices, and will not be described again. Further, since the peripherals specifically accessed by the 16-bit custom bus address are determined by the highest four bits, the custom bus in this application can realize expansion of up to 16 slave devices.

It can be understood that the identification and matching method of the above instruction address is only one of the implementation methods, and those skilled in the art can customize the above parameters according to the actual situation, so as to ensure that the bus address signal matches the peripheral address of the external device. Can. The above-mentioned bus design and bus control method, through simple input and output and only simple combinational logic control, make the circuit synthesized by the self-defined bus in this application have the characteristics of small area, resource saving, and de-redundancy , can save enough resources on the FPGA chip to implement other functions in practical applications.

Moreover, the soft core of the processor needs to interact with the bus to fetch instructions from the instruction register. Since the processor of this application is built on the FPGA, the ROM on the FPGA board is used as the instruction register, and the RAM on the FPGA board is used as the processor. The cache of the soft core, in order to complete the interactive communication between the soft core of the processor and the outside, a UART controller is mounted on the bus to convert the parallel data of the CPU bus into serial data, and then send it to the UART receiving end of other devices . Since the SOC area in this application is relatively small, in some industrial control fields, the soft cores of multiple processors can be deployed on one FPGA chip, and the data exchange between multiple cores can be performed through the serial port on the bus.

It can be seen from the above that the FPGA-based 32-bit RISC-V processor of the present application can improve the data processing of the RISC-V processor from the perspective of the whole system through the soft core of the five-stage pipeline control mode and the improved design of the bus control. In addition, the 32-bit five-stage pipeline soft-core processor adopting the RISC-V open source instruction architecture is deployed behind the FPGA chip, and through the interaction between the bus and onboard resources, the SOC can be quickly built to improve the efficiency of research and development.

Please refer to FIG. 5 , which shows the structure of the electronic device provided by the embodiment of the present application. The electronic device 100 in this structure includes the FPGA-based 32-bit RISC-V processor 10 described above.

This FPGA-based 32-bit RISC-V processor 10 can be based on the program stored in the memory, that is, according to the program stored in the read-only memory (Read-Only Memory, ROM) or loaded from the storage part to random access memory (Random Access Memory, RAM) to perform various appropriate actions and processing, such as performing the method in the above-mentioned embodiment:

Predefine an external device address for the external device, and the external device address is used as a unique access identifier for the external device; obtain the bus address signal, and match the bus address signal with the external device address; The device address determines the corresponding target external device; accesses the target external device and realizes data transmission.

In RAM, various programs and data necessary for system operation are also stored. The FPGA-based 32-bit RISC-V processor 10, the memory, and the bus are connected to each other. Input/Output (I/O) interfaces are also connected to the bus.

In some embodiments, the following components can be connected to the I/O interface: an input section including a keyboard, a mouse, etc.; an output section including a liquid crystal display (Liquid Crystal Display, LCD) etc. and a speaker; a storage section including a hard disk, etc. ; and a communication part including a network interface card such as a LAN (Local Area Network, local area network) card, a modem, or the like. The communication section performs communication processing via a network such as the Internet.

It can be seen from the above that the FPGA-based electronic device of the present application can improve the data processing efficiency of the RISC-V processor from the perspective of the overall system, and adopt the 32-bit five-stage pipeline soft-core processor deployment of the RISC-V open source instruction architecture After the FPGA chip, through the interaction between the bus and onboard resources, the SOC can be quickly built to improve the efficiency of research and development.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

In the description of this application, it should be noted that unless otherwise specified and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected, or integrally connected; it can be mechanically connected, or electrically connected, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction of two components relation. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.

Apparently, the above-mentioned embodiments of the present application are only examples for clearly illustrating the present application, rather than limiting the way of completing the construction of the present application. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all construction completion methods here. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included within the protection scope of the claims of the present application.

Claims (12)

1. A FPGA-based 32-bit RISC-V processor, the processor comprising:

at least one soft core having a 32-bit RISC-V architecture; and

the bus is in communication connection with the soft core and is used for carrying out connection communication with external equipment;

the soft core comprises a fetching module, a decoding module, an executing module, a memory access module and a write-back module which are sequentially connected and form a five-stage pipeline control mode;

the bus comprises a bus controller, and the bus controller enables the soft core to be connected and communicated with external equipment through the bus in a bus control mode based on one master and multiple slaves; the bus control mode at least comprises the following steps:

predefining an external device address for an external device, wherein the external device address is used as a unique access identifier of the external device;

the method comprises the steps of obtaining a bus address signal, and matching the bus address signal with an external device address;

determining corresponding target external equipment according to the external equipment address successfully matched;

accessing the target external equipment and realizing data transmission.

2. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the finger module further comprises:

and the prefetching instruction submodule is used for preprocessing an instruction which is read and enters the soft core.

3. The FPGA-based 32-bit RISC-V processor of claim 2, wherein the prefetch finger submodule is specifically configured to:

acquiring bit information of a preset position in a preprocessing instruction, and judging whether the preprocessing instruction is a branch jump instruction or not according to the bit information;

if yes, generating a jumped instruction address corresponding to the preprocessing instruction, and pre-reading the next preprocessing instruction.

4. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the soft core further comprises:

and the pipeline control module is used for carrying out pipeline control through the independent hot code.

5. The FPGA-based 32-bit RISC-V processor of claim 4, wherein the fetch module, decode module, execute module, memory access module, and write-back module are all provided with enable ends;

the assembly line control module is connected with the enabling end and is used for controlling the on-off of the instruction fetching module, the decoding module, the executing module, the memory access module and the write-back module by taking the independent thermal code as an enabling signal.

6. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the tag bits are provided in the bus address signals, the matching the bus address signals to external device addresses comprising:

and matching the marking bit in the bus address signal with an external device address.

7. The FPGA-based 32-bit RISC-V processor of claim 6, wherein the bus address signal is an 8-bit signal and the tag bit is the upper four bits.

8. The FPGA-based 32-bit RISC-V processor of claim 7, wherein the accessing the target external device and enabling data transfer comprises:

when the target external device is a RAM, transmitting a write enable signal of the soft core as a write enable signal of the RAM;

and assigning the data returned by the RAM to a bus as output to be transferred to the soft core.

9. The FPGA-based 32-bit RISC-V processor of any of claims 6-8, wherein the bus further comprises a multiplexer through which the soft core is coupled to the external device.

10. An FPGA-based 32-bit RISC-V processor as claimed in any one of claims 6-8 wherein the external device comprises at least one of ROM, RAM, UART and GPIO.

11. The FPGA-based 32-bit RISC-V processor of claim 1, wherein the soft core further comprises an arithmetic operation unit.

12. An FPGA-based electronic device comprising an FPGA-based 32-bit RISC-V processor as claimed in any one of claims 1-11.