CN116382634B - Pseudo-random code generation circuit and method - Google Patents
Pseudo-random code generation circuit and method Download PDFInfo
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Abstract
The application provides a pseudo-random code generation circuit and a pseudo-random code generation method. The pseudo-random code generation circuit includes: the initial value module is used for storing the appointed initial state value and the feedback polynomial; the exclusive or gate array module is connected with the initial value module and is used for calculating the initial state value and generating a high-order state value; the data stream storage module is used for generating state data of the current period according to the initial state value and the high-order state value, and selecting the state value with a preset bit number from the state data as an output data stream; the data output module is capable of outputting the output data stream as a pseudo-random code. According to the method, the state data composed of the multi-bit state values are generated through the exclusive-OR gate array module, the state data with preset bits are output through the data stream storage module, the multi-bit pseudo-random code is output once, and the testing efficiency of the pseudo-random code in the test scene is improved.
Description
Technical Field
The application relates to the technical field of data communication, in particular to a pseudo-random code generation circuit and a pseudo-random code generation method.
Background
PRBS (Pseudo-Random Binary Sequence, pseudo-random code) is capable of generating random data streams, commonly used for simulation and testing of high-speed digital communication links. An LFSR (Linear Feedback Shift Register ) is used to generate a repeatable pseudo-random code sequence.
In the prior art, the pseudo-random code sequence generated by the LFSR is generated in a mode of continuously outputting the rightmost value through a shift register and then shifting the whole data stream to the right. The mode only outputs 1bit of data each time, has higher frequency requirement on clock signals in the application requiring high-speed test, and has too little data quantity output each time, thereby affecting the test efficiency.
Disclosure of Invention
An object of the present application is to provide a pseudo-random code generating circuit and method, so as to meet the frequency requirements of different clock signals and improve the test efficiency.
According to an aspect of an embodiment of the present application, there is provided a pseudo-random code generating circuit, including:
the initial value module is used for storing the appointed initial state value and the feedback polynomial;
the exclusive-or gate array module is connected with the initial value module at one end and is used for calculating the initial state value according to the feedback polynomial to generate a high-order state value;
the data stream storage module is connected with the initial value module and the exclusive-or gate array module, and is used for generating state data of a current period according to the initial state value and the high-order state value, and selecting a state value with a preset bit number from the state data as an output data stream of the current period;
and the input end of the data output module is connected with the output end of the data stream storage module and is used for outputting the output data stream as pseudo-random codes.
According to an aspect of an embodiment of the present application, there is provided a method for generating a pseudo random code, including:
acquiring an initial state value and a feedback polynomial;
calculating the initial state value based on the feedback polynomial to generate a high-order state value;
generating state data of a current period according to the initial state value and the high-order state value, and selecting a state value with a preset bit number from the state data;
and outputting the state value of the preset bit number as a pseudo-random code of the current period.
In the embodiment of the application, a pseudo-random code generating circuit is provided, which comprises an initial value module, an exclusive-or gate array module, a data stream storage module and a data output module, wherein the initial value module is used for storing an initial state value and a feedback polynomial, the structure of the exclusive-or gate array module is determined according to the feedback polynomial, the initial state value is calculated according to the exclusive-or gate array module, a high-order state value is generated, state data is generated according to the initial state value and the high-order state value through the data stream storage module, and a state value with a preset bit number is selected in the state data for the data output module to output as the pseudo-random code.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 shows a schematic circuit configuration of a pseudo random code generating circuit according to an embodiment of the present application.
Fig. 2 shows a schematic circuit configuration of a pseudo random code generating circuit according to another embodiment of the present application.
Fig. 3 shows a schematic circuit configuration of a pseudo random code generating circuit according to another embodiment of the present application.
Fig. 4 is a flow chart illustrating a pseudo random code generating method according to an embodiment of the present application.
Fig. 5 shows a schematic structural diagram of a pseudo random code generating apparatus according to an embodiment of the present application.
Fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more example embodiments. In the following description, numerous specific details are provided to give a thorough understanding of example embodiments of the present application. However, those skilled in the art will recognize that the aspects of the present application may be practiced with one or more of the specific details omitted, or with other methods, components, steps, etc. In other instances, well-known structures, methods, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.
Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.
Fig. 1 shows a schematic circuit configuration of a pseudo random code generating circuit according to an embodiment of the present application.
An initial value module 110 for storing the specified initial state value and the feedback polynomial.
And the exclusive-or gate array module 120, one end of which is connected with the initial value module 110 and is used for calculating the initial state value according to the feedback polynomial to generate a high-order state value.
The data stream storage module 130 is connected to the initial value module 110 and the exclusive-or gate array module, and is configured to generate state data of a current period according to the initial state value and the high state value, and select a state value with a preset number of bits from the state data as an output data stream of the current period.
And the input end of the data output module is connected with the output end of the data stream storage module and is used for outputting the output data stream as pseudo-random code.
Specifically, the initial value module 110 is configured to store a specified initial state value and a feedback polynomial.
The feedback polynomial is applied in a shift register with a feedback function. The shift register has several registers, each of which stores a binary number. The shift register outputs the end number each time and then moves the whole one bit to the right.
The shift register adopts a feedback function, takes the existing sequence in the register as the input of the feedback function, and fills the result output by the feedback function to the leftmost end of the shift register after a certain operation in the feedback function.
The feedback polynomial is a characteristic polynomial of the feedback function, and is used for limiting exclusive or on some bits in the shift register, and storing the exclusive or result to the leftmost end of the shift register.
The initial state value refers to a random code seed that is used as a shift register to cyclically generate an initial value of the data stream.
The exclusive or gate array module 120 is configured to generate a high-order state value according to the initial state value. The initial state values are used as low state values and form a set of sequences together with the high state values.
The structure of the exclusive-or gate array module 120 is related to the feedback polynomial, as the feedback polynomial is a characteristic polynomial that defines the feedback function, which acts to define the number of bits in the shift register that are subject to exclusive-or computation.
The xor gate array module 120 is composed of a plurality of xor gates, wherein the input of each xor gate is calculated by the value distributed by the feedback polynomial, and the number of the xor gates is different according to the difference of the feedback polynomial and the bit number of the initial state value.
The data stream storage module 130 is configured to store the status data, and select a status value with a preset number of bits from the status data as the output data stream of the current period.
The data output module 140 is configured to output the output data stream as a pseudo-random code.
As shown in fig. 1, the initial state value and the feedback polynomial are written into the initial value module 110, the initial value module 110 is connected with the data stream storage module 130, the initial state value is stored in the data stream storage module 130, meanwhile, the initial state value is input into the xor gate array module 120, and the xor gate array module 120 calculates based on the initial state value to obtain the high-order state value. The high state value is written to the data stream storage module 130. After the data stream storage module 130 generates the state data, it is necessary to select the multi-bit state value to output as a pseudo-random code.
It should be noted that, the number of bits of the initial state value and the high state value is the same, for example, the initial state value is 8 bits, and the high state value is 8 bits, and then the data stream storage module 130 selects to output a 4bit data stream every cycle.
In this embodiment, the pseudo random code generating circuit includes an initial value module, an exclusive or gate array module, a data stream storage module and a data output module, where the initial value module is used to store an initial state value and a feedback polynomial, the structure of the exclusive or gate array module is determined according to the feedback polynomial, the initial state value is calculated according to the exclusive or gate array module, a high-order state value is generated, state data is generated according to the initial state value and the high-order state value through the data stream storage module, and a state value with a preset number of bits is selected from the state data for the data output module to output as a pseudo random code.
Fig. 2 shows a schematic circuit configuration of a pseudo random code generating circuit according to another embodiment of the present application.
As shown in fig. 2, as an alternative embodiment, the pseudo-random code generating circuit further includes:
the input end of the data bit filling module 150 is connected with the output end of the data output module 140, and the output end of the data bit filling module 150 is connected with the data stream storage module 130, so as to generate bit filling data according to the state values of the state data except the output data stream.
The data stream storage module 130 is further configured to generate status data of a next period according to the bit complement data and status values of the status data other than the output data stream, and select a status value of a preset bit number from the status data of the next period as the output data stream of the next period.
Specifically, in order to circularly generate the pseudo-random code, in the shift register, the value of the end (rightmost end) is output every time, then the whole is shifted to the right, the leftmost value is calculated according to a preset calculation mode and is filled, and the pseudo-random code can be circularly generated by cycling the above process.
The data complement module 150 is operative to generate complement data for populating the leftmost state value.
The input end of the data bit compensation module 150 is connected to the output end of the data output module 140, and is configured to receive the values output by the data output module 140 except the output data stream, and generate bit compensation data according to the values.
Further, the output end of the data bit filling module 150 is connected to the input end of the data stream storage module 130, and is used for filling the bit filling data with the leftmost state value to form the state data of the next period, and selecting the state value with the preset bit number from the state data of the next period as the pseudo-random code of the next period.
It should be noted that the pseudo-random code is composed of a series of values, each value being composed of a data stream output per period. The pseudo-random code of the next cycle refers to the data streams output by the next cycle as part of the pseudo-random code.
In this embodiment, the data bit filling module 150 generates bit filling data for constructing a data stream to be circularly output, so as to realize the effect of circularly generating the pseudo-random code.
As an alternative embodiment, the data stream storage module 130 is further configured to receive a shift signal, and when the shift signal is enabled, the data stream storage module 130 selects a state value of a preset number of bits in the state data of the next cycle as the output data stream of the next cycle.
In particular, the data stream storage module 130 is further configured to receive the shift signal. The shift signal, when enabled, enables the data stream storage module 130 to select a state value of the state data.
In the initial stage, the shift signal is not valid, and initial state data needs to be generated according to the initial state value. After the current initial state data is output, bit-filling data is generated according to the data bit-filling module 150. When the shift signal is enabled, the data stream storage module 130 selects an output data stream from the state data and outputs a corresponding pseudo random code through the data output module 140.
Further, the data bit compensation module 150 includes at least one xor gate, and the number of the xor gates is related to the number of the state values of the preset number of bits output by the data output module 140.
Specifically, the data bit compensation module 150 includes at least one xor gate, and the xor gates are connected in parallel. And the input of each exclusive OR gate is a state value of a certain bit of the state data, and exclusive OR calculation is carried out according to the state value to obtain the bit complement data. The input of the data bit compensation module 150 is state data output by the data output module 140 except for pseudo random codes.
The number of the data bit-filling modules 150 is related to the number of the state values of the preset number of bits output by the data output module 140, for example, the number of data streams to be output by the data output module 140 in each period is 4 bits, and then the number of exclusive-or gates of the data bit-filling modules 150 is also 4.
In this embodiment, the data bit compensation module 150 is composed of at least one xor gate, the number of the xor gates is the same as the number of the output pseudo-random codes, on the premise of outputting the multi-bit data stream at one time, multi-bit data at the leftmost end of the shift register can be filled at one time, cyclic output of the pseudo-random codes is realized, and the multi-bit data stream can be output at the same time in each period.
Further, the xor gate array module 120 includes at least one xor gate; each exclusive or gate is used for performing exclusive or calculation according to the state value distributed by the feedback polynomial, and the state value distributed by the feedback polynomial corresponds to the state value of the preset bit number in the initial state value.
Specifically, the xor gate array module 120 includes at least one xor gate, and each xor gate is configured to perform calculation according to the state value of the corresponding bit number in the initial state value.
The number of exclusive-or gates is related to the number of bits of the initial state value.
Further, the data output module 140 includes:
and the input end of the D trigger is connected with the output end of the data stream storage module 130, and the D trigger is used for outputting the state value of the preset bit number of the state data as a pseudo-random code.
The S interface in the D trigger is connected with a clock signal, and the R interface is connected with a reset signal. The input of the D flip-flop is connected to the output of the data stream storage module 130, and is used to output the data stream selected by the data stream storage module 130 as a pseudo-random code output when the clock signal is enabled.
Figure 3 shows a schematic circuit diagram of a pseudo-random code generating circuit according to another embodiment of the present application, specifically, the initial state value is 00000100 the feedback polynomial is a circuit structure diagram of a pseudo random code generation circuit of x-3+x-2+1.
As shown in FIG. 3, the number of bits of the output pseudo-random code is 4 bits, i.e., [3:0].
The xor gate array module 120 consists of 10 xor gates, each input of which is 8 bits of the initial state value. For example, the inputs of the first exclusive OR gate are bits 1 and 2, which are represented as state values corresponding to [0:1], e.g., 0.
The first six exclusive-OR gates are generated [13:8], namely, the 14 th bit to the 9 th bit, and the 16 th bit and the 15 th bit are respectively generated by two exclusive-OR gates connected in parallel.
Fig. 4 is a flow chart of a pseudo random code generating method according to an embodiment of the present application, the method includes the following steps:
s400, acquiring an initial state value and a feedback polynomial.
S410, calculating the initial state value based on the feedback polynomial to generate a high-order state value.
Specifically, the feedback polynomial is used for performing exclusive-or calculation on the initial state value to generate a high-order state value.
S420, generating state data of the current period according to the initial state value and the high-order state value, and selecting a state value with a preset bit number from the state data.
Specifically, state data of the current period is generated according to the initial state value and the high-order state value, and a state value with a preset bit number is selected from the state data.
For example, the state data has 16 bits in total, each bit is composed of a binary number, and the preset bit number refers to a certain bit of the 16 bits, for example, a bit located at the far right end.
S430, outputting the state value of the preset bit number as the pseudo-random code of the current period.
In the present embodiment, the generation method of the pseudo random code corresponds to the generation circuit of the pseudo random code. Wherein the number of last output pseudo-random codes is related to the feedback polynomial and the initial state value.
In this embodiment, an initial state value and a feedback polynomial are obtained, the initial state value is calculated by the feedback polynomial to obtain a high-order state value, state data of a current period is generated based on the initial state value and the high-order state value, a state value with a preset bit number is selected from the state data of the current period to serve as a pseudo-random code of the current period, the state value with the preset bit number is selected from the state data, so that a multi-bit data stream can be output at one time, the speed requirement on a clock signal is not high, the efficiency of the output pseudo-random code can be improved, and the efficiency of a test is improved in a high-speed data communication test scene.
As an alternative embodiment, in step S410, the initial state value is calculated based on the feedback polynomial, and the high-order state value is generated, including:
s411, based on the feedback polynomial, determining the number of bits in the initial state value for exclusive OR calculation.
S412, performing exclusive OR calculation on the initial state value according to the number of bits subjected to exclusive OR calculation to obtain a high-order state value.
In particular, the feedback polynomial is able to determine the number of bits by which the state data stored in the shift register is xored, essentially in the manner used to determine the way the exclusive-or operation is performed.
On the basis, the exclusive OR calculation is carried out on the initial state value, and the high-order state value is obtained.
In this embodiment, the high-order state value and the initial state value together form the state data, and the bit number of the state data is widened based on the initial state value, which is favorable for carrying in advance, thereby realizing the effect of outputting the multi-bit data stream once.
As an alternative embodiment, after outputting the state value of the preset number of bits as the pseudo random code of the current period in step S430, the method further includes:
s440, generating bit compensation data based on the state values of the current period state data except the pseudo random code.
S450, generating the state data of the next period according to the bit filling data and the state values of the state data of the current period except the pseudo-random code.
Specifically, in the state data of the current period, a state value of a certain bit is outputted as a pseudo-random code, and the remaining state values other than the pseudo-random code are used to generate bit-complement data.
The state data of the next cycle is generated based on the bit-fill data and the state values of the state data of the current cycle other than the pseudorandom code.
For example, if the state data is 16 bits in total, and the state value of [3:0] bits is outputted as a pseudo-random code, which corresponds to the value of [3:1] bits being advanced, a 4-bit data stream can be outputted at a time.
After carry ahead, the whole of the [15:4] bits of the state data is moved rightwards and becomes [11:0], at this time, the [15:12] bits are empty, and then the bit compensation data is required to be generated according to the state value of the original [15:4] bits, and the value of the bit compensation data is filled on the [15:12] bits at this time.
Therefore, the data stream with preset bit number is continuously output, the original state data moves rightwards as a whole, and the generated complementary bit data is filled in the leftmost position, so that the pseudo-random code can be periodically and circularly generated.
In this embodiment, the complementary bit data is generated by the original state data, and on the basis that the multi-bit data stream can be output at one time, the cyclic output of the pseudo-random code is realized, which is beneficial to improving the efficiency of generating the pseudo-random code.
Further, the number of state values of the bit filling data is the same as the number of bits of the pseudo random code.
Fig. 5 shows a schematic structural diagram of a pseudo random code generating apparatus according to an embodiment of the present application.
The pseudo-random code generation device comprises:
the initial value obtaining module 51 is configured to obtain an initial state value and a feedback polynomial.
The high-order state value generating module 52 is configured to calculate the initial state value based on the feedback polynomial, and generate a high-order state value.
The state data generating module 53 is configured to generate state data of a current period according to the initial state value and the high-order state value, and select a state value with a preset number of bits from the state data.
The pseudo-random code module 54 is configured to output a state value of a preset number of bits as a pseudo-random code of a current period.
Further, the pseudo-random code generating device further includes:
and the bit compensation data generation module is used for generating bit compensation data based on the state values of the current period state data except the pseudo-random code.
And the state data cycle generation module is used for generating the state data of the next period according to the bit filling data and the state values of the state data of the current period except the pseudo-random code.
Fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 60 shown in fig. 6 is only an example and should not be construed as limiting the functionality and scope of use of the embodiments herein.
As shown in fig. 6, the electronic device 60 is in the form of a general purpose computing device. Components of electronic device 60 may include, but are not limited to: the at least one processing unit 610, the at least one memory unit 620, and a bus 630 that connects the various system components, including the memory unit 620 and the processing unit 610.
Wherein the storage unit stores program code that is executable by the processing unit 610 such that the processing unit 610 performs steps according to various exemplary embodiments of the present application described in the description section of the exemplary method described above in the present specification. For example, the processing unit 610 may perform various steps as shown in fig. 4.
The storage unit 620 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 6201 and/or cache memory unit 6202, and may further include Read Only Memory (ROM) 6203.
The storage unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
Bus 630 may be a local bus representing one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or using any of a variety of bus architectures.
The electronic device 60 may also communicate with one or more external devices 700 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 60, and/or any device (e.g., router, modem, etc.) that enables the electronic device 60 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 650. An input/output (I/O) interface 650 is connected to the display unit 640. Also, electronic device 60 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 360. As shown, network adapter 660 communicates with other modules of electronic device 60 over bus 630. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 60, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a mobile terminal, etc.) to execute the method for generating a pseudo-random code according to the embodiments of the present application.
In an exemplary embodiment of the present application, there is also provided a computer-readable storage medium having stored thereon computer-readable instructions, which when executed by a processor of a computer, cause the computer to perform the method of generating a pseudo-random code described in the method embodiment section above.
According to an embodiment of the present application, there is also provided a program product for implementing the method in the above method embodiments, which may employ a portable compact disc read only memory (CD-ROM) and comprise program code and may be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable signal medium may include a data signal propagated in baseband or as part of a carrier wave with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, in accordance with embodiments of the present application. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
Furthermore, although the various steps of the methods herein are depicted in the accompanying drawings in a particular order, this is not required to either suggest that the steps must be performed in that particular order, or that all of the illustrated steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a mobile terminal, etc.) to perform the method according to the embodiments of the present application.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (8)
1. A pseudo-random code generating circuit, the circuit comprising:
the initial value module is used for storing the appointed initial state value and the feedback polynomial;
the exclusive-or gate array module is connected with the initial value module at one end and is used for calculating the initial state value according to the feedback polynomial to generate a high-order state value;
the data stream storage module is connected with the initial value module and the exclusive-or gate array module, and is used for generating state data of a current period according to the initial state value and the high-order state value, and selecting a state value with a preset bit number from the state data as an output data stream of the current period;
the input end of the data output module is connected with the output end of the data stream storage module and is used for outputting the output data stream as pseudo-random codes;
the input end of the data bit filling module is connected with the output end of the data output module, and the output end of the data bit filling module is connected with the data stream storage module and is used for generating bit filling data according to the state values of the state data except the output data stream;
the data stream storage module is further configured to generate status data of a next period according to the bit-filling data and status values of the status data except the output data stream, and select a status value of a preset bit number from the status data of the next period as the output data stream of the next period.
2. The pseudorandom code generation circuit of claim 1 wherein the data stream storage module is further configured to receive a shift signal, the data stream storage module selecting a state value of a preset number of bits in a next cycle of state data as the output data stream for the next cycle when the shift signal is enabled.
3. The pseudorandom code generation circuit of claim 1 wherein the data bit-compensation module comprises at least one exclusive or gate, the number of exclusive or gates being related to the number of state values of the predetermined number of bits output by the data output module.
4. The pseudo-random code generating circuit according to claim 1, wherein the exclusive or gate array module comprises at least one exclusive or gate;
and each exclusive or gate is used for performing exclusive or calculation according to the state value distributed by the feedback polynomial, wherein the state value distributed by the feedback polynomial corresponds to the state value of the preset bit number in the initial state value.
5. The pseudo-random code generating circuit according to claim 1, wherein the data output module comprises:
and the input end of the D trigger is connected with the output end of the data stream storage module, and the D trigger is used for outputting the state value of the preset bit number of the state data as a pseudo-random code.
6. A method of pseudo-random code generation, the method comprising:
acquiring an initial state value and a feedback polynomial;
calculating the initial state value based on the feedback polynomial to generate a high-order state value;
generating state data of a current period according to the initial state value and the high-order state value, and selecting a state value with a preset bit number from the state data;
outputting the state value of the preset bit number as a pseudo-random code of the current period;
generating bit-complement data based on state values of the state data except the pseudo-random code in a current period;
and generating state data of the next period according to the bit filling data and the state values of the state data except the pseudo random code of the current period.
7. The method of generating pseudo-random code according to claim 6, wherein calculating the initial state value based on the feedback polynomial generates a high-order state value, comprising:
determining the number of bits for exclusive OR calculation in the initial state value based on the feedback polynomial;
and performing exclusive-or calculation on the initial state value according to the number of bits subjected to exclusive-or calculation to obtain the high-order state value.
8. The method of generating a pseudorandom code of claim 6 wherein the number of state values of the bit-complement data is the same as the number of bits of the pseudorandom code.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4493046A (en) * | 1981-05-26 | 1985-01-08 | Nippon Electric Co., Ltd | Apparatus for generation of binary pseudo-random numbers |
| CN1914590A (en) * | 2004-01-30 | 2007-02-14 | 日本胜利株式会社 | Pseudo random number generation device and pseudo random number generation program |
| CN101019099A (en) * | 2004-09-22 | 2007-08-15 | 诺基亚公司 | Method and device for generating pseudo random numbers |
| CN101138195A (en) * | 2005-02-14 | 2008-03-05 | 法国电信公司 | Method system and device for generation of a pseudo-random data sequence |
| CN102025389A (en) * | 2009-09-09 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for generating pseudorandom sequence |
| CN102707923A (en) * | 2011-04-25 | 2012-10-03 | 中国电子科技集团公司第三十八研究所 | Pseudo-random number generation circuit and pseudo-random number generation method |
| CN213458021U (en) * | 2020-12-15 | 2021-06-15 | 张桂红 | Pseudo-random sequence generation circuit |
| JP2021144463A (en) * | 2020-03-12 | 2021-09-24 | 富士通株式会社 | Pseudo-random number generation circuit device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0013349D0 (en) * | 2000-06-01 | 2000-07-26 | Tao Group Ltd | Pseudo-random number generator |
| DE10357782B3 (en) * | 2003-12-10 | 2005-05-04 | Infineon Technologies Ag | Random number generator for cryptographic applications e.g. for chip card, has intermediate condition of pseudo-random number generator stored in memory as initializing information |
-
2023
- 2023-05-29 CN CN202310613519.6A patent/CN116382634B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4493046A (en) * | 1981-05-26 | 1985-01-08 | Nippon Electric Co., Ltd | Apparatus for generation of binary pseudo-random numbers |
| CN1914590A (en) * | 2004-01-30 | 2007-02-14 | 日本胜利株式会社 | Pseudo random number generation device and pseudo random number generation program |
| CN101019099A (en) * | 2004-09-22 | 2007-08-15 | 诺基亚公司 | Method and device for generating pseudo random numbers |
| CN101138195A (en) * | 2005-02-14 | 2008-03-05 | 法国电信公司 | Method system and device for generation of a pseudo-random data sequence |
| CN102025389A (en) * | 2009-09-09 | 2011-04-20 | 中兴通讯股份有限公司 | Method and device for generating pseudorandom sequence |
| CN102707923A (en) * | 2011-04-25 | 2012-10-03 | 中国电子科技集团公司第三十八研究所 | Pseudo-random number generation circuit and pseudo-random number generation method |
| JP2021144463A (en) * | 2020-03-12 | 2021-09-24 | 富士通株式会社 | Pseudo-random number generation circuit device |
| CN213458021U (en) * | 2020-12-15 | 2021-06-15 | 张桂红 | Pseudo-random sequence generation circuit |
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