CN116382560A

CN116382560A - Management method and control system for memory

Info

Publication number: CN116382560A
Application number: CN202111595719.0A
Authority: CN
Inventors: 沈佳奇; 陈正亮; 王琛銮; 蔡全; 蔡勤世
Original assignee: Lianyun Technology Hangzhou Co ltd
Current assignee: Lianyun Technology Hangzhou Co ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2023-07-04

Abstract

The invention discloses a management method and a control system for a memory. The management method comprises the following steps: for a plurality of time periods within a first time window, counting an average amount of data to be processed by the control system in each time period; and comparing the plurality of average data amounts corresponding to the plurality of time periods with a first set threshold value respectively, and if each average data amount is smaller than the first set threshold value, recycling garbage from the storage medium. The management method and the control system of the memory of the embodiment judge the low load state of the host more accurately, so that garbage collection can be performed at the right time, and the problem that the performance of the host is affected by selecting improper time to perform garbage collection is avoided to the greatest extent.

Description

Management method and control system for memory

Technical Field

The present application relates to the field of memory, and more particularly to a management method and control system for memory.

Background

Solid state disks (SSD, solid State Drive) are nonvolatile data storage devices composed of a controller and an array of memory chips. The interface of the solid state disk can be compatible with a traditional hard disk which uses a magnetic disk as a storage medium, and has the advantages of small volume, light weight, low power consumption, no noise, high read-write speed and the like compared with the traditional hard disk, so the interface of the solid state disk is widely used for replacing the traditional hard disk at present, and is applied to various fields such as notebook computers, industrial control, video monitoring, network terminals, navigation equipment and the like.

Because the solid state disk uses the flash memory chip as the storage medium, the garbage collection needs to be periodically and irregularly carried out, namely, the effective data of the storage blocks (blocks) on the flash memory chip are read out and rewritten into other storage blocks, and then the data on the corresponding storage blocks are erased, so that a new available storage block can be obtained.

In the related art, in order to avoid influencing the read-write performance of the host to the solid state disk, the solid state disk generally selects to perform garbage collection under the low load state of the host, specifically, the solid state disk compares the read-write performance of the host to the solid state disk with a set threshold, and when the read-write performance is already lower than the set threshold, the host is considered to enter the low load state, and the solid state disk starts garbage collection. However, this determination method is not accurate in at least the following four scenarios:

1) In a full-disk state, the solid state disk has less free space, and the solid state disk increases garbage collection, so that the writing performance of a host to the solid state disk is extremely small;

2) Certain severe environments (such as a high-temperature environment or a poor low-temperature environment), the host computer has very small read and write performance for the solid state disk;

3) In some situations (such as that firmware needs to be worn and balanced), the solid state disk increases garbage collection, so that the writing performance of the host computer on the solid state disk becomes extremely small.

4) The quality of the individual storage block is poor, and when the host reads the block, a plurality of abnormal processing flows are generated, so that the read performance of the host on the solid state disk is particularly small.

All four of these cases may lead to misjudging the low load condition of the host. If the host is not in a low load state, but the solid state disk is judged to be in a low load state and garbage collection is executed, the read-write performance of the host on the solid state disk is caused to be poorer. Such degradation may not greatly affect the user experience when the solid state disk does not reach full disk (full disk means that the usage rate of the storage medium in the solid state disk reaches 95% or more), but when the hard disk reaches full disk, such degradation may cause the user experience to become a channel cake.

Based on this, a more accurate determination is needed to determine the host low load condition.

Disclosure of Invention

In view of the above, the present disclosure provides a memory management method and a memory to solve the above-mentioned problems.

According to a first aspect of the present disclosure, there is provided a management method for a memory including a control system and a storage medium, the management method being performed by the control system, including:

for a plurality of time periods within a first time window, counting an average amount of data to be processed by the control system in each time period;

and comparing the average data amounts corresponding to the time periods with a first set threshold value respectively, and if each average data amount is smaller than the first set threshold value, recycling garbage from the storage medium.

In some embodiments, further comprising: if at least one of the plurality of average data amounts is greater than or equal to the first set threshold, repeating the management method within a second time window subsequent to the first time window.

In some embodiments, the first time window is divided equally into the plurality of time periods.

In some embodiments, further comprising: and switching the new physical block obtained by executing garbage collection into an SLC CACHE mode.

In some embodiments, the management method further comprises: the physical block being written to is turned off to facilitate the control system switching to the SLC CACHE mode for write operations on other physical blocks.

In some embodiments, the management method is only performed when the following conditions are met: the usage of the storage medium is greater than or equal to a second set threshold.

In some embodiments, the memory is a solid state disk, and the storage medium is a flash memory chip.

According to a second aspect of the present disclosure, there is provided a control system of a memory including a control system and a storage medium, comprising:

an interface unit for receiving a command from a host;

a processor;

firmware, including computer instructions executed by a processor;

a processor for executing the computer instructions to perform the following operations:

and comparing the plurality of average data amounts corresponding to the plurality of time periods with a first set threshold value respectively, and if each average data amount is smaller than the first set threshold value, recycling garbage from the storage medium.

In some embodiments, the firmware stored computer instructions further comprise: after the garbage collection, the corresponding physical block is instructed to be switched to an SLC CACHE mode.

According to a third aspect of the present disclosure, there is provided a solid state disk including the memory controller described above and a flash memory chip serving as a storage medium.

The management method and the control system of the memory of the embodiment judge the low load state of the host more accurately, so that garbage collection can be performed at the right time, and the problem that the performance of the host is affected by selecting improper time to perform garbage collection is avoided to the greatest extent.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing embodiments thereof with reference to the following drawings in which:

FIG. 1 shows a schematic block diagram of a prior art computer system;

FIG. 2 illustrates a functional block diagram of the firmware of FIG. 1 in accordance with an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a first time window and a second time window;

FIG. 4a is an exemplary diagram of a non-average split time window;

FIG. 4b is an example graph of time steps of two time window divisions differing in the case of average division;

FIG. 5 is a flow chart of a method of management for memory;

Detailed Description

The present disclosure is described below based on embodiments, but the present disclosure is not limited to only these embodiments. In the following detailed description of the present disclosure, certain specific details are set forth in detail. The present disclosure may be fully understood by one skilled in the art without a description of these details. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the disclosure. The figures are not necessarily drawn to scale.

The flowcharts, block diagrams in the figures illustrate the possible architecture, functionality, and operation of the systems, methods, devices according to the embodiments of the present disclosure, and the blocks in the flowcharts and block diagrams may represent a module, a program segment, or a code segment, which is executable instructions for implementing the specified logical function(s). It should also be noted that the executable instructions that implement the specified logic functions may be recombined to produce new modules and program segments. The blocks of the drawings and the order of the blocks are thus merely to better illustrate the processes and steps of the embodiments and should not be taken as limiting the invention itself.

Before describing various embodiments of the present disclosure, some basic features related to flash memory chips are described.

There are four types of memory cells of flash memory chips currently in hot use: SLC, MLC, TLC and QLC.

The memory cell of SLC stores 1bit of information, i.e. only two voltage variations, 0, 1.

Each memory cell of an MLC stores 2 bits of information, requiring more complex voltage control, with four variations of 00,01,10, 11.

Each memory cell of TLC stores 3 bits of information, with voltages ranging from 000 to 001 with 8.

There are 16 variations in the voltage of each memory cell of the QLC.

In comparison, the comparison between the read-write performance of these four types of memory cells is: SLC > MLC > TLC > QLC, and the comparison between memory capacity and product cost is: SLC < MLC < TLC < QLC. It is also well understood that the less the voltage variation stored in the memory cell, the simpler it is to control, and correspondingly the higher the read-write performance, while at the same time the less data can be stored, the poorer the memory capacity and the higher the product cost.

Fig. 1 shows a schematic block diagram of a computer system according to the prior art. Computer system 100 includes a host 110, a control system 120, and a storage medium 130. Hereinafter, a solid state disk is described as an example. The solid state disk includes, for example, a control system 120 and a storage medium 130 as shown in the figure, and the storage medium of the storage medium 130 is, for example, a flash memory chip array.

The host interface 121 of the control system 120 is connected to the host 110 to transmit instructions. Host interface 121 is, for example, SATA, M.2, mSATA, and PCI-E. The processor 123 is electrically connected to the host interface 121, the cache controller 124, and the flash memory controller 125. The cache controller 124 is electrically connected to the cache unit, and SRAM125 and/or DRAM 126 are provided as cache units of the control system 120. The flash controller 125 is electrically connected to the storage medium 130.

To enable the control system 120 to handle read and write accesses from the host 110, the control system 120 also includes an FTL (Flash Translation Layer ) formed as firmware 127, as shown. Referring to fig. 2, the FTL includes a scheduling module 1272, a host write module 1274, and a host read module 1275 that are executed by the processor 123. One core idea of FTL is address mapping, which corresponds to an L2P mapping table, which indicates how a logical address sent by host 110 and a physical address on storage medium 130 establish a mapping relationship. The L2P map is stored in SRAM125 and/or DRAM 126 on the figure. Using the L2P mapping table, the host write module 1274 and the host read module 1275 complete the read/write operations as follows: the host write module 1274 reads the L2P mapping table from the buffer unit, maps the logical address received from the host 110 to a specific physical address of the storage medium 130 based on the L2P mapping table, and writes data to the specific physical address of the storage medium 130; host read module 1275 also reads the L2P mapping table from the cache unit, maps the logical address received from host 110 to a specific physical address of storage medium 130 based on the L2P mapping table, and reads the required data from the specific physical address of storage medium 130. The scheduling module 1272 is responsible for general control tasks such as scheduling host write modules 1274, host read modules 1275, etc.

Storage medium 130 includes an array of flash memory chips. To improve the data read/write performance, the flash controller 125 may read/write the flash memory chip of the storage medium 130 via a plurality of channels CH0 and CH 1. Each channel is connected to a set of flash memory chips. Each flash memory chip includes a plurality of physical blocks, each physical block including a plurality of physical pages. Data access operations to flash memory chips include read, write, and erase. Due to the physical characteristics of the flash memory chip, a basic unit of data read and write operations is, for example, a physical page, and a basic unit of erase operations is, for example, a physical block.

Referring to fig. 2, firmware 127 further includes a load monitoring module 1271 and a garbage collection module 1273 provided by embodiments of the present disclosure that are executed by processor 123.

The load monitoring module 1271 is responsible for monitoring the load state of the host in real time, judging whether the load state is a low load state, and executing the garbage collection module to collect garbage when the load state is determined to be the low load state. The garbage collection module 1273 is responsible for directing garbage collection to release usable blocks.

Compared with the related art, the host low-load judging method provided by the embodiment of the disclosure comprises the following steps: for a preset time window, the time window is divided into a plurality of time periods, in each time period, the data amount to be processed is obtained from the command received by the host 110, the total data amount to be processed in the time period is counted accordingly, the average data amount of each time period is obtained and counted by dividing the total data amount by the duration of each time period, and the average data amount of each time period is compared with a first set threshold value, and only if the average data amount of all time periods is smaller than the first set threshold value, the host is considered to be in a low-load state. The first set threshold is an empirical value, which can be determined according to the average data size delivered by the host when the host is idle, and the value of all hard disks does not change much.

For example, the time window is 6s, statistics is performed every 250ms, and when the data quantity counted for 24 times is detected to be smaller than the first set threshold value, the host is in a low-load state. At this time, the hard disk is used for garbage collection, so that a large amount of garbage collection is performed when the host is in low load, and enough space is released.

However, when the preset time window is monitored, if the average data amount in a certain time period obtained through statistics is found to be greater than or equal to a preset threshold value, the host low-load state is judged not to be. At this time, the hard disk does not carry out garbage collection.

The control system of the memory provided by the embodiment is more accurate in judging the low-load state of the host, so that the control system can recycle the garbage at the right time, and the problem that the performance of the host is affected by selecting improper time to recycle the garbage is avoided to the greatest extent.

In some embodiments, since garbage collection module 1273 performs garbage collection operations on storage medium 130 in units of physical blocks, the operations performed include: the physical block to be garbage recovered is determined, then the data on the physical block is transferred to the physical block of the storage medium 130, and then the data is erased, so that after the erasing operation is performed, if the storage type of the physical block is determined to be one of MLC, TLC, QLC, the physical block can be switched to an SLC CACHE mode, and after the switching, the memory cell with the physical type of MLC, TLC, QLC can simulate SLC to be written and read, thereby improving the reading performance.

In some embodiments, the physical block being written is closed. Since both the writing and reading operations of physical blocks are performed in PAGEs, when one physical block may not complete the reading or writing operation of all PAGEs at a time, but for example, the control system writes PAGE1 of physical block1 (and the remaining PAGEs are not written) first, then performs garbage collection of physical block2, and sets block2 after performing garbage collection to SLC CACHE mode, so that the control system may further instruct to close physical block1 being written, then the subsequent writing operation of the control system may select block2 of SLC CACHE mode, thereby achieving performance improvement.

In a further embodiment, the firmware shown in fig. 2 further includes a hard disk monitoring unit, which is configured to monitor the usage of the storage medium in real time, and enable the load monitoring module 1271 and the garbage collection module 1273 shown in fig. 2 only when the usage of the storage medium is greater than or equal to the second set threshold. The second set threshold may be a threshold used when a full disk is judged, for example, 95%, i.e., when a memory is judged to be full, starting to perform garbage collection based on load monitoring.

The above embodiments are applicable to system disks, storage disks, and external hard disks, and are particularly applicable to system disks. Because the system disk basically does not have the condition of being idle for a period of time, the system (Windows/Linux) can send a small amount of read-write commands to the hard disk, and the system disk in the related art cannot enter a low-power consumption mode, so that a large amount of garbage collection is basically not needed, the available physical blocks of the system disk in a full disk state are reduced or even not needed, and the performance is greatly reduced. Through the embodiment, the garbage collection can release enough space, and the read-write performance can be further improved by switching the physical blocks after garbage collection into the SLC CACHE mode, so that the performance can be obviously improved when the operation is restarted after stopping the read-write operation for a period of time, and the user experience is greatly improved.

In summary, the method provided by the present disclosure can enable the solid state disk (especially the system disk) to be used for a long time and to be full of disk state, and still maintain performance without dropping speed while meeting low power consumption. It should be noted, however, that for a system disk, garbage collection based on load monitoring as described in the above embodiments cannot be performed during the period of time that the system disk has just been powered on, BIOS booted, or I/O Queue is established, but the remaining scenarios are applicable. Therefore, in theory, before judging whether the host is low-load, it is first judged whether the host is one of the three conditions, if not, the garbage collection based on the load monitoring described in the above embodiment is started to be performed, so as not to affect the normal operation of the system disk.

FIG. 3 is a schematic diagram of an exemplary first time window and second time window. As shown in fig. 3, the first time window is composed of time instants S0 to S4, and the second time window is composed of time instants S3 to S7. The statistical strategies based on the graph shown in fig. 3 are: once the average data amount for a certain period of time is found to be about to or has exceeded the first set threshold, the current statistics process is stopped immediately and the next round of statistics process is started, so in this example, between S2 to S3, the average data amount is found to exceed the first set threshold, the statistics process for the first time window is terminated and the statistics process for the second time window is started from the moment S3. Of course, this need not be the case, and the second time window may also start at time S4, for example, even at time S5 or S6 after time S4. It should be noted, however, that while in this example both time windows on the graph are equally divided in the same time step, embodiments of the present disclosure do not force that each time window must be equally divided.

Fig. 4a is an example diagram of a non-average split time window. Fig. 4b is an exemplary diagram of time steps of two time window divisions differing in the case of average division. In fig. 4a, the time points S11 to S15 are one time window, the time points S11 to S13 are divided into two time periods on average, and the time points S13 to S15 are divided into two time periods on average. In this example, the uneven division may be random or may be defined in advance. In fig. 4b, the fourth time window and the fifth time window are divided equally, but they are both divided in different time steps, the fifth time window being divided in the figure in twice the time step as the fourth time window for clarity. The idea to be expressed for this example is: the time step taken by the next time window may be determined based on the magnitude relationship of the average data amount for the multiple time periods within the previous time window to the set threshold. For example, assuming that the average data amount for all time periods within the last time window is much greater than the set threshold, the next time window may be separated from the last time window by a period of time, and the next time window may be divided into a smaller number of multiple time periods. It should be appreciated that since the embodiments of the present disclosure count the average amount of data per time period, the same value of the first set threshold may be used in different embodiments.

Fig. 5 is a flow chart of a method for managing memory. The management method is performed by a control system of the memory. As shown in fig. 5, the following steps are included.

In step S501, the first time window is divided into a plurality of time periods.

In step S502, for a plurality of time periods, the statistical control system averages the amount of data to be processed in each time period.

In step S503, a plurality of average data amounts corresponding to a plurality of time periods are compared with a first set threshold value, respectively.

In step S504, it is determined whether or not each of the average data amounts is smaller than the first set threshold, and if all of the average data amounts are smaller than the first set threshold, step S505 is performed.

In step S505, garbage collection is instructed to be performed on the storage medium of the memory.

According to the embodiment, the control system of the memory determines whether the host is in a low power consumption state or not by counting the average data amount of each of a plurality of time periods in one time window and according to the size relation between each average data amount and the first set threshold value, so as to recycle garbage in the host low power consumption state. The judgment result obtained by the judgment mode is more accurate.

The control system of the memory in this embodiment determines the low load state of the host more accurately, so that garbage collection is performed at a more appropriate time, so as to avoid the problem that performance of the host is affected by selecting an inappropriate time to perform garbage collection to the greatest extent.

In some embodiments, the steps shown in fig. 5 are repeatedly performed, that is, when the average data amount corresponding to at least one time period in the first time window is greater than or equal to the first set threshold, the method shown in fig. 5 is performed for the second time window. The relation between the second time window and the first time window is not limited, and examples thereof can be seen in the following embodiments.

In some embodiments, the second time window is a time window after the first time window, in other embodiments, the multiple time periods into which the first time window is divided may be divided equally or non-equally, the first time window and the second time window may be divided equally in the same time step, or divided equally in different time steps, see in particular the description above for fig. 3 and fig. 4a to 4 b.

In some embodiments, the method further comprises: after garbage collection, if the storage type of the physical block is determined to be a type other than SLC (for example, one of MLC, TLC, QLC), it may be switched to SLC CACHE mode, after which the storage unit physically MLC, TLC, QLC will simulate writing and reading of SLC, thus improving the reading performance. Further, the physical block being written is closed.

In a further embodiment, the management method further includes: the use condition of the storage medium is monitored in real time, and the management method shown in fig. 5 is executed only when the use rate of the memory is greater than or equal to the second set threshold. The second set threshold may be a threshold used when a full disk is judged, for example, 95%, i.e., when a memory is judged to be full, garbage collection based on load monitoring is started.

The term "module" as used herein may refer to, be part of, or include the following: an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality.

Those skilled in the art will appreciate that the various modules or units of a data processing system according to the present disclosure may be implemented in hardware, firmware, or software. The software includes, for example, code programs formed using various programming languages such as JAVA, C/C++/C#, SQL, and the like. Although steps and sequences of steps of embodiments of the present disclosure are presented in terms of methods and apparatus, executable instructions that implement the specified logic functions may be rearranged to generate new steps. The order of the steps should not be limited to only the order of the steps in the method and method illustration, but may be modified at any time as required by the function. For example, some of the steps may be performed in parallel or in reverse order.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A management method for a memory, the memory including a control system and a storage medium, the management method performed by the control system, comprising:

2. The management method of claim 1, further comprising: if at least one of the plurality of average data amounts is greater than or equal to the first set threshold, repeating the management method within a second time window subsequent to the first time window.

3. The management method according to claim 1, wherein the first time window is equally divided into the plurality of time periods.

4. The management method of claim 1, further comprising: and switching the new physical block obtained by executing garbage collection into an SLC CACHE mode.

5. The management method according to claim 4, the management method further comprising: the physical block being written to is turned off to facilitate the control system switching to the SLC CACHE mode for write operations on other physical blocks.

6. The management method according to claim 1, which is executed only when the following condition is satisfied: the usage of the storage medium is greater than or equal to a second set threshold.

7. The management method according to claim 1, wherein the memory is a solid state disk, and the storage medium is a flash memory chip.

8. A control system for a memory, the memory comprising a control system and a storage medium, comprising:

an interface unit for receiving a command from a host;

a processor;

firmware, including computer instructions executed by a processor;

9. The control system of claim 8, the firmware stored computer instructions further comprising: after the garbage collection, the corresponding physical block is instructed to be switched to an SLC CACHE mode.

10. A solid state disk comprising the memory controller of claim 8 or 9 and a flash memory chip serving as a storage medium.