KR20180039802A - Data storage device and operating method thereof - Google Patents

Abstract

A data storage device includes a nonvolatile memory device which includes a reference memory region and a normal memory region and determines whether to perform a refresh operation based on the reference memory region, a controller which determines the first memory region of the normal memory region based on the history of a wear leveling operation in accordance with a determination result of the nonvolatile memory device, and controls the nonvolatile memory device to perform the refresh operation on a second memory region excluding the first memory region of the normal memory region. It is possible to save power and time.

Description

≪ Desc / Clms Page number 1 > DATA STORAGE DEVICE AND OPERATING METHOD THEREOF &

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and more particularly, to a data storage device including a non-volatile memory device.

The data storage device may be configured to store data provided from an external device in response to a write request of the external device. In addition, the data storage device may be configured to provide stored data to an external device in response to a read request of the external device. An external device is an electronic device capable of processing data, and may include a computer, a digital camera, a cellular phone, or the like. The data storage device may be built in an external device or operated in a detachable form and connected to an external device.

The data storage device may be a personal computer memory card (PCMCIA) card, a CF (compact flash) card, a smart media card, a memory stick, various multimedia cards (MMC, eMMC, RS-MMC, MMC- Digital (SD), Mini-SD, Micro-SD, Universal Flash Storage (UFS), or Solid State Drive (SSD).

The data storage device may include a non-volatile memory device for storing data. A non-volatile memory device can retain stored data even when power is not applied. The non-volatile memory device may be a flash memory device such as NAND Flash or NOR Flash, a Ferroelectrics Random Access Memory (FeRAM), a Phase-Change Random Access Memory (PCRAM), a Magnetic Random Access Memory (MRAM) A Resistive Random Access Memory (ReRAM), and the like.

An embodiment of the present invention is to provide a data storage device and a method of operation thereof that can save power and time consumed in performing a refresh operation.

A data storage device according to an embodiment of the present invention includes a nonvolatile memory device configured to include a reference memory area and a normal memory area and configured to determine whether to perform a refresh operation based on the reference memory area; And a controller for determining a first memory area of the normal memory area on the basis of a history of a wear leveling operation according to a result of the determination of the nonvolatile memory device and determining a first memory area in a second memory area excluding the first memory area And a controller configured to control the nonvolatile memory device to perform the refresh operation for the nonvolatile memory device.

According to another aspect of the present invention, there is provided a method of operating a data storage device including: determining whether to perform a refresh operation based on a reference memory area; Determining a first memory area of a normal memory area based on a history of a wear leveling operation in accordance with a determination result; And performing the refresh operation on a second memory area of the normal memory area except for the first memory area.

The data storage device and the operation method thereof according to the embodiment of the present invention can save power and time consumed in performing the refresh operation.

1 is a block diagram illustrating a non-volatile memory device in accordance with an embodiment of the present invention.
FIGS. 2A and 2B are diagrams for explaining a drift phenomenon of memory cells,
FIGS. 3A and 3B are diagrams for explaining a method of operating the state monitor unit for the reference memory area,
FIG. 4 is a flowchart showing the operation of the nonvolatile memory device of FIG. 1,
FIG. 5 is a flowchart showing the operation of the status monitor unit of FIG. 1,
6 is a block diagram illustrating a data storage device in accordance with an embodiment of the present invention.
FIG. 7 is a diagram for explaining how a wear leveling operation and a refresh operation are performed in the data storage device of FIG. 6;
FIG. 8 is a diagram for explaining how a wear leveling operation and a refresh operation are performed in the data storage device of FIG. 6;
9 is a flowchart showing an operation method of the controller of Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a non-volatile memory device 100 in accordance with an embodiment of the present invention.

The nonvolatile memory device 100 can store data according to the control of an external controller (not shown), and can maintain stored data without receiving power from the outside. In the following, the non-volatile memory device 100 may be a Resistive Random Access Memory (ReRAM). However, the embodiment of the present invention is not limited thereto, and the nonvolatile memory device 100 may be a flash memory device such as a NAND Flash or a NOR Flash, a ferroelectrics random access memory (FeRAM), a PCRAM Phase-Change Random Access Memory) and MRAM (Magnetic Random Access Memory).

The non-volatile memory device 100 may include a control unit 110, a reference memory area 120, and a normal memory area 130. [

The control unit 110 not only performs the write operation and the read operation with respect to the reference memory area 120 and the normal memory area 130 under the control of the controller but also ensures the data reliability of the nonvolatile memory device 100, Lt; RTI ID = 0.0 > and / or < / RTI > The management operations may include a status monitor operation and a refresh operation as described below.

The control unit 110 may include a status monitor unit 111 and a refresh unit 112.

The status monitor unit 111 may monitor the deterioration of the reference memory area 120 in order to determine whether or not a refresh operation should be performed on the normal memory area 130. [ The status monitor unit 111 can determine whether the reference memory cells in the reference memory area 120 that have been written to exist in the predetermined state have changed to the critical state by the drift phenomenon. That is, since the reference memory cells in the reference memory area 120 have the same structure as the normal memory cells in the normal memory area 130, the status monitor 111 monitors the deterioration of the reference memory area 120, The state deterioration of the memory area 130 can be estimated.

Specifically, the status monitor unit 111 counts the target reference memory cells among the reference memory cells that have been written so as to exist in the predetermined state, and when the counted number exceeds the threshold number, the refresh operation for the normal memory area 130 Can be determined to be performed. At this time, the status monitor unit 111 may count a reference memory cell having a resistance value larger than the critical resistance value among the reference memory cells as a target reference memory cell.

The refresh unit 112 may perform a refresh operation on the normal memory area 130 according to the determination of the status monitor unit 111. [ The refresh unit 112 may perform a refresh operation according to various known methods. The state of the normal memory cells in the normal memory region 130 may be deteriorated by the drift phenomenon according to the passage of time since the write operation is performed but can be recovered through the refresh operation.

The controller 110 may perform a write operation on the reference memory area 120 so that the reference memory cells in the reference memory area 120 are in a predetermined state after performing the refresh operation on the normal memory area 130 have. Therefore, the reference memory area 120 can reflect the deterioration of the state of the normal memory area 130 again.

As described above, the deterioration of the state of the reference memory area 120 can be monitored by the status monitor 111. [ The reference memory area 120 may store predetermined data so that the deterioration of the state can be determined through the change of the stored data. For example, the reference memory cells included in the reference memory area 120 may all be written to exist in a predetermined state.

The normal memory area 130 stores various data including data transmitted from the controller, and the refresh operation can be performed by the refresh unit 112. [

FIGS. 2A and 2B are diagrams for explaining the drift phenomenon of memory cells. In FIGS. 2A and 2B, the horizontal axis R indicates a resistance value of a memory cell, and the vertical axis Cell # indicates a number of memory cells.

First, the memory cells of the reference memory area 120 and the normal memory area 130 may exist in a set state or a reset state according to a data value stored through a write operation. The set state and the reset state can be classified according to the resistance value of the memory cell. That is, the memory cell having the resistance value smaller than the read resistance value Rrd exists in the set state, and the memory cell having the resistance value larger than the read resistance value Rrd may exist in the reset state. In FIG. 2A, the state distribution D1 includes memory cells in a set state, and the state distribution D2 may include memory cells in a reset state.

The read operation for the memory cell can be performed by passing a predetermined current through the memory cell and comparing the amount of current passing through the memory cell with the amount of reference current. The reference current amount may be an amount of current corresponding to the lead resistance value Rrd, that is, an amount of current passing through the memory cell having the lead resistance value Rrd. Therefore, when the resistance value of the memory cell is smaller than the read resistance value Rrd, that is, when the amount of current passing through the memory cell is larger than the reference current amount, it is determined that the memory cell is in the set state, That is, the set data can be read. When the resistance value of the memory cell is larger than the read resistance value Rrd, that is, when the amount of current passing through the memory cell is smaller than the reference current amount, it is determined that the memory cell is in the reset state, That is, the reset data can be read.

Referring to FIG. 2B, when the drift phenomenon 201 in which the resistance value of the memory cell increases with time, the state distribution D1 can move to the state distribution D3. At this time, if the read operation is performed based on the read resistance value Rrd, the reset data may be read from the memory cells 202 in which the set data was written, so that a read error may occur. The drift phenomenon 201 may occur in the reference memory region 120 and the normal memory region 130 in the same manner.

FIGS. 3A and 3B are diagrams for explaining a method of operating the state monitor unit 111 for the reference memory area 120. FIG.

Referring to FIG. 3A, first, reference memory cells in the reference memory area 120 can be written to exist in a set state. Thus, the reference memory cells can form the state distribution D1. Thereafter, as described with reference to FIG. 2B, the resistance values of the reference memory cells can be increased by the drift phenomenon, and the state distribution D1 can move to the state distribution D4.

The state monitor unit 111 detects the reference memory cells having the worst state based on the threshold resistance value Rth1 of the reference memory cells, that is, the target reference memory cells 302 having a resistance value larger than the threshold resistance value Rth1 You can count.

Specifically, the status monitoring unit 111 can perform a read operation on the reference memory cells based on the threshold current amount corresponding to the threshold resistance value Rth1. The threshold current amount may be an amount of current corresponding to the threshold resistance value Rth1, that is, an amount of current passing through the memory cell having the threshold resistance value Rth1. That is, the state monitor unit 111 passes the currents to the reference memory cells, compares the amounts of current passing through the reference memory cells with the threshold current amounts, respectively, and outputs the reference memory cells corresponding to the current amounts smaller than the threshold current amount to the target reference memory cells (302). In other words, the status monitor unit 111 may count the reference memory cells into which the reset data is read in the read operation based on the threshold current amount corresponding to the threshold resistance value Rth1, as the target reference memory cells 302. [

When the counted number exceeds the threshold number, the status monitor unit 111 may determine to perform the refresh operation with respect to the normal memory area 130. [

On the other hand, the threshold resistance value Rth1 is set to a value smaller than the lead resistance value Rrd, and the threshold number can be set in consideration of the margin 301. [

FIG. 3B shows a case where a status monitoring operation is performed according to the threshold resistance value Rth2 and the threshold number set differently from FIG. 3A.

In FIG. 3B, the reference memory cells of the reference memory area 120 are written to exist in a set state, and the reference memory cells may form the state distribution D1.

The state monitor unit 111 performs a refresh operation when all the reference memory cells have resistance values larger than the threshold resistance value Rth2, that is, when the state distribution D1 of the reference memory cells shifts to the state distribution D5 It can be decided to perform. In other words, the status monitor unit 111 can determine to perform the refresh operation when the reset data is read from all the reference memory cells in the read operation based on the threshold current amount corresponding to the threshold resistance value Rth2.

The threshold resistance value Rth2 may be set in consideration of the margin 303. [

On the other hand, the state monitoring operation is performed such that the time required for the resistance value of the memory cell written in the set state to increase to the lead resistance value Rrd, i.e., the drift time is experimentally calculated and set to be performed periodically within the calculated time . The drift time can be calculated through a test in which the set data is written to the memory cell and then the read operation is repeated until the reset data is read.

4 is a flowchart showing the operation of the nonvolatile memory device 100 of FIG.

4, in step S110, the controller 110 performs a write operation on the reference memory cells such that the reference memory cells of the reference memory area 120 are in a predetermined state, for example, a set state .

In step S120, the status monitor unit 111 can determine whether to perform the refresh operation based on the reference memory area 120. [ The specific operation of the status monitor unit 111 will be described in detail with reference to FIG. When it is determined to perform the refresh operation, the procedure can move to step S130. When it is determined not to perform the refresh operation, the procedure can be terminated.

In step S130, the refresh unit 112 may perform a refresh operation on the normal memory area 130. [

5 is a flowchart showing the operation of the status monitor 111 of FIG. The procedure shown in Fig. 5 may be the embodiment of step S120 of Fig.

The status monitor unit 111 may count the target reference memory cells among the one or more reference memory cells included in the reference memory area 120 in step S210. Each of the target reference memory cells may have a resistance value greater than the threshold resistance value. The state monitor unit 111 passes the currents to the reference memory cells, compares the amounts of current passing through the reference memory cells with the threshold current amounts corresponding to the threshold resistance values, respectively, and outputs reference memory cells corresponding to the current amounts smaller than the threshold current amount Can be counted as target reference memory cells.

In step S220, the status monitor unit 111 may determine whether the counted number exceeds the threshold number. When it is determined that the counted number exceeds the threshold number, the procedure may move to step S230. When it is determined that the counted number does not exceed the threshold number, the procedure may terminate.

In step S230, the status monitor unit 111 may determine to perform the refresh operation.

6 is a block diagram illustrating a data storage device 1 according to an embodiment of the present invention.

The data storage device 1 may include a controller 10 and a non-volatile memory device 200.

The controller 10 can control the write operation and the read operation of the nonvolatile memory device 200. [ The controller 10 controls the refresh operation of the nonvolatile memory device 200 through the refresh management unit 11 to ensure the data reliability of the nonvolatile memory device 200, The wear leveling operation can be performed through the wear leveling unit 12 to extend the service life.

The refresh management section 11 can control the nonvolatile memory device 200 to perform the refresh operation more efficiently. Specifically, when it is determined that the refresh operation should be performed by the state monitor unit 211 according to the above-described method, the refresh management unit 11 updates the normal memory area 230 in the normal memory area 230 based on the execution history of the wear leveling operation. 1 memory area 231 and controls the nonvolatile memory device 200 to perform a refresh operation on the second memory area 232 excluding the first memory area 231 of the normal memory area 230 . The first memory area 231 may include memory units on which the wear leveling operation has been performed until it is determined that the current refresh operation is to be performed after the previous refresh operation is performed. As will be described later, since the drift effect is removed through the wear leveling operation in the first memory area 231, the refresh operation may not be required. Therefore, the unnecessary refresh operation is not performed, so that the power and time consumed in the refresh operation can be reduced.

The wear leveling unit 12 may perform a wear leveling operation such that the normal memory area 230 of the non-volatile memory device 200 is uniformly worn. On the other hand, the wear leveling operation may involve a write operation. Therefore, the refresh operation may not be required in the first memory region 231 in which the wear leveling operation has been performed since the drift effect has been removed once. The wear leveling unit 12 may store information about the memory area where the wear leveling operation is performed.

Non-volatile memory device 200 may be configured and operative substantially similar to non-volatile memory device 100 of FIG. The nonvolatile memory device 200 may include a control unit 210 including a status monitor unit 211 and a refresh unit 212, a reference memory area 220, and a normal memory area 230. The state monitor unit 211 monitors the change in the state of the reference memory area 220 so as to determine the first memory area 231 in which the refresh operation is not to be performed when it is determined that the refresh operation should be performed, 200 to the refresh management unit 11. The refresh unit 212 can perform a refresh operation on the second memory area 232 excluding the first memory area 231 in the normal memory area 230 under the control of the refresh management unit 11. [

FIG. 7 is a diagram for explaining how a wear leveling operation and a refresh operation are performed in the data storage device 1 of FIG. FIG. 7 shows a normal memory area 230 including memory units corresponding to addresses "0" to "7 "

Before starting the description, the wear leveling operation in Fig. 7 may be performed for the first and second memory units selected according to the swap algorithm. Specifically, the wear leveling unit 12 can sequentially select the first one of the memory units, for example, by increasing the address, whenever the wear leveling operation is performed. Further, the wear leveling section 12 can select the memory unit of the next address for the first memory unit as the second memory unit each time the wear leveling operation is performed. The wear leveling unit 12 may exchange data stored in the first memory unit and data stored in the second memory unit with each other whenever the wear leveling operation is performed. Thus, the memory units can be accessed evenly and can be wear-leveled. On the other hand, according to the embodiment, the second memory unit may not be the memory unit of the next address for the first memory unit, but may be another memory unit selected according to a predetermined rule.

Referring to FIG. 7, when it is determined in the time zone T1 that the refresh operation is necessary by the status monitor unit 211, the refresh management unit 11 determines whether or not the refresh operation is required for all the memory units at addresses "0" The nonvolatile memory device 200 can be controlled to perform the refresh operation.

Various host operations such as a write operation and a read operation can be performed under the control of the host device between the time zone T1 and the time zone T2. On the other hand, the wear leveling operation may be performed periodically, for example, every time the write operation by the host device is performed a predetermined number of times. As a result, a wear leveling operation can be performed according to the swap algorithm in the time zones T2 to T4.

Specifically, in the time zone T2, the wear leveling unit 12 can exchange data stored in the first and second memory units, that is, the memory units of the addresses "0" and "1 " In the time zone T3, the wear leveling unit 12 may exchange data stored in the memory units of the addresses "1" and "2 " The wear leveling unit 12 in the time zone T4 may exchange data stored in the memory units of the addresses "2" and "3 "

When it is determined in the time zone T5 that the refresh operation is required by the status monitor unit 211, the refresh management unit 11 performs a wear leveling operation (a refresh operation) during the time period T1 from the previous refresh operation to the time period T5 Volatile memory device 200 can be controlled to perform the refresh operation only for the memory units from addresses "4" to "7 " except for the memory units from addresses" 0 &

That is, for example, in the memory unit of the address "0", if the write operation is performed through the wear leveling operation in the time zone T2, the drift effect generated before will be removed. In the memory unit at the address "0 ", since only a weak drift effect occurs from the time zone T2 to the time zone T5, the refresh operation can be omitted. Similarly, the refresh operation can be omitted because the drift effect is eliminated even in the memory units from addresses "1" to "3 ", so that the power and time consumed in the refresh operation can be reduced.

FIG. 8 is a diagram for explaining how a wear leveling operation and a refresh operation are performed in the data storage device of FIG. 6. FIG. In Fig. 8, the wear leveling operation can be performed according to the gap specification algorithm, unlike the swap algorithm applied in the wear leveling operation in Fig.

In the gap algorithm, two memory units to be subjected to the wear leveling operation, that is, a memory unit to be designated as a gap and a memory unit previously designated as a gap, can be selected. The wear leveling unit 12 can sequentially select the memory units to be designated as the gaps among the memory units, for example, by increasing the addresses each time the wear leveling operation is performed. A memory unit designated as a gap may not be used for storing data. The wear leveling unit 12 may copy the data stored in the memory unit to be designated as the gap to the memory unit previously designated as the gap every time the wear leveling operation is performed. That is, the wear leveling unit 12 can change the gap while increasing the address each time the wear leveling operation is performed. As a result, the memory units can be accessed evenly.

Specifically, in the time zone T11, the refresh operation can be performed on the memory units at addresses "1" to "7" as the state monitor unit 211 determines that the refresh operation is necessary. The memory unit at address "0 " may be an area designated as a gap and an area not used for storing data.

After the write operation by the host apparatus is performed a predetermined number of times from the time period T11, the ware leveling unit 12 writes the data stored in the memory unit of the address "1 " Unit and replace the gap from the memory unit at address "0 " to the memory unit at address" 1 ". Similarly, after the write operation by the host apparatus is performed a predetermined number of times from the time period T12, the ware leveling unit 12 sets the data stored in the memory unit at the address "2 "Quot; 1 "to a memory unit at address" 2 ". After the write operation by the host device is performed a predetermined number of times from the time period T13, the ware leveling unit 12 writes the data stored in the memory unit at the address "3 " Unit and replace the gap with a memory unit at address "2" from a memory unit at address " 3 ".

Then, in the time period T15, the state monitoring unit 211 can perform the refresh operation according to the determination. At this time, the refresh management unit 11 stores the memory units from the addresses "0" to "3 " at which the ware leveling operation was performed during the time period T11 to the time period T15 during which the previous refresh operation was performed, The nonvolatile memory device 200 can be controlled so that the refresh operation is performed only for the memory units at addresses "4" to "7 " That is, the memory units at addresses "0" to "2" which were gaps between the time periods T11 and T15 have been removed from the drift effect through the write operation and the memory unit at the address "3" The refresh operation will not be required.

9 is a flowchart showing an operation method of the controller 10 of Fig. The controller 10 may determine to control the refresh operation of the nonvolatile memory device 200 according to the report of the status monitor 211. [

In step S310, the controller 10 can determine the first memory area 231 of the normal memory area 230 based on the execution history of the wear leveling operation. According to the embodiment, the controller 10 may determine the memory units in which the swap operation has been performed as the first memory area 231 after the previous refresh operation is performed. According to an embodiment, the controller 10 may determine the memory units designated as gaps to be the first memory area 231 after the previous refresh operation has been performed.

In step S320, the nonvolatile memory device 200 performs a refresh operation on the second memory area 232 excluding the first memory area 231 in the normal memory area 230 under the control of the controller 10 Can be performed.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims rather than by the foregoing description, It should be understood as. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: Nonvolatile memory device
110:
111:
112: Refresh portion
120: Reference memory area
130: Normal memory area

Claims (12)

A nonvolatile memory device including a reference memory area and a normal memory area, the nonvolatile memory device being configured to determine whether to perform a refresh operation based on the reference memory area; And
Determining a first memory area of the normal memory area on the basis of a history of a wear leveling operation according to a result of the determination of the nonvolatile memory device and determining a first memory area of the normal memory area excluding the first memory area And a controller configured to control the non-volatile memory device to perform the refresh operation. The method according to claim 1,
Wherein the nonvolatile memory device counts target reference memory cells among one or more reference memory cells included in the reference memory area and determines to perform the refresh operation when the counted number exceeds a threshold number,
Wherein each of the target reference memory cells has a resistance value greater than a threshold resistance value. 3. The method of claim 2,
The nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is configured to pass a current through each of the reference memory cells, compare amounts of currents passing through the reference memory cells with a threshold current amount corresponding to the threshold resistance value, And counting the reference memory cells as the target reference memory cells. 3. The method of claim 2,
Wherein the nonvolatile memory device performs a write operation on the reference memory cells such that the reference memory cells are in a predetermined state after performing the refresh operation. The method according to claim 1,
Wherein the controller determines the memory units in which the swap operation has been performed to be the first memory area after the previous refresh operation is performed based on the execution history of the wear leveling operation. The method according to claim 1,
Wherein the controller determines the memory units designated as gaps to be the first memory area after the previous refresh operation is performed based on the execution history of the wear leveling operation. Determining whether to perform a refresh operation based on a reference memory area;
Determining a first memory area of a normal memory area based on a history of a wear leveling operation in accordance with a determination result; And
And performing the refresh operation on a second memory area of the normal memory area excluding the first memory area. 8. The method of claim 7,
Wherein the step of determining whether to perform the refresh operation comprises:
Counting target reference memory cells of one or more reference memory cells included in the reference memory region, each of the target reference memory cells having a resistance value greater than a threshold resistance value;
And when the counted number exceeds a threshold number, determining to perform the refresh operation. 9. The method of claim 8,
Wherein counting the target reference memory cells comprises:
Passing current through the reference memory cells, respectively;
Comparing the amounts of current passing through the reference memory cells with a threshold current amount corresponding to the threshold resistance value, respectively; And
And counting reference memory cells corresponding to an amount of current less than the threshold current amount as the target reference memory cells. 9. The method of claim 8,
Further comprising performing a write operation on the reference memory cells such that the reference memory cells are in a predetermined state after performing the refresh operation. 8. The method of claim 7,
Wherein determining the first memory area comprises:
And determining the memory units in which the swap operation has been performed as the first memory area after the previous refresh operation is performed, based on the execution history of the wear leveling operation. 8. The method of claim 7,
Wherein determining the first memory areas comprises:
Determining a memory unit designated as a gap as the first memory area after a previous refresh operation is performed, based on the execution history of the wear leveling operation.

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