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CN116110853A - 一种改善源漏外延层与栅极桥接的方法 - Google Patents

一种改善源漏外延层与栅极桥接的方法 Download PDF

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CN116110853A
CN116110853A CN202111327354.3A CN202111327354A CN116110853A CN 116110853 A CN116110853 A CN 116110853A CN 202111327354 A CN202111327354 A CN 202111327354A CN 116110853 A CN116110853 A CN 116110853A
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明涉及改善源漏外延层与栅极桥接的方法，涉及半导体集成电路技术，通过在形成多晶硅栅行的刻蚀工艺之后增加对鳍体底部间的绝缘层进行刻蚀的工艺，然后形成侧墙和硬掩膜层，之后再形成源漏外延层，如此由于增加的对鳍体底部间的绝缘层进行刻蚀的工艺，使位于外延层与多晶硅栅极下的孔洞间隔离，而避免栅极结构的多晶硅与源漏外延层的桥接，而提高器件性能。

Description

一种改善源漏外延层与栅极桥接的方法
技术领域
本发明涉及半导体集成电路技术，尤其涉及一种改善源漏外延层与栅极桥接的方法。
背景技术
随着半导体工艺不断发展，器件的尺寸也不断缩小，鳍式晶体管应运而生。
现有鳍式晶体管包括：形成于半导体衬底上的鳍体，鳍体包括多条且平行排列，鳍体的底部通过绝缘层隔离，鳍式晶体管还包括多晶硅栅，多晶硅栅也包括多条且平行排列，各多晶硅栅的长度方向和鳍体的长度方向垂直，被多晶硅栅所覆盖的鳍体的表面用于形成沟道，之后通过金属替代工艺在多晶硅栅的形成区域形成金属栅。另鳍式晶体管可为N型鳍式晶体管和P型鳍式晶体管。N型鳍式晶体管的金属栅的两侧形成源区和漏区，且源区和漏区中形成有嵌入式SiP外延层。如为P型鳍式晶体管，源区和漏区中形成有嵌入式SiGe外延层。不同的外延层轮廓导致不同的压力和器件性能，较大的外延层有利于形成较大压力和较低的阻抗，但增加外延层的体积存在导致外延层和栅极桥接的问题，而影响器件性能。
发明内容
本发明在于提供一种改善源漏外延层与栅极桥接的方法，包括：S1：提供半导体衬底，在半导体衬底上形成多条鳍体，所述多条鳍体并行排列，在所述鳍体的底部形成绝缘层，以隔离各所述鳍体；S2：形成多晶硅栅层，并进行刻蚀工艺形成多条多晶硅栅行，所述多条多晶硅栅行并行排列，且所述多条多晶硅栅行的长度方向和所述多条鳍体的长度方向垂直排列，而在所述多条多晶硅栅行和所述多条鳍体的交叉区域分别形成伪栅极结构；S3：对鳍体的底部间的绝缘层进行刻蚀工艺，以去除第一厚度的绝缘层，保留部分厚度的绝缘层；S4：形成侧墙，所述侧墙覆盖裸露的鳍体表面、鳍体间的绝缘层表面及多晶硅栅行表面；S5：在侧墙上形成硬掩膜层；S6：在鳍体上的伪栅极结构的两侧形成源区或漏区，且源区或漏区中形成有嵌入式沟槽；以及S7：在沟槽内形成嵌入式外延层，嵌入式外延层作为源漏外延层。
更进一步的，绝缘层采用浅沟槽场氧。
更进一步的，嵌入式外延层包括嵌入式SiGe外延层和嵌入式SiP外延层。
更进一步的，嵌入式SiP外延层形成于N型鳍式晶体管的伪栅极结构两侧的源区或漏区中；嵌入式SiGe外延层形成于P型鳍式晶体管的伪栅极结构两侧的源区或漏区中。
更进一步的，所述第一厚度h1为2nm至10nm之间。
更进一步的，所述第一厚度h1为5nm。
更进一步的，采用沉积工艺形成所述侧墙。
更进一步的，采用沉积工艺形成所述硬掩膜层。
更进一步的，采用刻蚀工艺形成所述沟槽。
更进一步的，所述沟槽260为∑形沟槽。
附图说明
图1至图5为本发明一实施例的鳍式场效应晶体管源漏外延层形成过程的立体结构示意图。
具体实施方式
下面将结合附图，对本发明中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在不做出创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
应当理解，本申请的权利要求及说明书中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。本申请的说明书和权利要求书中使用的术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
本发明一实施例中，在于提供一种改善源漏外延层与栅极桥接的方法，包括：
S1：提供半导体衬底，在半导体衬底上形成多条鳍体，所述多条鳍体并行排列，在所述鳍体的底部形成绝缘层，以隔离各所述鳍体；S2：形成多晶硅栅层，并进行刻蚀工艺形成多条多晶硅栅行，所述多条多晶硅栅行并行排列，且所述多条多晶硅栅行的长度方向和所述多条鳍体的长度方向垂直排列，而在所述多条多晶硅栅行和所述多条鳍体的交叉区域分别形成伪栅极结构；S3：对鳍体的底部间的绝缘层进行刻蚀工艺，以去除第一厚度的绝缘层，保留部分厚度的绝缘层；S4：形成侧墙，所述侧墙覆盖裸露的鳍体表面、鳍体间的绝缘层表面及多晶硅栅行表面；S5：在侧墙上形成硬掩膜层；S6：在鳍体上的伪栅极结构的两侧形成源区或漏区，且源区或漏区中形成有嵌入式沟槽；S7：在沟槽内形成嵌入式外延层，嵌入式外延层作为源漏外延层。
具体的，请参阅图1至图5，图1至图5为本发明一实施例的鳍式场效应晶体管源漏外延层形成过程的立体结构示意图；本发明的改善源漏外延层与栅极桥接的方法，包括：
S1：如图1所示，提供半导体衬底200，在半导体衬底200上形成多条鳍体210，所述多条鳍体210并行排列，在所述鳍体210的底部形成绝缘层220，以隔离各所述鳍体210；
本发明一实施例中，半导体衬底与多条鳍体210的材质相同，如硅，也即多条鳍体210由衬底或形成于衬底上的外延层形成。在本发明一实施例中，通过对半导体衬底进行光刻刻蚀形成多条鳍体210。在本发明一实施例中，绝缘层220通常采用浅沟槽场氧。
S2：如图1所示，形成多晶硅栅层，并进行刻蚀工艺形成多条多晶硅栅行230，所述多条多晶硅栅行230并行排列，且所述多条多晶硅栅行230的长度方向和所述多条鳍体210的长度方向垂直排列，而在所述多条多晶硅栅行230和所述多条鳍体210的交叉区域分别形成伪栅极结构；
S3：如图2所示，对鳍体底部间的绝缘层220进行刻蚀工艺，以去除第一厚度h1的绝缘层，保留部分厚度的绝缘层；
本发明一实施例中，所述第一厚度h1为2nm至10nm之间。
本发明一实施例中，较佳的，所述第一厚度h1为5nm。
S4：如图3所示，形成侧墙240，所述侧墙240覆盖裸露的鳍体210表面、鳍体间的绝缘层220表面及多晶硅栅行230表面；
本发明一实施例中，采用沉积工艺形成所述侧墙240。
S5：如图3所示，在侧墙240上形成硬掩膜层250；
本发明一实施例中，采用沉积工艺形成所述硬掩膜层250。
S6：如图4所示，在鳍体上的伪栅极结构的两侧形成源区或漏区，且在源区或漏区中形成嵌入式沟槽260；
本发明一实施例中，采用刻蚀工艺形成所述沟槽260。
本发明一实施例中，所述沟槽260为∑形沟槽。
S7：如图5所示，在沟槽260内形成嵌入式外延层，嵌入式外延层作为源漏外延层270。
本发明一实施例中，采用沉积工艺形成所述嵌入式外延层。
本发明一实施例中，嵌入式外延层包括嵌入式SiGe外延层和嵌入式SiP外延层。其中嵌入式SiP外延层形成于N型鳍式晶体管的伪栅极结构两侧的源区或漏区中；嵌入式SiGe外延层形成于P型鳍式晶体管的伪栅极结构两侧的源区或漏区中。
如上所述，通过在形成多晶硅栅行的刻蚀工艺之后增加对鳍体底部间的绝缘层进行刻蚀的工艺，然后形成侧墙和硬掩膜层，之后再形成源漏外延层，如此由于增加的对鳍体底部间的绝缘层进行刻蚀的工艺，使位于外延层与多晶硅栅极下的孔洞间隔离，而避免栅极结构的多晶硅与源漏外延层的桥接，而提高器件性能。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种改善源漏外延层与栅极桥接的方法，其特征在于，包括：
S1：提供半导体衬底，在半导体衬底上形成多条鳍体，所述多条鳍体并行排列，在所述鳍体的底部形成绝缘层，以隔离各所述鳍体；
S2：形成多晶硅栅层，并进行刻蚀工艺形成多条多晶硅栅行，所述多条多晶硅栅行并行排列，且所述多条多晶硅栅行的长度方向和所述多条鳍体的长度方向垂直排列，而在所述多条多晶硅栅行和所述多条鳍体的交叉区域分别形成伪栅极结构；
S3：对鳍体的底部间的绝缘层进行刻蚀工艺，以去除第一厚度的绝缘层，保留部分厚度的绝缘层；
S4：形成侧墙，所述侧墙覆盖裸露的鳍体表面、鳍体间的绝缘层表面及多晶硅栅行表面；
S5：在侧墙上形成硬掩膜层；
S6：在鳍体上的伪栅极结构的两侧形成源区或漏区，且源区或漏区中形成有嵌入式沟槽；以及
S7：在沟槽内形成嵌入式外延层，嵌入式外延层作为源漏外延层。
2.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，绝缘层采用浅沟槽场氧。
3.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，嵌入式外延层包括嵌入式SiGe外延层和嵌入式SiP外延层。
4.根据权利要求3所述的改善源漏外延层与栅极桥接的方法，其特征在于，嵌入式SiP外延层形成于N型鳍式晶体管的伪栅极结构两侧的源区或漏区中；嵌入式SiGe外延层形成于P型鳍式晶体管的伪栅极结构两侧的源区或漏区中。
5.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，所述第一厚度h1为2nm至10nm之间。
6.根据权利要求5所述的改善源漏外延层与栅极桥接的方法，其特征在于，所述第一厚度h1为5nm。
7.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，采用沉积工艺形成所述侧墙。
8.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，采用沉积工艺形成所述硬掩膜层。
9.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，采用刻蚀工艺形成所述沟槽。
10.根据权利要求1所述的改善源漏外延层与栅极桥接的方法，其特征在于，所述沟槽260为∑形沟槽。
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