CN116013987A - A kind of SiC VDMOSFET power device and its preparation method - Google Patents

Abstract

The invention discloses a structure of a SiC VDMOSFET power device, which comprises: an N-type SiC substrate, a drain electrode positioned on the back surface and the front surface of the N-type SiC substrate, and an N-type epitaxial layer; two P well regions are formed by injection at two sides of the N-type epitaxial layer, a P+ contact region and an N+ source region are sequentially formed in each P well region, the P+ contact region is far away from the JFET region, and the N+ source region is adjacent to the P+ contact region and is close to the JFET region; the first layer of gate oxide layer is arranged on the N-type epitaxial layer and is positioned above the JFET region, the channel and part of the N+ source region, the first layer of gate oxide layer above the channel is downwards concave, a gate is formed on the first layer of gate oxide layer, and a source is formed on the P+ contact region and part of the N+ source region. The concave gate oxide layer is formed through dry etching, the gate oxide layer is thick above the JFET region and thin above the channel, the threshold voltage of the device is reduced under the condition that the electric field intensity born by the gate oxide layer is not affected, and the performance and reliability of the device are improved.

Description

A kind of SiC VDMOSFET power device and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, and more specifically, the invention relates to a SiC VDMOSFET power device and a preparation method thereof.

Background technique

As a representative of the third-generation semiconductor material, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap width, high breakdown electric field, high thermal conductivity, high electron saturation rate, and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate at higher temperatures It can run stably under low conditions, and is also suitable for high voltage and high frequency scenarios. At the same time, SiC material is the only semiconductor other than Si material that can grow _SiO2 through thermal oxidation, which provides a reference process for the development of voltage-controlled device MOSFET gate oxide, making MOSFET widely used. For the voltage-controlled power device SiC VDMOSFET, it realizes the conduction of the conductive channel by applying pressure on the gate oxide layer. Therefore, the quality of the gate oxide layer determines whether the entire device can work properly.

Application publication number CN 114446785 A, application publication date 2022.05.06, patent name: A preparation process for improving the threshold voltage stability of silicon carbide VDMOSFET devices, which is to prepare the gate oxide layer by high-temperature thermal oxidation in an oxygen environment; due to SiC After its thermal oxidation, there are a large number of dangling bonds, carbon clusters and near-interface traps in the gate oxide layer, which has a very high interface state density, which seriously affects the reliability of the gate oxide and the normal operation of SiC VDMOSFET. .

Contents of the invention

The present invention provides a structure of a SiC VDMOSFET power device, aiming to improve the above problems.

The present invention is achieved like this, a kind of structure of SiC VDMOSFET power device, described structure comprises:

N-type SiC substrate 2, drain 1 and N-type epitaxial layer 3 located on the back and front of N-type SiC substrate 2;

Two P well regions 4 are implanted on both sides of the N-type epitaxial layer 3, and a P+ contact region 5 and an N+ source region 6 are sequentially formed in each P well region 4. The P+ contact region 5 is set away from the JFET region, and the N+ source region 6 is adjacent to the P+ contact area 5 and is set close to the JFET area;

The first layer of gate oxide layer 9 arranged on the N-type epitaxial layer is located above the JFET region, the channel and part of the N+ source region 6, and the first layer of gate oxide layer 9 above the channel is concave downwards, on the first A gate 10 is formed on the gate oxide layer, and a source is formed on the P+ contact region 5 and part of the N+ source region 6 .

Further, the SiC VDMOSFET power device also includes:

The second gate oxide layer 8 is located between the first gate oxide layer 9 and the N-type epitaxial layer 3 , and is located above the JFET region, channel and part of the N+ source region 6 .

Further, thermal oxidation is performed on the N-type epitaxial layer 3 with the shallow implantation of phosphorous ions to form a second gate oxide layer 8 .

Further, two lightly doped N-type regions 7 are formed in the P well region 4 , which are respectively adjacent to the JFET region and the N+ source region 6 .

The present invention is achieved like this, a kind of preparation method of SiC VDMOSFET power device, described method comprises the steps:

S1. Epitaxially growing an N-type epitaxial layer 3 on the front side of the N-type SiC substrate 2;

S2, forming two P well regions 4 by ion implantation on both sides of the front side of the N-type epitaxial layer 3,

S3. Perform ion implantation at the P well region 4 away from the JEFT region to form a P+ contact region 5, and perform ion implantation at the P well region 4 close to the JFET region and close to the P+ contact region 5 to form an N+ source region 6 ;

S4, forming a shallow phosphorous ion implantation layer on the top of the N-type epitaxial layer 3, and activating the implanted ions;

S5. Deposit a _SiO2 layer on the JFET region, channel and part of the N+ source region 6, form a _SiO2 oxide layer by thermal oxidation, and consume the phosphorus ion shallow implantation layer, and perform annealing in NO;

S6. Etching the _SiO2 oxide layer to form the second gate oxide layer 8, dry etching the _SiO2 layer to form the first gate oxide layer with a thick thickness above the JFET region and a thin thickness above the channel layer 9;

S7, forming a gate 10 on the first gate oxide layer 9, forming a source 11 on the P+ contact region 5 and a part of the N+ source region 6 away from the JFET region, and forming a source electrode 11 on the N-type SiC substrate Bottom 2 backside drain 1.

Further, the formation process of the phosphorus ion shallow implantation layer on the top of the N-type epitaxial layer 3 is as follows:

Deposit a SiO ₂ cushion layer on the N-type epitaxial layer, and then perform phosphorus ion implantation. After the implantation, remove all the SiO ₂ cushion layer, and form a phosphorus ion shallow implantation layer on the top of the N-type epitaxial layer 3 .

Further, the thickness of the second gate oxide layer is 20-30 nm, and the thickness of the first gate oxide layer is 60-80 nm.

Further, the etching thickness of the SiO ₂ layer is 40-60nm, and the etching width is slightly larger than the width of the trench to form the first gate oxide layer.

Further, after step S3 and before step S4, the method further includes: performing sub-implantation on both sides of the channel between the N+ source region 6 and the JEFT region to form a lightly doped N-type region 7 .

The present invention uses a recessed gate oxide layer and additionally adds two lightly doped N-type regions on both sides of the channel, combined with phosphorus ion shallow implantation pretreatment to form a thin oxide layer by thermal oxidation and PECVD deposited _SiO2 layer In this way, the gate oxide layer with the target thickness can be efficiently prepared, without affecting the withstand voltage capability of the gate oxide layer, the effect of reducing the threshold voltage of SiC VDMOSFET and the defect of the gate oxide layer can be achieved, and the thermal electron degradation effect can be prevented, and the improvement can be achieved. device performance and reliability.

Description of drawings

Fig. 1 is the structural representation of the SiC VDMOSFET power device that the embodiment of the present invention provides;

Fig. 2 is the flow chart of the SiC VDMOSFET power device preparation method provided by the embodiment of the present invention;

3 is a schematic diagram of the device structure after forming an N-type epitaxial layer provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a device structure after forming a P well region provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a device structure after forming a P+ contact region provided by an embodiment of the present invention;

6 is a schematic diagram of a device structure after forming an N+ source region provided by an embodiment of the present invention;

FIG. 7 is a schematic diagram of a device structure after forming a lightly doped N-type region provided by an embodiment of the present invention;

FIG. 8 is a schematic diagram of the device structure after forming a shallow phosphorous ion implantation layer provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of the device structure after depositing a _SiO2 layer provided by an embodiment of the present invention;

Fig. 10 is a schematic diagram of the device structure after forming an _SiO2 oxide layer after thermal oxidation provided by an embodiment of the present invention;

FIG. 11 is a schematic diagram of a device structure after forming a second gate oxide layer according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of the device structure after forming the first gate oxide layer provided by the embodiment of the present invention;

FIG. 13 is a schematic diagram of a device structure after forming a gate provided by an embodiment of the present invention;

FIG. 14 is a schematic diagram of a device structure after forming a source provided by an embodiment of the present invention;

1. Drain, 2. N-type SiC substrate, 3. N-type epitaxial layer, 4. P well region, 5. P+ contact region, 6. N+ source region, 7. Lightly doped N-type region, 8. The first Two layers of gate oxide layer, 9. first layer of gate oxide layer, 10. gate, 11. source. 12. Phosphorus ion shallow implantation layer.

Detailed ways

The specific implementation of the present invention will be described in further detail below by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art have a more complete, accurate and in-depth understanding of the inventive concepts and technical solutions of the present invention.

FIG. 1 is a schematic structural diagram of a SiC VDMOSFET power device provided by an embodiment of the present invention. For convenience of description, only the parts related to the embodiment of the present invention are shown.

VDMOSFET is a vertical conductive double-diffused MOSFET power device. The SiC VDMOSFET power device includes:

Drain 1-type SiC substrate 2, N-type epitaxial layer 3, P well region 4, P+ contact region 5, N+ source region 6, first gate oxide layer 9, gate 10, source 11;

N-type SiC substrate 2, drain electrode 1 and N-type epitaxial layer 3 are respectively formed on the back and front of N-type SiC substrate 2; two P well regions 4 are formed on both sides of N-type epitaxial layer 3, In the region 4, a P+ contact region 5 and an N+ source region 6 are sequentially formed. The P+ contact region 5 is set away from the JFET region, and the N+ source region 6 is adjacent to the P+ contact region 5 and is set close to the JFET region; A gate oxide layer 9 is located above the JFET region, channel and part of the N+ source region 6; the first gate oxide layer 9 above the channel is concave downward, and a gate 10 is formed on the first gate oxide layer , forming a source on the P+ contact region 5 and part of the N+ source region 6 .

In the present invention, the recessed gate oxide layer is formed by dry etching, the gate oxide layer is thicker above the JFET region, and thinner above the channel, without affecting the electric field strength of the gate oxide layer, The threshold voltage of the device is reduced, and the performance and reliability of the device are improved.

In an embodiment of the present invention, the SiC VDMOSFET power device also includes:

The second gate oxide layer 8 is located between the first gate oxide layer 9 and the N-type epitaxial layer 3 , and is located above the JFET region, channel and part of the N+ source region 6 .

In the embodiment of the present invention, two lightly doped N-type regions 7 are formed in each P well region 4, respectively adjacent to the JFET region and N+ source region 6; lightly doped N-type regions are added to the upper parts of the SiC VDMOSFET channel. type region, which reduces the hole concentration of the channel to a certain extent, thereby reducing the threshold voltage of the device and improving the performance of the oxide layer; in addition, the existence of the lightly doped N-type region can prevent the thermal electron degradation effect .

Fig. 2 is the flow chart of the SiC VDMOSFET power device preparation method provided by the embodiment of the present invention, the method specifically includes the following steps:

S1. Select an N-type SiC substrate 2 with a doping concentration of 1e19cm ⁻³ ;

S2. Forming an N-type epitaxial layer 3 by epitaxial growth on the front side of the N-type SiC substrate 2, and its doping concentration is 8e15cm ^-3 to 1.5e16 cm ^-3 , as shown in FIG. 3 ;

S3. Two P well regions 4 are formed by ion implantation on both sides of the N-type epitaxial layer 3, the implanted ions are aluminum ions, the doping concentration is 1e17cm ^-3 ~ 1e18cm ^-3 , and the implantation depth is 0.8um ~ 1um, as shown in the figure 4 shown;

S4. Perform ion implantation in the P well region 4 away from the JEFT region to form a P+ contact region 5, the implanted ions are aluminum ions, the doping concentration is 1e19 cm ^-3 , and the implantation depth is 0.4-0.5um, as shown in FIG. 5 ;

S5. Perform ion implantation in the P well region 4 close to the JFET region and close to the P+ contact region 5 to form the N+ source region 6. The implanted ions are phosphorus ions, the doping concentration is 1e19 cm ^-3 , and the implantation depth is 0.4-0.5um ,As shown in Figure 6;

S6. Deposit a 50-100nm _SiO2 cushion layer on the N-type epitaxial layer 3, and then perform phosphorus ion implantation. After the implantation, remove all the _SiO2 cushion layer, and form a phosphorus ion shallow implantation layer on the top of the N-type epitaxial layer 3 12. The doping concentration is less than 1e19 cm ^-3 , and the implantation depth is 0.01-0.02um, as shown in Figure 8;

S7. Perform high-temperature annealing to activate the implanted ions, the annealing temperature is 1300°C-1600°C, and the time is 15-30min;

S8. Deposit a 60-80 nm SiO ₂ layer by PECVD on the JFET region, channel and part of the N+ source region 6, as shown in FIG. 9 .

S9. Form a 20-30nm _SiO2 oxide layer by thermal oxidation, the oxidation temperature is 1250°C-1350°C, and the oxidation time is 10-30min. The phosphorus ion shallow implantation layer is completely consumed, and then annealed in NO. The duration is 1 hour, and the annealing temperature is 1150°C to 1350°C, as shown in Figure 10;

S10, by dry etching, the _SiO2 oxide layer generated by thermal oxidation is etched, only the _SiO2 oxide layer on the JFET region, the rear trench and part of the N+ source region 6 is kept, and the second layer of gate oxide layer 8 is formed. As shown in Figure 11;

S11, perform dry etching on the _SiO2 layer, etch away part of the _SiO2 layer above the channel, the etching thickness is 40-60nm, the etching width is slightly larger than the channel length, and the first layer of gate oxide layer 9 is formed, as As shown in Figure 12;

S12 , forming a gate 10 on the first gate oxide layer 9 by metal sputtering, as shown in FIG. 13 .

S13. On the P+ contact region 5 and part of the N+ source region 6 away from the JFET region, form a source electrode 11 by metal sputtering, and form an ohmic contact through high-temperature rapid thermal annealing, as shown in FIG. 14 ;

S14. On the back surface of the N-type SiC substrate 2, a drain 1 is formed by metal sputtering, and an ohmic contact is formed through laser annealing, as shown in FIG. 1 .

There are two gate oxide layers in the present invention, the gate oxide layer generated by thermal oxidation is thinner, and the gate oxide layer deposited by PECVD is thicker; during the pretreatment of phosphorus ion shallow implantation, add SiO ₂ cushion layer, this cushion layer can help reduce The ion implantation damages the surface of the N-type epitaxial layer, and contributes to the shallow depth of the phosphorus ion implantation layer on the upper part of the N-type epitaxial layer; after the pretreatment of phosphorus ion shallow implantation, thermal oxidation is performed, and the shallow phosphorus ion implantation layer If it is completely consumed, part of the implanted P element will remain in the generated thin gate oxide layer, thereby playing the role of phosphorus passivation. This way makes it easier for phosphorus to combine with carbon, silicon and oxygen to form a stable compound, reducing the interface state. In addition, the generated oxide layer is thinner, thereby reducing the defects of the gate oxide layer; thermal oxidation prepares a thinner oxide layer, and PECVD deposits a thicker oxide layer on the thin oxide layer. The combination of the two methods can efficiently prepare the target thickness of gate oxide. In addition, because of the existence of the SiO ₂ cushion layer, the depth of ion implantation into the epitaxial layer is reduced, and the purpose of shallow implantation is realized.

In another embodiment of the present invention, in order to improve the thermal electron degradation effect, after step S3 and before step S4, sub-implantation is performed on both sides of the channel between the N+ source region 6 and the JEFT region to form light N-type region 7 is doped, as shown in FIG. 7 .

The present invention has been exemplarily described, and obviously the specific implementation of the present invention is not limited by the above-mentioned manner, as long as various non-substantial improvements are carried out by adopting the method concept and technical scheme of the present invention, or unimproving the present invention Ideas and technical solutions that are directly applied to other occasions are within the protection scope of the present invention.

Claims (9)

1. A structure of a SiC VDMOSFET power device, the structure comprising:

an N-type SiC substrate (2), a drain electrode (1) and an N-type epitaxial layer (3) which are positioned on the back and the front of the N-type SiC substrate (2);

two P well regions (4) are formed by injection at two sides of the N-type epitaxial layer (3), a P+ contact region (5) and an N+ source region (6) are sequentially formed in each P well region (4), the P+ contact region (5) is far away from the JFET region, and the N+ source region (6) is adjacent to the P+ contact region (5) and is close to the JFET region;

the first layer of gate oxide layer (9) is arranged on the N-type epitaxial layer, is arranged above the JFET region, the channel and part of the N+ source region (6), the first layer of gate oxide layer (9) above the channel is concave downwards, the gate (10) is formed on the first layer of gate oxide layer, and the source is formed on the P+ contact region (5) and part of the N+ source region (6).

2. The structure of a SiC VDMOSFET power device of claim 1, wherein said SiC VDMOSFET power device further comprises:

the second layer of gate oxide (8) is positioned between the first layer of gate oxide (9) and the N-type epitaxial layer (3) and is positioned above the JFET region, the channel and part of the N+ source region (6).

3. A structure of a SiC VDMOSFET power device as claimed in claim 2, characterized in that the N-type epitaxial layer (3) in which the shallow implantation of phosphorus ions is present is thermally oxidized to form a second gate oxide layer (8).

4. A structure of a SiC VDMOSFET power device as claimed in claim 1, characterized in that two lightly doped N-type regions (7) are formed in the P-well region (4), arranged adjacent to the JFET region, the n+ source region (6), respectively.

5. A method for manufacturing a SiC VDMOSFET power device, the method comprising the steps of:

s1, epitaxially growing an N-type epitaxial layer (3) on the front surface of the N-type SiC substrate (2);

s2, forming two P well regions (4) on two sides of the front surface of the N-type epitaxial layer (3) through ion implantation;

s3, performing ion implantation at a position, far away from the JEFT region, of the P well region (4) to form a P+ contact region (5), and performing ion implantation at a position, close to the JFET region, of the P well region (4) and close to the P+ contact region (5) to form an N+ source region (6);

s4, forming a phosphorus ion shallow injection layer on the top of the N-type epitaxial layer (3), and activating injection ions;

s5, depositing SiO on the JFET region, the channel and part of the N+ source region (6) ₂ A layer formed of SiO by thermal oxidation ₂ Oxidizing the layer, consuming the phosphorus ion shallow injection layer, and annealing in NO;

s6, to SiO ₂ Etching the oxide layer to form a second gate oxide layer (8) of SiO ₂ Dry etching is carried out on the layer to form a first layer of grid oxide layer (9) with a thick thickness above the JFET region and a thin thickness above the channel;

s7, forming a grid electrode (10) on the first layer of grid electrode oxide layer (9), forming a source electrode (11) on the P+ contact region (5) and a part of N+ source region (6) far away from the JFET region, and forming a back drain electrode (1) of the N-type SiC substrate (2).

6. The method for manufacturing a SiC VDMOSFET power device according to claim 5, wherein the forming process of the shallow phosphorus ion implantation layer on top of the N-type epitaxial layer (3) is as follows:

deposition of SiO on the N-type epitaxial layer ₂ The cushion layer is then subjected to phosphorus ion implantation, and after the implantation is finished, all SiO is removed ₂ And a cushion layer, wherein a phosphorus ion shallow injection layer is formed on the top of the N-type epitaxial layer (3).

7. The method of manufacturing a SiC VDMOSFET power device of claim 6 wherein the second gate oxide layer has a thickness of 20-30 nm and the first gate oxide layer has a thickness of 60-80 nm.

8. The method of manufacturing a SiC VDMOSFET power device of claim 7, wherein SiO ₂ The etching thickness of the layer is 40-60 nm, and the etching width is slightly larger than the trench width, so that a first layer of gate oxide layer is formed.

9. The method of manufacturing a SiC VDMOSFET power device of claim 5, further comprising, after step S3, before step S4:

and carrying out sub-implantation on two sides of a channel between the N+ source region (6) and the JEFT region to form a lightly doped N-type region (7).

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