CN118335778A - Diamond SGT device and preparation method thereof - Google Patents
Diamond SGT device and preparation method thereof Download PDFInfo
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- CN118335778A CN118335778A CN202410741904.3A CN202410741904A CN118335778A CN 118335778 A CN118335778 A CN 118335778A CN 202410741904 A CN202410741904 A CN 202410741904A CN 118335778 A CN118335778 A CN 118335778A
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- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 47
- 239000010432 diamond Substances 0.000 title claims abstract description 47
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 81
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 46
- 230000004888 barrier function Effects 0.000 claims description 45
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- 238000002407 reforming Methods 0.000 claims description 21
- 239000013077 target material Substances 0.000 claims description 19
- 229910052786 argon Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 16
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 15
- 239000012300 argon atmosphere Substances 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000000407 epitaxy Methods 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 11
- 239000001257 hydrogen Substances 0.000 claims description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims description 11
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000003054 catalyst Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000012071 phase Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 4
- 239000012808 vapor phase Substances 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000000927 vapour-phase epitaxy Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a diamond SGT device and a preparation method thereof, and relates to the technical field of semiconductors, and the diamond SGT device comprises drain metal, wherein an n-type substrate, an n-type drift layer and a grid medium are arranged above the drain metal, a shielding grid is arranged below the inside of the grid medium, and grid metal is arranged above the inside of the grid medium; an n+ current equalizing layer is further arranged above the n-type drift layer, a p+ well region is arranged above the n+ current equalizing layer, an n+ source region is arranged above the p+ well region, and source metal is arranged above the n+ source region. By arranging the optimized layout between the deeper p+ well region and the gate metal, the breakdown of a gate dielectric is effectively prevented, and the reliability of the gate is improved; in addition, by increasing the doping concentration of the p+ well region and the design of the n+ current sharing layer, the preparation flow is reduced, the distribution and flow of electrons are optimized, the gate charge and the on-resistance are reduced, and the overall performance and the efficiency of the device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a diamond SGT device and a preparation method thereof.
Background
Diamond is one of the representative ultra-wide band gap semiconductor devices, the band gap is about 5.5eV, the critical breakdown field strength is as high as 10MV/cm, the electron saturation speed is 3 x 10 7 cm/s, but the thick epitaxy and deep etching processes are still immature due to the problems in the process development stage, and the device structure development has room.
In order to solve the above problems, we propose a new SGT device structure, which realizes the advantages of simple device structure process and low loss, and realizes the preparation of the SGT structure by adopting a combination of distributed epitaxy and ion implantation.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a diamond SGT device and a preparation method thereof, which are used for solving the problems in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions: a diamond SGT device comprises drain metal, wherein the drain metal is positioned at the bottommost end of the device, an n-type substrate is arranged above the drain metal, an n-type drift layer is arranged above the n-type substrate, a gate dielectric is arranged above the n-type drift layer, a shielding gate is arranged below the inside of the gate dielectric, and a gate metal is arranged above the inside of the gate dielectric;
an n+ current equalizing layer is further arranged above the n-type drift layer, a p+ well region is arranged above the n+ current equalizing layer, an n+ source region is arranged above the p+ well region, a source metal is arranged above the n+ source region, and the source metal is further located above the p+ well region.
According to the technical scheme, the thickness of the n-type substrate is 1 mu m, the doping concentration of the n-type substrate is 5 multiplied by 10 18cm-3, the thickness of the n-type drift layer is 5-8 mu m, the doping concentration of the n-type drift layer is 1 multiplied by 10 17cm-3~5×1017cm-3, and the gate dielectric is silicon dioxide.
Further optimizing the technical scheme, the thickness from the bottom of the shielding grid to the bottom of the grid medium is 500nm, the distance from the rightmost side of the shielding grid to the rightmost side of the grid medium is 200-300nm, the distance from the leftmost side of the shielding grid to the leftmost side of the grid medium is 200-300nm, and the thickness of the shielding grid is 300nm.
According to the technical scheme, the thickness of the n+ current equalizing layer is 300nm, the doping concentration of the n+ current equalizing layer is 5×10 18cm-3, the thickness from the bottom to the top of the p+ well region is 600nm, the thickness from the bottom of the p+ well region to the bottom of the n+ source region is 300nm, the doping concentration of the p+ well region is1×10 18cm-3~5×1018cm-3, the thickness of the n+ source region is 300nm, the thickness of the gate metal is 200nm, the thickness from the top of the shielding gate to the bottom of the gate metal is 300nm, and the thickness of the gate metal is 500nm.
The technical scheme is further optimized, and the bottom depth of the p+ well region is lower than 100nm of the gate metal, so that the gate dielectric breakdown possibly caused by the gate dielectric electric field concentration between the gate metal and the shielding gate and at the outer side of the shielding gate when the gate is electrified is protected.
The preparation method of the diamond SGT device is based on the diamond SGT device and comprises the following specific steps:
S1, epitaxially growing an n-type drift layer on an n-type diamond substrate with drain metal;
S2, depositing a barrier layer on the n-type drift layer, etching a gate dielectric through hole, etching the n-type drift layer along the through hole, and etching a shielding gate and a part of the region corresponding to the gate dielectric;
S3, depositing a layer of silicon dioxide on the etched shielding gate and the partial area corresponding to the gate dielectric;
s4, removing the barrier layer in the step S2, reforming a new barrier layer, etching a through hole of a shielding grid region, depositing shielding grid metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing manner;
s5, removing the barrier layer in the step S4, reforming a new barrier layer, etching an n+ current sharing layer area, and epitaxially growing an n+ current sharing layer;
S6, removing the barrier layer in the step S5, reforming a new barrier layer, etching the p+ well region, and epitaxially growing a layer of p+ well region;
s7, removing the barrier layer in the step S6, reforming a new barrier layer, etching the gate through hole, etching the diamond gate area, and depositing a gate dielectric;
S8, removing the barrier layer in the step S7, reforming a new barrier layer, etching a gate metal through hole, depositing gate metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing manner;
s9, removing the barrier layer in the step S8, reforming a new barrier layer, etching the n+ source region through hole, and forming an n+ source region in an ion implantation mode;
s10, removing the barrier layer in the step S9, reforming a new barrier layer, etching a source metal through hole, depositing gate metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing mode.
Further optimizing the technical scheme, in the steps S1, S5 and S6, during epitaxial growth, the epitaxial technology adopts chemical vapor phase epitaxy, and methane in the epitaxy: the hydrogen volume ratio is 1:4, and the growth temperature is 1000 ℃.
Further optimizing the technical scheme, in the step S2, the etching is performed by adopting a gas phase etching method, and under the gas environment with the volume ratio of oxygen to hydrogen of 1:1 and the high temperature condition of 1200 ℃, nickel is adopted as a catalyst.
In the step S3, silicon dioxide is sputtered in a magnetron sputtering mode, and argon generates glow discharge in an argon environment under the condition of 3000V high voltage to strike a silicon dioxide target material, so that the silicon dioxide target material is sputtered and deposited on the upper surface of the device.
Further optimizing the technical scheme, in the step S7, etching is performed by adopting a diamond gas phase etching method, and under the gas environment with the volume ratio of oxygen to hydrogen of 1:1 and the high temperature condition of 1200 ℃, nickel is adopted as a catalyst;
The silicon dioxide adopts a magnetron sputtering mode, argon generates glow discharge under the condition of 3000V high voltage in an argon atmosphere, and the silicon dioxide target is impacted to cause the silicon dioxide target to be splashed and deposited on the upper surface of the device.
Compared with the prior art, the invention provides a diamond SGT device and a preparation method thereof, and the diamond SGT device has the following beneficial effects:
According to the diamond SGT device and the preparation method thereof, by arranging the optimized layout between the deeper p+ well region and the grid metal, the breakdown of a grid dielectric is effectively prevented, and the reliability of the grid is improved; in addition, by increasing the doping concentration of the p+ well region and the design of the n+ current sharing layer, the preparation flow is reduced, the distribution and flow of electrons are optimized, and the gate charge and the on-resistance are reduced, so that the overall performance and the efficiency of the device are improved; the shielding grid of the device enhances the concentration and distribution of internal electrons through the charge effect, further reduces the conduction loss, reduces the capacitance effect of the grid electrode to the drain electrode, and reduces the switching loss.
Drawings
FIG. 1 is a schematic cross-sectional view of a diamond SGT device according to the present invention;
FIG. 2 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S1;
FIG. 3 is a schematic cross-sectional view of a diamond SGT device according to step S2 of the method of the present invention;
FIG. 4 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S3;
FIG. 5 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S4;
FIG. 6 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S5;
FIG. 7 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S6;
FIG. 8 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S7;
FIG. 9 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S8;
FIG. 10 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S9;
FIG. 11 is a schematic cross-sectional view of a diamond SGT device according to the present invention at step S10.
In the figure: 1. a drain metal; 2. an n-type substrate; 3. an n-type drift layer; 4. a gate dielectric; 5. a shield grid; 6. a gate metal; 7. n+ uniform flow layer; 8. a p+ well region; 9. an n+ source region; 10. source metal.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
Referring to fig. 1, a diamond SGT device includes a drain metal 1, the drain metal 1 is located at the bottommost end of the device, an n-type substrate 2 is disposed above the drain metal 1, an n-type drift layer 3 is disposed above the n-type substrate 2, a gate dielectric 4 is disposed above the n-type drift layer 3, a shielding gate 5 is disposed below the inside of the gate dielectric 4, and a gate metal 6 is disposed above the inside of the gate dielectric 4. An n+ current equalizing layer 7 is further arranged above the n-type drift layer 3, a p+ well region 8 is arranged above the n+ current equalizing layer 7, an n+ source region 9 is arranged above the p+ well region 8, a source metal 10 is arranged above the n+ source region 9, and the source metal 10 is further arranged above the p+ well region 8.
The device adopts diamond material, overcomes the defect that the traditional Si SGT device can only work in a medium-voltage section (about 200V), and can fully exert the advantages of low on-resistance and low switching loss in a high-voltage section (600-800V).
The thickness of the n-type substrate 2 is 1 μm, the doping concentration of the n-type substrate 2 is 5×10 18cm-3, the thickness of the n-type drift layer 3 is 5-8 μm, the doping concentration of the n-type drift layer 3 is 1×10 17cm-3~5×1017cm-3, and the gate dielectric 4 is silicon dioxide. The thickness from the bottom of the shielding grid 5 to the bottom of the grid dielectric 4 is 500nm, the distance from the rightmost side of the shielding grid 5 to the rightmost side of the grid dielectric 4 is 200-300nm, the distance from the leftmost side of the shielding grid 5 to the leftmost side of the grid dielectric 4 is 200-300nm, and the thickness of the shielding grid 5 is 300nm. The thickness of the n+ current equalizing layer 7 is 300nm, the doping concentration of the n+ current equalizing layer 7 is 5×10 18cm-3, the thickness from the bottom to the top of the p+ well region 8 is 600nm, the thickness from the bottom of the p+ well region 8 to the bottom of the n+ source region 9 is 300nm, the doping concentration of the p+ well region 8 is 1×10 18cm-3~5×1018cm-3, the thickness of the n+ source region 9 is 300nm, the thickness of the gate metal 6 is 200nm, the thickness from the top of the shielding gate 5 to the bottom of the gate metal 6 is 300nm, and the thickness of the gate metal 6 is 500nm.
The conventional device structure has a p+ source region at a position parallel to the n+ source region 9 to realize ohmic contact between the source metal 10 and the p+ source region, the p+ source region and the low doped p+ well region naturally form ohmic contact, and the low doped p+ well region and the n+ current sharing layer 7 or the n-type drift layer 3 of the conventional device form a pn junction to generate a body diode structure. The device improves the doping concentration of the p+ well region 8, the p+ well region 8 and the source metal 10 directly form ohmic contact, and the p+ well region 8 and the n+ uniform current layer 7 or the n-type drift layer 3 form a pn junction to generate a body diode structure.
Therefore, the doping concentration of the p+ well region 8 is higher than that of the conventional device well region, and the parasitic body diode of the device is formed, so that the body diode freewheel when the device is not conducted is completed, and the additional p+ source region process preparation flow is reduced.
The bottom depth of the p+ well region 8 is lower than that of the gate metal 6100nm, so that the gate dielectric 4 possibly caused by electric field concentration between the gate metal 6 and the gate dielectric 4 outside the middle of the shielding gate 5 when the gate is electrified can be effectively protected, the gate reliability problem occurs, and the gate reliability is improved.
Meanwhile, the doping concentration of the p+ well region 8 of the device is independently increased, so that the device can be fully conducted only when larger gate charge is generated, an n+ current sharing layer 7 is constructed below the p+ well region 8, a pn junction formed by the n+ current sharing layer 7 and the p+ well region 8 diffuses to the upper part of the p+ well region 8, the gate inversion region of the device is reduced, the gate charge of the device is reduced, and the problem caused by the increase of the doping concentration of the p+ well region 8 is counteracted.
In this embodiment, the n+ current equalizing layer 7 can reduce the gate charge of the device, and can equalize electrons from the n+ source region 9, so that the electrons are diffused from the gate dielectric 4 to the left and right sides of the device, current concentration in the device is inhibited, and on-resistance of the device is reduced.
In this embodiment, the shielding gate 5 of the device can form an inversion layer on the left, right and lower sides of the shielding gate 5 and the gate dielectric 4 in the device through the charge effect, so as to improve the electron concentration of the n-type drift layer 3, reduce the on-resistance of the device, and reduce the on-loss of the device. The shielding grid 5 of the device can also shield the capacitance effect of the grid electrode of the device on the drain electrode, reduce the Miller capacitance, reduce the grid charge of the device and reduce the switching loss of the device.
Embodiment two:
the diamond SGT device according to example one was prepared by the following steps:
s1, as shown in FIG. 2, epitaxially growing an n-type drift layer 3 on an n-type diamond substrate with drain metal 1; the epitaxy technology adopts chemical vapor phase epitaxy, and methane in the epitaxy: the hydrogen volume ratio is 1:4, and the growth temperature is 1000 ℃.
S2, as shown in FIG. 3, a barrier layer is deposited on the n-type drift layer 3, a through hole of the grid dielectric 4 is etched, the n-type drift layer 3 is etched along the through hole, and the shielding grid 5 and a partial area corresponding to the grid dielectric 4 are etched; the etching adopts a gas phase etching method, and under the gas atmosphere of which the volume ratio of oxygen to hydrogen is 1:1 and the high temperature condition of 1200 ℃, nickel is adopted as a catalyst for etching.
S3, as shown in FIG. 4, a layer of silicon dioxide is deposited on the etched shielding gate 5 and the partial area corresponding to the gate dielectric 4, the silicon dioxide adopts a magnetron sputtering mode, argon generates glow discharge under the condition of high voltage of 3000V in an argon atmosphere, and the silicon dioxide target is impacted to enable the silicon dioxide to be deposited on the upper surface of the device in a splashing way.
S4, as shown in FIG. 5, removing the barrier layer in the step S2, reforming a new barrier layer, etching the through hole in the area of the shielding grid 5, depositing shielding grid 5 metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of high voltage of 3000V in argon atmosphere, and striking a metal target material to enable the metal target material to be splashed and deposited on the upper surface of the device;
S5, as shown in FIG. 6, removing the barrier layer in the step S4, reforming a new barrier layer, etching the area of the n+ current sharing layer 7, and epitaxially growing a layer of n+ current sharing layer 7; the epitaxy technology adopts chemical vapor phase epitaxy, the volume ratio of methane to hydrogen in the epitaxy is 1:4, and the growth temperature is 1000 ℃.
S6, as shown in FIG. 7, removing the barrier layer in the step S5, reforming a new barrier layer, etching the region of the p+ well region 8, and epitaxially growing a layer of p+ well region 8; the epitaxy technology adopts chemical vapor phase epitaxy, the volume ratio of methane to hydrogen in the epitaxy is 1:4, and the growth temperature is 1000 ℃.
S7, as shown in FIG. 8, removing the barrier layer in the step S6, reforming a new barrier layer, etching a gate through hole, etching a diamond gate region, and depositing a gate dielectric 4; the etching adopts a diamond gas phase etching method, and under the gas atmosphere of which the volume ratio of oxygen to hydrogen is 1:1 and the high temperature condition of 1200 ℃, nickel is adopted as a catalyst for etching. The silicon dioxide adopts a magnetron sputtering mode, argon generates glow discharge under the condition of 3000V high voltage in an argon atmosphere, and the silicon dioxide target is impacted to cause the silicon dioxide target to be splashed and deposited on the upper surface of the device.
S8, as shown in FIG. 9, removing the barrier layer in the step S7, reforming a new barrier layer, etching a through hole of the grid metal 6, depositing the grid metal 6 in a magnetron sputtering mode, generating glow discharge by argon under the high voltage condition of 3000V in an argon atmosphere, and striking a metal target to enable the metal target to be splashed and deposited on the upper surface of the device;
S9, as shown in FIG. 10, removing the barrier layer in the step S8, reforming a new barrier layer, etching the through hole of the n+ source region 9, and forming the n+ source region 9 by adopting an ion implantation mode;
S10, as shown in FIG. 11, removing the barrier layer in the step S9, reforming a new barrier layer, etching a through hole of the source metal 10, depositing the gate metal 6 by adopting a magnetron sputtering mode, generating glow discharge by argon under the condition of high voltage of 3000V in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing manner.
The beneficial effects of the invention are as follows:
According to the diamond SGT device and the preparation method thereof, by arranging the optimized layout between the deeper p+ well region and the grid metal, the breakdown of a grid dielectric is effectively prevented, and the reliability of the grid is improved; in addition, by increasing the doping concentration of the p+ well region and the design of the n+ current sharing layer, the preparation flow is reduced, the distribution and flow of electrons are optimized, and the gate charge and the on-resistance are reduced, so that the overall performance and the efficiency of the device are improved; the shielding grid of the device enhances the concentration and distribution of internal electrons through the charge effect, further reduces the conduction loss, reduces the capacitance effect of the grid electrode to the drain electrode, and reduces the switching loss.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. The diamond SGT device is characterized by comprising drain metal, wherein the drain metal is positioned at the bottommost end of the device, an n-type substrate is arranged above the drain metal, an n-type drift layer is arranged above the n-type substrate, a gate dielectric is arranged above the n-type drift layer, a shielding gate is arranged below the inside of the gate dielectric, and a gate metal is arranged above the inside of the gate dielectric;
An n+ current equalizing layer is further arranged above the n-type drift layer, a p+ well region is arranged above the n+ current equalizing layer, the thickness of the n+ current equalizing layer is 300nm, the doping concentration of the n+ current equalizing layer is 5×10 18cm-3, the thickness from the bottom to the top of the p+ well region is 600nm, the thickness from the bottom to the bottom of the n+ source region is 300nm, and the doping concentration of the p+ well region is 1×10 18cm-3~5×1018cm-3;
An n+ source region is arranged above the p+ well region, a source metal is arranged above the n+ source region, and the source metal is also arranged above the p+ well region.
2. The diamond SGT device of claim 1, wherein the n-type substrate has a thickness of 1 μm, the n-type substrate has a doping concentration of 5 x 10 18cm-3, the n-type drift layer has a thickness of 5-8 μm, the n-type drift layer has a doping concentration of 1 x 10 17cm-3~5×1017cm-3, and the gate dielectric is silicon dioxide.
3. The diamond SGT device of claim 1, wherein the thickness of the bottom of the shield grating to the bottom of the gate dielectric is 500nm, the distance from the rightmost side of the shield grating to the rightmost side of the gate dielectric is 200-300nm, the distance from the leftmost side of the shield grating to the leftmost side of the gate dielectric is 200-300nm, and the thickness of the shield grating is 300nm.
4. The diamond SGT device of claim 1, wherein the n+ source region has a thickness of 300nm, the gate metal has a thickness of 200nm, the top of the shield gate has a thickness of 300nm to the bottom of the gate metal, and the gate metal has a thickness of 500nm.
5. The diamond SGT device of claim 1, wherein the bottom depth of the p+ well region is 100nm below the gate metal for protecting the gate dielectric breakdown caused by the concentration of the gate dielectric electric field between and outside the gate metal and the shield gate that occurs when the gate is energized.
6. A method of making a diamond SGT device, based on the diamond SGT device of any one of claims 1 to 5, comprising the specific steps of:
S1, epitaxially growing an n-type drift layer on an n-type diamond substrate with drain metal;
S2, depositing a barrier layer on the n-type drift layer, etching a gate dielectric through hole, etching the n-type drift layer along the through hole, and etching a shielding gate and a part of the region corresponding to the gate dielectric;
S3, depositing a layer of silicon dioxide on the etched shielding gate and the partial area corresponding to the gate dielectric;
s4, removing the barrier layer in the step S2, reforming a new barrier layer, etching a through hole of a shielding grid region, depositing shielding grid metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing manner;
s5, removing the barrier layer in the step S4, reforming a new barrier layer, etching an n+ current sharing layer area, and epitaxially growing an n+ current sharing layer;
S6, removing the barrier layer in the step S5, reforming a new barrier layer, etching the p+ well region, and epitaxially growing a layer of p+ well region;
s7, removing the barrier layer in the step S6, reforming a new barrier layer, etching the gate through hole, etching the diamond gate area, and depositing a gate dielectric;
S8, removing the barrier layer in the step S7, reforming a new barrier layer, etching a gate metal through hole, depositing gate metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing manner;
s9, removing the barrier layer in the step S8, reforming a new barrier layer, etching the n+ source region through hole, and forming an n+ source region in an ion implantation mode;
s10, removing the barrier layer in the step S9, reforming a new barrier layer, etching a source metal through hole, depositing gate metal in a magnetron sputtering mode, generating glow discharge by argon under the condition of 3000V high voltage in an argon atmosphere, and striking a metal target material to enable the metal target material to be deposited on the upper surface of the device in a splashing mode.
7. The method for manufacturing a diamond SGT device according to claim 6, wherein in steps S1, S5 and S6, during epitaxial growth, chemical vapor epitaxy is used as an epitaxy technique, and methane in the epitaxy: the hydrogen volume ratio is 1:4, and the growth temperature is 1000 ℃.
8. The method according to claim 6, wherein in the step S2, the etching is performed by using a gas phase etching method, and using nickel as a catalyst in a gas atmosphere having a volume ratio of oxygen to hydrogen of 1:1 and a high temperature of 1200 ℃.
9. The method for manufacturing a diamond SGT device according to claim 6, wherein in the step S3, silicon dioxide is sputtered on the upper surface of the device by means of magnetron sputtering, and argon is subjected to glow discharge in an argon atmosphere under a high voltage condition of 3000V to strike a silicon dioxide target material.
10. The method for manufacturing a diamond SGT device according to claim 6, wherein in the step S7, a diamond vapor phase etching method is adopted for etching, and nickel is adopted as a catalyst for etching under a gas environment with a volume ratio of oxygen to hydrogen of 1:1 and a high temperature of 1200 ℃;
The silicon dioxide adopts a magnetron sputtering mode, argon generates glow discharge under the condition of 3000V high voltage in an argon atmosphere, and the silicon dioxide target is impacted to cause the silicon dioxide target to be splashed and deposited on the upper surface of the device.
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