CN115987063A

CN115987063A - Mixed-mode power factor corrector and operation method thereof

Info

Publication number: CN115987063A
Application number: CN202211477769.3A
Authority: CN
Inventors: 洪宗良; 邱绍贤
Original assignee: Yarongyuan Technology Shenzhen Co ltd; Yaruiyuan Technology Shenzhen Co ltd
Current assignee: Yarongyuan Technology Shenzhen Co ltd; Yaruiyuan Technology Shenzhen Co ltd
Priority date: 2022-11-23
Filing date: 2022-11-23
Publication date: 2023-04-18

Abstract

A mixed mode power factor corrector and an operation method thereof are provided. The power factor correction circuit includes a power inductor and a power switch, and the zero-crossing detection circuit detects a resonance phenomenon generated by a switching voltage across the power switch when the inductor current decreases to zero. The controller controls the power factor correction circuit to convert the input voltage to the output voltage by switching the zero-crossing detection circuit and the operation frequency control power switch, and controls the input current extracted by the power factor correction circuit to follow the input voltage. The controller controls the power switch to be turned on when the resonance generated by the switch voltage approaches the threshold of the zero-crossing detection circuit and the switching time of the power switch reaches the operating frequency based on the condition that the inductive current is reduced to zero.

Description

Mixed-mode power factor corrector and operation method thereof

Technical Field

The present invention relates to a power factor corrector and a method for operating the same, and more particularly, to a hybrid mode power factor corrector and a method for operating the same.

Background

PFC, power Factor Correction, refers to Power Factor Correction, which aims to increase the ratio of apparent Power to actual Power, i.e., the ratio of active Power divided by total Power consumption (apparent Power). The power factor can measure the effective utilization degree of the power, and when the power factor value is larger, the power utilization rate is higher. The regulations for utility power are different in each country, but basically, PFC is required when the input power of the power supply exceeds 75W.

The conventional active power factor corrector is generally implemented and applied by a Boost (Boost) converter, and can be roughly divided into a Discontinuous Conduction Mode (DCM), a Boundary Conduction Mode (BCM) and a Continuous Conduction Mode (CCM) according to the operation of an inductor current. As shown in fig. 1, in the critical conduction mode (BCM), the peak value of the inductor current Il is larger than that in the continuous conduction mode, so that the power device suffers from the disadvantages of higher current stress and conduction loss. However, the critical conduction mode has no problem of diode reverse recovery time, and the switching voltage at the two terminals of the main power switch can be switched at a lower voltage (low valley), so that there is an advantage of smaller switching loss. However, when the inductor current is small, the operation in the critical conduction mode is accompanied by a high switching frequency, which causes additional switching loss, and thus leads to a decrease in efficiency.

Therefore, how to design a mixed mode power factor corrector and a mixed mode operation method thereof, so that a single power factor corrector can operate in a continuous conduction mode, a critical conduction mode and a discontinuous conduction mode, and the problem of overhigh switching frequency of a switch when the inductive current is small is solved, which is a major subject to be researched by the authors of the present application.

Disclosure of Invention

In order to solve the above problems, the present invention provides a mixed mode power factor corrector to overcome the problems of the prior art. Therefore, the mixed-mode power factor corrector of the present invention includes a power factor correction circuit, a zero-crossing detection circuit and a controller. The power factor correction circuit receives an input voltage and comprises a power inductor and a power switch. The zero-crossing detection circuit is coupled to the power inductor to detect resonance of the switching voltage at two ends of the power switch. The controller is coupled to the power switch and the zero-crossing detection circuit, controls the power factor correction circuit to convert the input voltage to the output voltage by controlling the switching of the power switch through the operating frequency, and controls the input current drawn by the power factor correction circuit to follow the input voltage. Wherein, the controller is based on that the inductive current is reduced to zero, the resonance generated by the switch voltage is close to the threshold value of the zero-crossing detection circuit, and the switching time point of the power switch reaches the operation frequency.

The mixed mode operation method of the power factor corrector comprises the following steps: (a) The power factor correction circuit is controlled to convert the input voltage into the output voltage by switching a power switch of the operating frequency control power factor correction circuit, and the input current drawn by the power factor correction circuit is controlled to follow the input voltage. (b) Resonance of a switching voltage across a power switch of a power factor correction circuit is detected. (c) Based on the fact that the inductive current is reduced to zero, the resonance generated by the switching voltage is close to the threshold value of the zero-crossing detection circuit, and the switching time point of the power switch reaches the operating frequency, the power switch is controlled to be conducted.

The mixed-mode power factor corrector has the advantages that the mixed-mode power factor corrector can operate the power factor correction circuit in a continuous conduction mode, a critical conduction mode and a discontinuous conduction mode based on the magnitude of the inductive current, and limits the switching frequency of the power switch to be approximately equal to a fixed frequency, so that the switching loss is reduced due to the fact that the switching frequency of the power switch is prevented from rising, and the efficiency of the power factor corrector is improved.

Drawings

FIG. 1 is a waveform diagram illustrating a critical conduction mode of the prior art;

FIG. 2 is a block diagram of a mixed mode PFC according to the present invention;

FIG. 3 is a waveform diagram of the mixed-mode PFC according to the present invention;

FIG. 4 is a block diagram of the internal circuitry of the controller of the present invention;

FIG. 5 is a flowchart of a method of mixed-mode operation of the PFC according to the present invention.

100 power factor corrector, 1 power factor correction circuit, L power inductor, Q power switch, 2 zero crossing detection circuit, 3 controller, MULT multiplier, 32 comparison module, 34 trigger module, RS1 first trigger, OR1 first OR module, RS2 second trigger, AND module, OR2 second OR module, RS3 third trigger, 200 load, vin input voltage, vo output voltage, vdc direct current voltage, vds switch voltage, vref1, vref2 reference voltage, il inductor current, iin input current, sv voltage signal, sc control signal, vo _ fb, vin _ fb/Vin _ rms feedback signal, iref half-string wave signal, ipfc error signal, RAMP triangle wave signal, szcd comparison signal, sp pulse signal, S1, S2, S3 output signal, slg logic signal, sck signal, clock pulse continuous conduction mode, BCM critical conduction mode, DCM conduction mode, swP zero crossing point, swp zero crossing point, operation frequency, zcd operation frequency, zt operation frequency, S1, S2, S3 output signal, S0, AND S400 to S0 (step).

Detailed Description

The technical content and the detailed description of the invention are described as follows with the accompanying drawings:

referring to fig. 2, the hybrid mode pfc 100 receives an ac input voltage Vin, and converts the ac input voltage Vin into a dc output voltage Vo to provide the output voltage Vo to power the load 200. The power factor corrector 100 includes a power factor correction circuit 1, a zero-crossing detection circuit 2 and a controller 3, and the power factor correction circuit 1 may be a step-up or step-down converter circuit, or may be an isolated or non-isolated converter circuit. Taking the boost converter circuit as an example, the power factor correction circuit 1 includes a power inductor L and a power switch Q. The power factor correction circuit 100 receives an input voltage Vin, rectifies the input voltage Vin into a dc voltage Vdc through a bridge rectifier circuit, and switches the power switch Q to store/release energy in the power inductor L to generate an inductor current Il, so as to convert the dc voltage Vdc into an output voltage Vo.

The zero-crossing detection circuit 2 is coupled to the power inductor L to detect the resonance of the switching voltage Vds across the power switch Q. The zero-crossing detection circuit 2 may be a winding-coupled, current-transformer-induced or resistance-induced zero-crossing detection circuit. Taking the winding coupling type as an example, the zero-crossing detection circuit 2 is a winding coupled with the power inductor L to detect the resonance of the switching voltage Vds to generate the corresponding voltage signal Sv. The controller 3 is coupled to the power switch Q and the zero-crossing detection circuit 2, and controls the switching of the power switch Q by a control signal Sc having an operating frequency to control the power factor correction circuit 1 to convert the input voltage Vin into the output voltage Vo. The characteristic of the pfc 100 is that the controller 3 controls the switching timing of the power switch Q to control the waveform of the input current Iin drawn by the pfc circuit 1 to follow the input voltage Vin, so as to improve the power factor of the input terminal of the pfc 100 (usually to be improved to 0.9 or more). Wherein the operating frequency may be substantially a fixed frequency (e.g., without limitation, substantially 65 KHz).

Referring to fig. 2 and 3 together, the main object and feature of the present invention is that the controller 3 can operate the pfc circuit 1 in the continuous conduction mode CCM, the critical conduction mode BCM and the discontinuous conduction mode DCM based on the magnitude of the inductor current Il. When the inductive current Il is larger, the peak value of the inductive current Il can be smaller to reduce the current stress and Conduction loss (connection loss) of the power devices such as the power switch Q, etc. in CCM mode, so as to increase the efficiency of full load. When the inductor current Il is small, the power factor corrector can operate in the BCM or DCM mode, and limit the Switching frequency of the power switch Q to be substantially equal to the fixed frequency, so as to avoid the Switching loss (Switching loss) caused by the rising Switching frequency of the power switch Q, thereby improving the efficiency of the power factor corrector (when the inductor current Il is close to the zero crossing point P) under light load. The main reason is that the inductive current Il tends to rapidly touch the input voltage Vin sine wave and the zero crossing point P (because the voltage difference between the two is too low) as the inductive current Il approaches the zero crossing point P of the input voltage Vin, and the switching frequency of the power switch Q tends to be faster as the inductive current Il approaches the zero crossing point P without limiting the operating frequency Fsw.

Therefore, the controller 3 of the present invention determines that the switching frequency of the power switch Q reaches the operating frequency when the switching time is up, and controls the power switch Q to be turned on when the inductor current Il is as low as zero and the zero-crossing detection is close to the threshold (such as but not limited to 0 a), so as to limit the switching frequency of the power switch Q (i.e. the frequency of the control signal Sc) to be substantially equal to the fixed frequency. The fixed frequency is substantially equal to the frequency of the pfc circuit 1 operating in the continuous conduction mode CCM (i.e., constant frequency operation).

Under this operating rule, it is expected that the inductor current Il is lower as it is closer to the zero crossing point P of the input voltage Vin, whereas the inductor current Il is higher as it is closer to the peak of the input voltage Vin. Therefore, the controller 3 controls the pfc circuit 1 to operate in the discontinuous conduction mode DCM based on the input voltage Vin within a first predetermined range around the zero-crossing point P (assumed to be 0 v), and controls the power switch Q to be turned on under the condition that the operating frequency Fsw and the inductor current Il reach the threshold ZCD when the power switch Q is switched in the DCM. In the DCM mode, when the inductor current Il decreases to the threshold ZCD, the switching voltage Vds resonates due to the composition of the parasitic capacitor and the power inductor L of the power switch Q, and thus the switching voltage Vds at the two ends of the power switch Q also resonates. Therefore, the best timing for controlling the turn-on of the power switch Q is to control the turn-on of the power switch Q from the first resonance to the valley after the switchable time point of the power switch Q reaches the operating frequency Fsw and the inductor current Il is lower than the threshold ZCD except for the condition that the switchable time point of the power switch Q reaches the operating frequency Fsw and the inductor current Il is lower than the threshold ZCD. When the power switch is turned on under the condition, zero-voltage/zero-current switching can be ensured, and the switching loss of the power switch Q can be reduced.

On the other hand, the controller 3 controls the pfc circuit 1 to operate in the continuous conduction mode CCM based on the input voltage Vin being within a second predetermined range of the peak value, and controls the pfc circuit 1 to operate in the critical conduction mode BCM based on the input voltage Vin being outside the first predetermined range and the second predetermined range. When the pfc circuit 1 operates in the continuous conduction mode CCM (or the boundary conduction mode BCM), the controller 3 may control the power switch Q to be turned on when the switching time of the power switch Q reaches the operating frequency in advance. In the three switching modes, the control is performed mainly for whether the inductor current Il reaches 0, and the controller 3 limits the operating frequencies Fsw of the three to be substantially equal to a fixed frequency, so as to avoid that the operating frequency Fsw is too fast and the loss of the power switch Q is increased when the inductor current Il approaches the zero crossing point P of the input voltage Vin. It should be noted that in the prior art, the operations of DCM and BCM may be frequency conversion.

Referring to fig. 2, 3 and 4, the controller 3 may be a signal processing device with signal processing function, such as a Microcontroller (MCU), a Digital Signal Processor (DSP), etc., and the internal components may be a control module formed by a physical circuit or software control. For example, the comparator shown in fig. 4 may be a physical comparator, or may be a comparison procedure formed by software. In fig. 4, the control path for mainly controlling the on state of the power switch Q according to the present invention is shown by a solid line, and the control path shown by a dotted line is the control path for controlling the off state of the power switch Q. Since the control path for controlling the turn-off of the power switch Q is a common control path of a general power factor corrector, the present elements and their components are illustrated herein, but not limited thereto. All the control paths for controlling the turn-off of the power switch Q for power factor correction should be included in the scope of the present embodiment.

Here, the control path of the broken line is briefly described. The controller 3 captures a feedback signal Vo _ fb of the output voltage Vo from the power factor correction circuit 1, performs error amplification with a reference voltage Vref1, and compensates an error signal thereof to enter the multiplier MULT. The controller 3 also captures a feedback signal Vin _ fb/Vin _ rms of the input voltage Vin of the pfc circuit 1 into the multiplier MULT, where the feedback signal Vin _ fb is also a rectified signal corresponding to the input voltage Vin. The multiplier MULT provides a half-string signal Iref based on the error signal and the feedback signal Vin _ fb/Vin _ rms, which represents the reference signal that the input current Iin needs to follow. Then, the controller 3 captures the current of the power factor correction circuit 1, and after error amplification into an error amplification signal Ipfc, performs compensation operation on the half-sine wave signal Iref and the error amplification signal Ipfc. After the pulse signal is subjected to compensation operation, the pulse signal is compared with a triangular wave signal RAMP to obtain a switch turn-off signal representing that the power switch Q needs to be controlled to be turned off. Therefore, as shown in fig. 3, when the inductor current Il rises to the current value corresponding to the input voltage Vin after the power switch Q is turned on, the controller 3 knows that the power switch Q needs to be turned off by the switch turn-off signal, so that the inductor current Il starts to fall to follow the input voltage Vin.

The control path in the dotted line is divided into two paths, one (path 1) is used for latch control when the inductor current Il is lowered to the threshold ZCD and the on timing of the power switch Q is less than the operating frequency Fsw, and the other (path 2) is used for control when the inductor current Il is lowered to the threshold ZCD and the on timing of the power switch Q is controlled. As shown in fig. 4, the controller 3 includes a comparison module 32, a trigger module 34, a first flip-flop RS1, a first OR module OR1, a second flip-flop RS2, a AND module, a second OR module OR2, AND a third flip-flop RS3. The comparing module 32 is coupled to the zero-crossing detecting circuit 2, and compares the voltage signal Sv corresponding to the switching voltage Vds with the reference voltage Vref2 corresponding to the threshold ZCD to provide a comparison signal Szcd. The trigger module 34 generates the pulse signal Sp based on the comparison signal Szcd, and the trigger module 34 may be an upper edge trigger.

In the path 1, the first flip-flop RS1 provides the first output signal S1 to the first OR module OR1 based on the pulse signal Sp and the control signal Sc, OR the first OR module OR1 provides the logic signal Slg to the second flip-flop RS2 based on the first output signal S1 and the control signal Sc, and the second flip-flop RS2 provides the second output signal S2 based on the first output signal S1 and the clock signal Sck corresponding to the operating frequency Fsw. On path 2, AND block AND provides a third output signal S3 based on the comparison signal Szcd AND the clock signal Sck corresponding to the operating frequency Fsw. The second OR module OR2 receives the signals (i.e., the second output signal S2 and the third output signal S3) of the two paths (path 1 and path 2) to provide a switch-on signal indicating that the power switch Q needs to be controlled to be turned on based on the two signals, and the switch-on signal and the switch-off signal provide the control signal Sc through the logic operation of the third flip-flop RS3.

In the CCM mode, the path in which the controller 3 mainly operates is path 1 of the dotted line control path and the solid line control path. In the solid line control path for controlling the turn-off of the power switch Q, when the inductor current Il rises to the current value corresponding to the input voltage Vin after the power switch Q is turned on, the controller 3 knows that the power switch Q needs to be turned off through the switch turn-off signal. The switch-off signal causes the third flip-flop RS3 to reset such that the control signal Sc is at the low level (L), and the control signal Sc is at the high level (H) before the power switch is turned off in the solid line path such that the switch-on signal is at the low level (L). Therefore, the third flip-flop RS3 can provide the control signal Sc with the low level (L) to the power switch Q.

In the dotted control path for controlling the conduction of the power switch Q, when the power switch Q is turned off, the switch-off signal is at a low level (L), and the path 2 is not activated mainly because the inductor current Il is not as low as the threshold ZCD. Path 1 is mainly activated based on the clock signal Sck, and when the count of the clock signal Sck reaches a specific frequency (such as, but not limited to, 65 KHz), the second flip-flop RS2 is set to provide the second output signal S2 with high level (H) to the second OR module OR, so that the switch conducting signal provided by the second OR module OR is at high level (H). Therefore, the third flip-flop RS3 is triggered, such that the control signal Sc provided by the third flip-flop RS3 is at the high level (H). Therefore, in the CCM mode, the basis for controlling the conduction of the power switch Q is mainly based on the control signal Sc and the clock signal Sck received by the second flip-flop RS 2.

In the DCM mode or the BCM mode, the main paths of the controller 3 are path 1 and path 2 of the dotted line control path and the solid line control path. The dashed control path for controlling the turn-off of the power switch Q is similar to the CCM mode, and will not be described herein. In the solid control path for controlling the power switch Q to be turned on, the solid control path of the controller 3 mainly controls the power switch Q to be turned off during the latch time period based on the pulse signal Sp, and the latch time period is a time period from when the inductor current Il is lower than the threshold ZCD to when the power switch Q is switched to reach the operating frequency Fsw. The path 1 is mainly used for confirming the operation of the power switch Q keeping off in the latch period, and the path 2 is mainly used for confirming whether the time point of switching the power switch Q reaches the operation frequency Fsw.

Specifically, when the inductor current Il falls to the threshold ZCD and the operating frequency Fsw has not been reached, the trigger module 34 generates the pulse signal Sp based on the inductor current Il falling to the threshold ZCD. The first flip-flop RS1 provides the first output signal S1 to latch the second flip-flop RS2 based on the triggering of the pulse signal Sp, so as to lock the second output signal S2 outputted by the second flip-flop RS2 at the low level (L). On the other hand, the clock signal Sck of the path 2 has not counted until reaching the specific frequency (i.e. the operating frequency Fsw has not been reached), AND therefore the third output signal S3 provided by the AND module AND is also at the low level (L). The second OR module OR2 receives the low level (L) signals of the two paths and provides a switch turn-on signal of the low level (L) to control the power switch Q to keep turning off in the latch period. Referring to fig. 3, that is, the controller 3 latches the second flip-flop RS2 at time t 0-t 1 to control the power switch Q to remain off during the latching period, so as to avoid the situation that the operating frequency Fsw is too high near the zero crossing point P of the input voltage Vin.

On the other hand, when the inductor current Il decreases to the threshold ZCD AND reaches the operating frequency Fsw, the AND module AND knows that the power switch Q is switched based on the comparison signal Szcd AND the clock signal Sp, AND the inductor current Il also decreases to the threshold ZCD. Accordingly, AND block AND provides the third output signal S3 (i.e., high (H)) that controls the power switch to turn on accordingly. Therefore, in DCM and BCM modes, the basis for controlling the conduction of the power switch Q is mainly based on the comparison signal Szcd and the clock signal Sck.

It should be noted that, in an embodiment of the present invention, the components shown inside the controller 3 may be a control circuit composed of physical components or a control logic composed of software programs. For example, the AND-block AND may be an AND-gate, an AND circuit composed of electronic components, or a programming language written AND functional by software. As are other components, and will not be described in detail herein.

Referring to fig. 2, 3 and 5, the hybrid mode operation method of the pfc 100 mainly controls the pfc circuit 1 to operate in CCM, BCM and DCM mode, so as to reduce the switching loss to improve the efficiency of the pfc (when the inductor current Il is light load or approaches the zero crossing point P), and when the inductor current Il is large, the inductor current Il has a small peak value to reduce the current stress and conduction loss of the power device. On the other hand, when the pfc circuit 1 operates in CCM, BCM and DCM, the switching frequency of the power switch Q (i.e. the frequency of the control signal Sc) is limited to be substantially equal to the fixed frequency, so as to avoid the loss of the power switch Q caused by the too fast operating frequency Fsw as the inductor current Il approaches the zero-crossing point P of the input voltage Vin.

Therefore, the mixed-mode operation method of the pfc 100 includes controlling the pfc circuit to convert the input voltage into the output voltage by switching the power switch of the operation frequency control pfc circuit, and controlling the input current drawn by the pfc circuit to follow the input voltage (S100). In a preferred embodiment, the controller 3 controls the switching of the power switch Q by the control signal Sc with the operating frequency to control the power factor correction circuit 1 to convert the input voltage Vin into the output voltage Vo, and by controlling the switching timing of the power switch Q, the waveform of the input current Iin extracted by the power factor correction circuit 1 can be controlled to follow the input voltage Vin, so as to improve the power factor of the input terminal of the power factor corrector 100 (usually, the power factor can be improved to be more than 0.9).

Then, an inductor current of a power inductor of the power factor correction circuit is detected (S200). In a preferred embodiment, the zero-crossing detection circuit 2 is coupled to the power inductor L to detect the resonance of the switching voltage Vds across the power switch to generate the corresponding voltage signal Sv. Finally, based on the threshold value of the inductor current being close to zero, the resonance generated by the switch voltage is close to the threshold value of the zero crossing detection circuit, and the switching time of the power switch reaches the operating frequency, the power switch is controlled to be turned on (S300). In a preferred embodiment, the controller 3 is utilized to determine when the power switch Q is switched to the operating frequency, and when the inductor current Il is as low as zero and the zero crossing detection is close to the threshold (such as but not limited to 0 ampere), the power switch Q is controlled to be turned on, so as to limit the switching frequency of the power switch Q (i.e. the frequency of the control signal Sc) to be substantially equal to the fixed frequency. The fixed frequency is substantially equal to the frequency of the pfc circuit 1 operating in the continuous conduction mode CCM (i.e., constant frequency operation). Alternatively, the power switch is turned on (S400) based on the timing of the power switch switching reaching the operating frequency, and the control is the control behavior of the power factor correction circuit 1 in the continuous conduction mode CCM (or boundary conduction mode BCM).

However, the above-mentioned is only a detailed description and drawings of the preferred embodiments of the present invention, but the present invention is not limited thereto, and the present invention should be considered as limited to the following claims, and all the modifications and variations of the embodiments within the spirit and scope of the present invention should be included in the scope of the present invention, and any changes and modifications that can be easily conceived by those skilled in the art can be included in the scope of the present invention.

Claims

1. A mixed-mode power factor corrector comprising: the power factor correction circuit receives an input voltage and comprises a power inductor and a power switch;

a zero-crossing detection circuit coupled to the power inductor for detecting resonance of the switching voltage at two ends of the power switch;

and a controller coupled to the power switch and the zero-crossing detection circuit, and controlling the power factor correction circuit to convert the input voltage to an output voltage by controlling the switching of the power switch through an operation frequency, and controlling the input current drawn by the power factor correction circuit to follow the input voltage;

the method is characterized in that: the controller controls the power switch to be turned on based on that when the inductive current is reduced to zero, the resonance generated by the switching voltage approaches the threshold of the zero-crossing detection circuit, and the switching time of the power switch reaches the operating frequency.

2. The mixed-mode power factor corrector of claim 1, wherein: the controller includes: a comparison module coupled to the zero-crossing detection circuit and comparing a voltage signal corresponding to the inductor current with a reference voltage corresponding to the threshold value to provide a comparison signal; the trigger module generates a pulse signal based on the comparison signal; the controller controls the power switch to be kept off for a latch time period based on the pulse signal, wherein the latch time period is a time period from the time when the inductive current is lower than the threshold value to the time when the power switch is switched to reach the operating frequency.

3. The mixed-mode power factor corrector of claim 2, wherein: the controller further comprises: a first flip-flop that provides a first output signal based on the pulse signal; and a second flip-flop providing a second output signal based on the first output signal; the first flip-flop provides the first output signal to latch the second flip-flop based on the triggering of the pulse signal, so as to lock the second output signal and control the power switch to keep off in relation to the latch time period.

4. The mixed-mode power factor corrector of claim 2, wherein: the controller further comprises: and a module providing a third output signal based on the comparison signal and a clock signal corresponding to the operating frequency; the sum module obtains the time point of switching the power switch to the operating frequency based on the comparison signal and the clock signal, and when the inductive current is low to zero, the resonance generated by the switching voltage approaches the threshold value of the zero-crossing detection circuit, and correspondingly provides the third output signal capable of controlling the conduction of the power switch.

5. The mixed-mode power factor corrector of claim 1, wherein: the controller controls the power factor correction circuit to operate in a discontinuous conduction mode based on the input voltage being within a first predetermined range around a zero-crossing point, controls the power factor correction circuit to operate in a continuous conduction mode based on the input voltage being within a second predetermined range of a peak value, and controls the power factor correction circuit to operate in a critical conduction mode based on the input voltage being outside the first predetermined range and the second predetermined range.

6. The mixed-mode power factor corrector of claim 5, wherein: the controller operates in the discontinuous conduction mode, and when the switching time of the power switch reaches the threshold condition that the resonance generated by the switch voltage is close to zero crossing detection circuit when the operating frequency and the inductive current are low to zero, the power switch is turned on when the switch voltage resonates to a low valley.

7. The mixed-mode power factor corrector of claim 1, wherein: the zero-crossing detection circuit is a winding coupled to the power inductor to detect resonance of the switching voltage.

8. The mixed-mode power factor corrector of claim 1, wherein: the controller controls the power switch to be conducted by reaching the operating frequency in advance based on the switching time point of the power switch.

9. A method of mixed-mode operation of a power factor corrector comprising the steps of: controlling a power factor correction circuit to convert an input voltage to an output voltage by switching a power switch of the operation frequency control power factor correction circuit, and controlling an input current extracted by the power factor correction circuit to follow the input voltage; detecting resonance of the switching voltage at two ends of the power switch; and controlling the power switch to be conducted based on that the inductance current is reduced to zero, the resonance generated by the switch voltage is close to the threshold value of the zero-crossing detection circuit, and the switching time point of the power switch reaches the operating frequency.

10. The mixed-mode operation method of claim 9, wherein: it also includes the following steps:

the power switch is controlled to turn off based on the inductor current rising to a current value corresponding to the input voltage when the power switch is turned on.

11. The mixed-mode operation method of claim 9, wherein: it also includes the following steps: comparing the voltage signal corresponding to the inductor current with the reference voltage corresponding to the threshold value to provide a comparison signal; generating a pulse signal based on the comparison signal; and controlling the power switch to keep turning off in a bolt-lock time period based on the pulse signal; the latching time interval is the time interval between the time when the inductor current is lower than the threshold value and the time when the power switch is switched to reach the operating frequency.

12. The mixed-mode operation method of claim 11, wherein: it also includes the following steps: providing a first output signal based on the pulse signal; and providing a second output signal based on the first output signal; based on the triggering of the pulse signal, the first output signal is provided to lock the second output signal so as to control the power switch to keep off in the bolt-lock time period.

13. The mixed-mode operation method of claim 11, wherein: it also includes the following steps: providing a third output signal based on the comparison signal and a clock signal corresponding to the operating frequency; when the switching time of the power switch reaches the operating frequency based on the comparison signal and the clock signal, and the inductive current is reduced to zero, the resonance generated by the switch voltage approaches the threshold value of the zero-crossing detection circuit, and accordingly the third output signal capable of controlling the conduction of the power switch is provided.

14. The mixed-mode operation method of claim 11, wherein: it also includes the following steps: controlling the PFC circuit to operate in a discontinuous conduction mode based on the input voltage being within a first predetermined range around a zero-crossing point; controlling the power factor correction circuit to operate in a continuous conduction mode based on the input voltage being within a second predetermined range of peak value; and controlling the power factor correction circuit to operate in a critical conduction mode based on the input voltage being outside a first predetermined range and a second predetermined range.

15. The mixed-mode operation method of claim 9, wherein: it also includes the following steps: based on the condition that the power switch is operated in the discontinuous conduction mode and the switching time of the power switch reaches the condition that the operating frequency and the inductive current are low to zero, and the resonance generated by the switch voltage is close to the threshold value of a zero crossing detection circuit, the power switch is turned on when the switch voltage resonates to a low valley.

16. The mixed-mode operation method of claim 9, wherein: it also includes the following steps:

and controlling the power switch to be conducted based on the time point of switching of the power switch reaching the operating frequency in advance.