CN115955906A - Superconducting quantum chip, substrate thereof and manufacturing method of substrate - Google Patents
Superconducting quantum chip, substrate thereof and manufacturing method of substrate Download PDFInfo
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- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
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Abstract
The embodiment of the application provides a superconducting quantum chip, a substrate thereof and a manufacturing method of the substrate, which are used for reducing the effect of chip crosstalk with low cost. The manufacturing method of the substrate comprises the following steps: manufacturing a through hole on a main body of a chip substrate; performing film sputtering treatment on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate, wherein the surface comprises an upper surface and a lower surface; performing metal electroplating treatment on the main body of the chip substrate subjected to film sputtering treatment to form a metal column filled in the through hole and a metal coating covering the upper surface of the main body of the chip substrate; and smoothing the surface of the main body of the chip substrate subjected to metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, so as to form the substrate of the superconducting quantum chip.
Description
Technical Field
The embodiment of the application relates to the field of quantum chip manufacturing, in particular to a superconducting quantum chip, a substrate thereof and a manufacturing method of the substrate.
Background
The quantum computation is a novel computation mode for regulating and controlling a quantum information unit to perform computation according to a quantum mechanics law. Compared with the traditional general computer, the theoretical model of the computer is a universal turing machine. The theory model of the general quantum computation is a general turing machine which is re-interpreted by using the laws of quantum mechanics. From the point of view of computability, quantum computers can only solve the problems that can be solved by traditional computers, but from the point of view of computational efficiency, due to the existence of quantum mechanical superposition, certain known quantum algorithms are faster than the traditional general purpose computers in the problem processing speed.
The superconducting quantum chip is considered as one of the most possible platforms for realizing quantum computation because the processing technology is similar to that of the traditional semiconductor. However, with the rapid increase of the number of superconducting quantum bits in recent years, the required substrate volume of the superconducting quantum chip is also increasing. The substrate acts as a rectangular cavity to generate a TM110 resonant mode, for example, at a frequency of about 7.8GHz when the substrate side length reaches 0.85 cm. Since the commonly used superconducting qubit frequency is between 4-8GHz, the resonant modes of the substrate will introduce large electromagnetic crosstalk if in this range.
In the prior art, a superconducting Through Silicon Via (TSV) process is used to solve the problem of electromagnetic crosstalk of a chip, specifically, a through hole is formed in a main body of a chip substrate, and then a layer of superconducting metal is plated in the through hole by using a special process to destroy electric field distribution on the main body of the chip substrate and push up a cavity film, so that the electromagnetic crosstalk is reduced to a certain extent, but the method is high in cost.
Disclosure of Invention
In view of the above, the present invention has been made to provide a superconducting quantum chip and a substrate thereof, and a method of fabricating the substrate, which overcome or at least partially solve the above problems.
In a first aspect, the present invention provides a method for fabricating a substrate of a superconducting quantum chip, comprising:
manufacturing a through hole on a main body of a chip substrate;
performing film sputtering treatment on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate, wherein the surface comprises an upper surface and a lower surface;
performing metal electroplating treatment on the main body of the chip substrate subjected to the film sputtering treatment to form a metal column filled in the through hole and a metal coating covering the upper surface of the main body of the chip substrate;
and smoothing the surface of the main body of the chip substrate subjected to metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, so as to form the substrate of the superconducting quantum chip.
Optionally, before the fabricating the through hole on the main body of the chip substrate, the method further includes:
cleaning the surface of the main body of the chip substrate by using an organic solvent to remove surface attachments of the main body of the chip substrate.
Optionally, the fabricating the through hole on the main body of the chip substrate includes:
and manufacturing the through hole on the main body of the chip substrate by adopting a laser-induced etching technology, wherein the width of the through hole meets the target width.
Optionally, after the through hole is formed in the main body of the chip substrate, the method further includes:
thinning the main body of the chip substrate by adopting a thinning process so that the thickness of the main body of the chip substrate meets a target thickness;
and polishing the thinned main body of the chip substrate to enable the surface smoothness of the main body of the chip substrate to meet the target smoothness.
Optionally, the performing a film sputtering process on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate includes:
respectively carrying out sputtering treatment on a metal film layer on the surface of the main body of the chip substrate and the inner wall of the through hole by adopting a magnetron sputtering technology so as to generate a barrier layer on the inner wall of the through hole and the surface of the main body of the chip substrate;
after the barrier layer is generated on the inner wall of the through hole and the surface of the main body of the chip substrate, a seed layer is generated on the inner wall of the through hole and the surface of the main body of the chip substrate so that the seed layer covers the barrier layer; wherein the metal film layer comprises the barrier layer and the seed layer.
Optionally, the smoothing the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate includes:
and carrying out aluminum layer electroplating treatment on the main body of the chip substrate by using an organic solvent so as to fill aluminum into the through hole to form an aluminum column, and covering the aluminum on the upper surface of the main body of the chip substrate to form the metal coating, wherein the metal column is the aluminum column.
Optionally, the smoothing the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate includes:
and carrying out metal electroplating treatment on the main body of the chip substrate by using an electroplating process so as to fill copper or gold into the through hole to form a copper column or a gold column, and covering the copper and the gold on the upper surface of the main body of the chip substrate to form the metal coating, wherein the metal column is the copper column or the gold column.
Optionally, the smoothing the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate, and the forming of the substrate of the superconducting quantum chip includes:
etching the main body of the chip substrate by adopting wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate;
and polishing the surface of the etched main body of the chip substrate by adopting a chemical mechanical polishing process so as to ensure that the surface of the main body of the chip substrate is smooth and the thickness of the main body of the chip substrate meets a target thickness.
Optionally, the body of the chip substrate comprises at least quartz glass.
In a second aspect, the invention provides a substrate of a superconducting quantum chip, the substrate includes a main body and a through hole penetrating through upper and lower surfaces of the main body, an inner wall of the through hole is covered with a metal film layer, and a metal column is filled in the through hole covered with the metal film layer, the metal film layer at least includes a seed layer and a barrier layer, wherein the seed layer covers the barrier layer, the barrier layer is located between the inner wall of the through hole and the seed layer, and the main body is made of at least quartz glass.
Optionally, the metal film layer at least includes a seed layer and a barrier layer, the seed layer is a metal film layer containing copper, and the barrier layer is a metal film layer containing tantalum.
Optionally, the substrate of the superconducting quantum chip provided by the second aspect is manufactured by the manufacturing method of the first aspect.
In a third aspect, the present invention provides a superconducting quantum chip, where the superconducting quantum chip includes a substrate of the superconducting quantum chip, a superconducting metal base film covering an upper surface of the substrate, and a circuit structure disposed on the superconducting metal base film, and the substrate of the superconducting quantum chip is the substrate according to the second aspect.
According to the technical scheme, the invention has the following advantages: manufacturing a through hole on a main body of a chip substrate; performing film sputtering treatment on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate, wherein the surface comprises an upper surface and a lower surface; performing metal electroplating treatment on the main body of the chip substrate subjected to the film sputtering treatment to form a metal column filled in the through hole and a metal coating covering the upper surface of the main body of the chip substrate; and smoothing the surface of the main body of the chip substrate subjected to metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, so as to form the substrate of the superconducting quantum chip. According to the embodiment of the application, the through hole structure is formed on the main body of the chip substrate, metal is filled in the through hole part, crosstalk can be effectively inhibited, and the thickness and the structure of the main body of the chip substrate can be selected according to actual requirements. Meanwhile, compared with a silicon substrate, the main body of the chip substrate has lower cost and simple processing technology, and can effectively reduce the cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 is a process step diagram of a method of fabricating a substrate for a superconducting quantum chip according to the present disclosure;
FIG. 2 is a diagram of another process step of a method of fabricating a substrate for a superconducting quantum chip according to the present disclosure;
FIG. 3 is a diagram of another process step of a method of fabricating a substrate for a superconducting quantum chip according to the present disclosure;
FIG. 4 is a flow chart of a method of fabricating a substrate for a superconducting quantum chip according to the present disclosure;
fig. 5 is another flow chart of the method for manufacturing the substrate of the superconducting quantum chip disclosed by the invention.
Detailed Description
The superconducting quantum chip is considered as one of the most possible platforms for realizing quantum computation because the processing technology is similar to that of the traditional semiconductor. However, as the number of bits of superconducting quantum increases dramatically in recent years, the bulk volume of the chip substrate required becomes larger and larger. As the bit frequency of the commonly used superconducting quantum is in the range of 4-8GHz, larger electromagnetic crosstalk can be brought, and the performance of the quantum chip is influenced.
The prior art proposes to solve the problem of chip crosstalk by using superconducting TSV, and particularly, the method is mainly to perform through hole processing on a main body of a chip substrate and then plate a layer of metal (superconducting metal or non-superconducting metal) in the through hole by using a special process so as to destroy the electric field distribution on the substrate and push up a cavity film. Because the cavity film and the frequency are in positive correlation, the frequency can be correspondingly improved while the cavity film is pushed up, and therefore the effect of reducing crosstalk is achieved. However, the silicon wafer has a low price advantage and a high cost.
In another prior art, a special sample box is used to solve the problem of chip electromagnetic crosstalk, a metal column is formed on the sample box itself, a hole is drilled in a position corresponding to the metal column on a substrate of the superconducting quantum chip, and the two are assembled together (the hole on the substrate of the superconducting quantum chip is sleeved on the metal column) to push up a die cavity and inhibit the chip electromagnetic crosstalk.
Because the two schemes have problems, the embodiment of the application provides a manufacturing method of a substrate of a superconducting quantum chip, which is used for reducing the electromagnetic crosstalk of the chip at low cost.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 to 3, fig. 1 to 3 are process step diagrams of a method for manufacturing a substrate of a superconducting quantum chip according to the disclosure. For convenience of description, the three process step small diagrams included in fig. 1 are respectively named as step a, step b and step c from left to right, the three process step small diagrams included in fig. 2 are respectively named as step d, step e and step f from left to right, and the process step small diagram included in fig. 3 is named as step g. It is understood that the steps a, b, c, d, e, f and g are performed in sequence according to the execution sequence of the process steps. Namely, said, steps a to g collectively constitute a method of fabricating a substrate for a superconducting quantum chip. In any process step in fig. 1 to 2, the upper rectangular view is a cross-sectional view of the main body of the chip substrate, and the lower rectangular view is a top view of the main body of the chip substrate. In process step g in fig. 3, the upper rectangular view is a cross-sectional view of the substrate of the superconducting quantum chip, and the lower rectangular view is a top view of the substrate of the superconducting quantum chip. For convenience of understanding, the description is not repeated in the following.
As for step a, the figure may be understood as preparing the body of the chip substrate in advance. Preferably, the body of the chip substrate may be made of one or more semiconductor materials. Wherein the semiconductor material includes but is not limited to silicon Si, silicon dioxide SiO 2 And so on. Of course, the main body of the chip substrate may be made of other suitable insulating materials, such as quartz glass, etc., in this fabrication process. The price and the productivity of the quartz glass are far superior to those of semiconductor materials, so that the superconducting quantum chip manufactured by the process has price advantage, and the quartz glass can be selected as a substrate material of the superconducting quantum chip. For convenience of description, the following description of the main body of the chip substrate is specifically described in detail with respect to the quartz glass substrate.
In the process step shown in step a, a quartz glass substrate (i.e. the bulk of the chip substrate described above) is prepared in advance, and in order to make the thickness of the bulk of the final superconducting quantum chip substrate meet the target thickness, the thickness of the quartz glass substrate may be slightly higher than the target thickness, for example, the target thickness is 300 μm, and the thickness of the quartz glass substrate may be between 330 μm and 350 μm. Alternatively, the silica glass substrate may be cleaned to remove impurities on the surface of the silica glass substrate.
According to the step b, through holes can be manufactured on the quartz glass substrate through methods such as laser modification and wet etching. Of course, the method of making the through-hole is not limited to the method and may be other. As can be readily understood from the cross-sectional view of the main body of the chip substrate in step b, the through-hole completely penetrates the quartz glass substrate. In order to achieve the target performance of the superconducting quantum chip as much as possible, the through hole needs to satisfy a certain aspect ratio. For example, it has been found through experiments that the performance of the superconducting quantum chip satisfies the target performance when the aspect ratio is 6. Of course, other ratios are possible in practice to meet other performance aspect ratios.
One specific embodiment is therefore: through holes with the depth-to-width ratio of 6.
According to the step c, the quartz glass substrate may be thinned through a thinning process to be as thin as possible to a target thickness, and then the quartz glass substrate may be subjected to a surface polishing process to improve the smoothness of the surface of the quartz glass substrate. Of course, the thinning process step is not necessary, and the quartz glass substrate may not need to be thinned if it meets the target thickness.
Thus, one specific embodiment is: the quartz glass substrate is subjected to thinning treatment and polishing treatment by a thinning process, surface polishing, and the like, thereby thinning the quartz glass substrate to a target thickness as much as possible, for example, to a thickness of 300 μm.
According to step d, metal sputtering is performed on the inner wall of the through hole of the quartz glass substrate and the surface of the quartz glass substrate (wherein the surface includes an upper surface and a lower surface) by, but not limited to, film sputtering, so as to grow a metal film layer on the inner wall of the through hole and the surface of the quartz glass substrate. It can be understood that, as can be seen from the cross-sectional view of the main body of the chip substrate in step d, at least two metal film layers exist on the inner wall of the through hole and the surface of the quartz glass substrate, wherein the inner layer is a barrier layer and the outer layer is a seed layer. Namely, the seed layer covers the barrier layer, and the barrier layer is positioned between the inner wall of the through hole and the seed layer. As can be seen from the top view of the body of the chip substrate of step d, the surface of the quartz glass substrate appears grey compared to the top view of the body of the chip substrate of step c, i.e. represents that the surface of the quartz glass substrate is covered with the seed layer.
Thus, one specific embodiment is: and performing metal sputtering treatment on the quartz glass substrate in a film sputtering mode to grow a barrier layer on the inner wall of the through hole and the surface of the quartz glass substrate and grow a seed layer, wherein the metal film layer at least comprises the barrier layer and the seed layer.
According to the step e, the inner wall of the through hole and the upper surface of the quartz glass substrate are electroplated by, but not limited to, a metal electroplating process, so that metal is filled into the inner wall of the through hole to form a metal column filled in the through hole, and meanwhile, metal is filled into the seed layer on the upper surface of the quartz glass substrate to form a metal plating layer covering the seed layer. It can be understood that, compared with the cross-sectional view of the main body of the chip substrate in step d, as can be seen from the cross-sectional view of the main body of the chip substrate in step e, there are dark black layers on the inner walls of the through holes and the upper surface of the quartz glass substrate in step e, that is, the metal posts or the metal plating layers formed after electroplating. Compared with the top view of the main body of the chip substrate in step d, as can be seen from the top view of the main body of the chip substrate in step e, the color of the upper surface of the quartz glass substrate in step e is obviously darker than that of the upper surface of the quartz glass substrate in step d.
Thus, one specific embodiment is: and electroplating a metal coating layer covering the metal film layer and a metal column filled in the through hole on the upper surface of the quartz glass substrate by a metal electroplating process.
According to the step f, the quartz glass substrate is processed through wet etching and polishing processes so as to remove the metal coating on the upper surface of the quartz glass substrate and the metal film layer on the surface of the quartz glass substrate, and then the quartz glass substrate is polished so as to improve the smoothness of the surface of the quartz glass substrate. Finally, the substrate of the superconducting quantum chip can be formed. It is understood that the surface of the quartz glass substrate of step f is a metal plating layer from which the plating and the metal sputtered metal film layer have been removed, as can be seen from the cross-sectional view of the main body of the chip substrate of step f, compared to the cross-sectional view of the main body of the chip substrate of step e. Meanwhile, compared with the top view of the main body of the chip substrate in step e, it can be seen from the top view of the main body of the chip substrate in step f that the dark black pattern layer (i.e., the metal plating layer) has been removed on the quartz glass substrate in step f.
Thus, one specific embodiment is: the metal coating and the metal film layer on the upper surface of the quartz glass substrate and the metal film layer on the lower surface of the quartz glass substrate are removed through a wet etching process, and then the surface of the quartz glass substrate is polished through a polishing process, so that the upper surface and the lower surface of the quartz glass substrate are smooth, and finally the substrate of the superconducting quantum chip is formed.
According to the step g, the substrate of the superconducting quantum chip is processed through processes such as but not limited to magnetron sputtering or electron beam evaporation, so that at least one layer of superconducting metal base film is grown on the upper surface of the substrate of the superconducting quantum chip. It can be understood that, compared with the sectional view of the main body of the chip substrate in step f, as can be seen from the sectional view of the substrate of the superconducting quantum chip in step g, a gray layer exists on the upper surface of the substrate of the superconducting quantum chip in step g, where the gray layer is a superconducting metal base film grown through processes such as magnetron sputtering or electron beam evaporation. Meanwhile, as compared with the top view of the main body of the chip substrate in step f, as can be seen from the top view of the substrate of the superconducting quantum chip in step g, the upper surface of the substrate of the superconducting quantum chip in step g is covered with a gray layer (i.e., a superconducting metal base film).
Thus, one specific embodiment is: at least one layer of superconducting metal bottom film is grown on the substrate of the superconducting quantum chip through the processes of magnetron sputtering, electron beam evaporation and the like, and the superconducting metal bottom film is enabled to cover the substrate of the superconducting quantum chip.
Through the process steps described in fig. 1 to 3, a superconducting quantum chip using quartz glass as a substrate material can be manufactured, and compared with a silicon wafer, the price advantage is more obvious. Moreover, because the superconducting metal bottom film is plated on the through hole, the power plant distribution on the substrate can be effectively damaged, and the cavity film is pushed up, thereby effectively reducing crosstalk and meeting the design requirement of the superconducting quantum chip.
To facilitate understanding of the process steps described in fig. 1 to fig. 3, please refer to fig. 4, where fig. 4 is a flowchart of a method for manufacturing a substrate of a superconducting quantum chip, including steps 401 to 405.
401. Through holes are made on the main body of the chip substrate.
After the choice of using quartz glass as the substrate for the superconducting quantum chip, it is necessary to make through holes in the bulk of the chip substrate. It will be appreciated that, as is evident from the body of the chip substrate described above with reference to fig. 1 to 3, the body of the chip substrate may be made of one or more semiconductor materials. Wherein the semiconductor material includes but is not limited to silicon Si, silicon dioxide SiO 2 And the like. Of course, the main body of the chip substrate may be made of other suitable insulating materials, such as quartz glass, etc., in this fabrication process. As the price and the productivity of the quartz glass are far superior to those of semiconductor materials, the substrate of the superconducting quantum chip manufactured by the process has more price advantage, and therefore, the quartz glass can be selected as the substrate of the superconducting quantum chip. For convenience of description, the following description of the main body of the chip substrate is specifically described in detail with reference to a quartz glass substrate.
It is understood that the glass substrate material has no freely moving charges, so that the glass substrate material has a large amount of dielectric properties, low high-frequency loss and good transmission characteristics, and is suitable for high-frequency applications. The glass through hole Technology (TGV) does not need to manufacture an insulating layer, thereby reducing the process complexity and the processing cost. In some embodiments, through holes can be made in the quartz glass substrate to meet design requirements.
In some embodiments, through hole processing can be rapidly performed on the quartz glass substrate by a method combining laser modification and wet etching. The laser modification and wet etching method has high hole forming precision and high processing efficiency. Specifically, laser induced modification is carried out at the position where the TGV through hole needs to be manufactured, and then the glass material at the modified position is etched through wet etching to form the TGV through hole array.
Based on the above embodiments, the aspect ratio of the through hole can be set according to the use requirement, and in a specific embodiment, the aspect ratio of the through hole can be designed to be greater than or equal to 6:1. in particular, this is to ensure that the superconducting quantum chip can achieve the optimal performance in the subsequent electroplating process. Of course, the through hole array can be determined by the specification and the size of the main body of the chip substrate. In the case that the aspect ratio does not exceed 6: in case 1, the TGV pores were well metallized. As can be seen from the top view or the cross-sectional view in fig. 1 to fig. 3, the through hole arrays are regularly distributed, and in another embodiment, the number or the arrangement of the through hole arrays on the quartz glass substrate may not be limited. It should be understood that the above is only a specific example of the process of making the through holes, and for the aspect ratio and the through hole array described above, different aspect ratios or through hole arrays may also be designed according to design requirements, and the details are not limited herein.
402. And carrying out film sputtering treatment on the main body of the chip substrate so as to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate.
And after the through holes on the quartz glass substrate are generated, performing film sputtering treatment on the quartz glass substrate. Specifically, film sputtering is mainly performed on the inner wall of the through hole of the quartz glass substrate and the surface (upper surface and lower surface) of the quartz glass substrate, so that corresponding metal films can also be grown on the inner wall of the through hole and the surface of the quartz glass substrate. Meanwhile, the inner wall of the through hole also needs to be completely covered by the metal film layer.
In some embodiments, the metal film layer grown on the inner wall of the through hole and the surface of the quartz glass substrate at least comprises a barrier layer and a seed layer. Specifically, after a barrier layer is grown on the inner wall of the through hole and the surface of the quartz glass substrate through film sputtering treatment, a seed layer is grown on the basis of the barrier layer. Moreover, the barrier layer and the seed layer can completely cover the inner walls of the two sides of the through hole, so that the quartz glass substrate between any two adjacent through holes is wrapped. It will be understood that the seed layer at this point covers the barrier layer. Namely, the seed layer covers the barrier layer, and the barrier layer is positioned between the inner wall of the through hole and the seed layer.
403. And performing metal electroplating treatment on the main body of the chip substrate subjected to the film sputtering treatment to form a metal column filled in the through hole and a metal coating covering the upper surface of the main body of the chip substrate.
After the metal film layer grows on the inner wall of the through hole of the quartz glass substrate, metal electroplating treatment needs to be carried out on the quartz glass substrate, so that metal is filled on the metal film layer on the inner wall of the through hole and the upper surface of the quartz glass substrate.
In some embodiments, an aluminum layer plating process may be performed using an organic solution, so as to achieve aluminum layer filling of the inner wall of the through hole, and finally, an aluminum pillar (i.e., a metal pillar including aluminum) is formed on the inner wall of the through hole, and a metal film layer including aluminum is formed on the upper surface of the quartz glass substrate.
Of course, in another embodiment, the quartz glass substrate may be subjected to a metal plating process using an electroplating process, so as to fill metal on the metal film layers (barrier layer and seed layer) filled in the above steps. Specifically, metal is filled to the upper surface of the quartz glass substrate and the inner wall of the through hole, and a metal plating layer covering the metal film layer and a metal column completely filling the through hole are formed on the upper surface of the quartz glass substrate. Based on this example, the metal may be gold or copper, but may alternatively, in some embodiments, be electroplated from other metals.
It should be noted that, in the electroplating process, the thickness of the grown metal coating may be different and the corresponding polarization resistance may also be different under different electroplating time and current density.
404. And smoothing the surface of the main body of the chip substrate subjected to the metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, thereby forming the substrate of the superconducting quantum chip.
The metal film layer grown on the inner wall of the through hole or the filled metal column cannot exceed the surface of the quartz glass substrate, that is, the surface of the quartz glass substrate should be smooth and in the same horizontal plane, so that after all the through holes are filled with the metal coating, wet etching and polishing treatment needs to be performed on the quartz glass substrate, so as to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate. It should be noted that, the smoothing treatment described in this embodiment includes, but is not limited to, the wet etching and polishing treatment described above, and since the surface of the finally formed quartz glass substrate needs to be flat and smooth, the wet etching treatment may be performed on the surface of the quartz glass substrate, so as to make the surface of the quartz glass substrate flat, and then the polishing treatment may be performed on the surface of the quartz glass substrate, so as to make the surface of the quartz glass substrate smooth.
In one embodiment, the redundant metal film layer and the metal coating on the surface of the quartz glass substrate are removed by wet etching. Since there may be a concave or convex portion on the surface of the silica glass substrate after wet etching, it is necessary to perform a polishing process on the silica glass substrate after wet etching to smooth the surface of the silica glass substrate.
And finally, after wet etching and polishing treatment are carried out on the quartz glass substrate, the quartz glass substrate can be treated, and thus the substrate of the superconducting quantum chip is formed.
According to the manufacturing method of the substrate of the superconducting chip, quartz glass is used as a substrate material, the through hole structure is formed on the main body of the chip substrate, and metal is filled in the through hole part, so that crosstalk is effectively inhibited, and the thickness and the passing structure of the quartz glass can be selected according to actual requirements. Meanwhile, compared with a silicon substrate, the main body of the chip substrate has lower cost and simple processing technology, and can effectively reduce the cost.
To facilitate understanding of the process steps described in fig. 1 to fig. 3 and the method flow described in fig. 4, please refer to fig. 5, fig. 5 is a flow chart of a method for manufacturing a substrate of a superconducting quantum chip according to another embodiment of the present disclosure, which includes steps 501 to 509.
501. And carrying out surface cleaning on the surface of the main body of the chip substrate by using an organic solvent to remove surface attachments of the main body of the chip substrate.
The material of quartz glass can be selected but not limited to be used as the substrate of the superconducting quantum chip. Taking the quartz glass substrate as an example, before the superconducting quantum chip is manufactured, the surface (the upper surface and the lower surface) of the quartz glass substrate may be cleaned by using an organic solvent to remove the surface attachments of the quartz glass substrate. For example, the organic solution may be a tetrahydrofuran-benzene AlCl 3 +LiAlH 4 The organic solvent of (1). Of course, organic solvents containing other substances, e.g. AlCl, may also be selected 3 -LiAlH 4 Diethyl ether, alBr 3 -MBr-benzene (toluene), etc., and is not particularly limited herein.
In some embodiments, the fused silica glass may be cleaned using an organic reagent to remove surface contaminants. Specifically, the main material of the quartz glass at this time is silicon dioxide SiO 2 The specific dimensional structure may be a 2 inch wafer, with process tolerances, such that the quartz glass substrate is selected to have a thickness of about 330-350 μm.
It is understood that the materials and dimensions of the quartz glass substrate are merely illustrative, and other conditions may be used.
In other embodiments, the characteristics of the quartz glass material and the characteristics of the TGV process can be combined to make a pretreatment scheme for degreasing and microetching, specifically, a treatment process of degreasing by acetone to remove organic contamination on the surface of the quartz glass substrate, removing microscopic particles on the surface of the substrate by chromic acid oxidation effect, and soaking the microetching substrate by 10% hydrofluoric acid is adopted to clean the surface of the quartz glass substrate. It will be appreciated that the above cleaning options are merely exemplary and that other options are possible.
Based on the embodiment, in order to improve the cleaning rate, the cleaning uniformity and the subsequent etching rate, 5% of NH4F additive can be added into the original 20% hydrofluoric acid solution, and a water bath heating mode of 40 ℃ is adopted, so that the etching rate and the uniformity of the subsequent wet etching can be effectively improved, the batch processing of TGV through holes can be realized, and the through hole rate is improved to more than 99% from the previous 30% or less. It will be appreciated that the above cleaning options are merely exemplary and that other options are possible.
It should be noted that other descriptions may refer to the description of step a, and are not repeated herein.
502. And manufacturing a through hole on the main body of the chip substrate by adopting a laser induction and etching technology.
Step 502 in this embodiment is similar to step 401 in fig. 4, and is not described herein again. It should be noted that the through holes can be formed by combining laser induction and wet etching.
In some embodiments, it is understood that the aspect ratio of the through hole may be other ratios, for example, 7: 1. 8:1 or 9:1, etc., and are not specifically limited herein. For example, the aspect ratio may be low, but not too high, which may affect the fabrication of the seed layer during sputtering. Correspondingly, if the aspect ratio changes, the aperture of the through hole needs to be adaptively adjusted, and the details are not limited herein. Optimally, in this embodiment, the target aspect ratio of the selected through hole is 6:1.
based on the embodiment described in step 501, the quartz glass substrate after laser modification (laser induction) is subjected to wet etching, and after etching, deionized water can be used for ultrasonic cleaning to clean the hydrofluoric acid remaining on the inner wall of the through hole. It will be appreciated that the above cleaning options are merely exemplary and that other options are possible.
It should be noted that other descriptions may refer to the description of step b, and are not repeated herein.
503. The main body of the chip substrate is processed by a thinning process and a surface polishing process.
In some embodiments, after the through holes are formed in the main body of the chip substrate, in order to make the thickness of the quartz glass substrate meet the target thickness, i.e. 300 μm, a thinning process is required to thin the quartz glass substrate, so as to thin the quartz glass substrate to the target thickness. Of course, the thinning process step is not necessary, and the quartz glass substrate may not need to be thinned if it meets the target thickness.
After the quartz glass substrate is processed by using a wet etching process or a thinning process, the surface of the quartz glass substrate may have a condition of non-uniform surface. In addition, due to the existence of a certain non-uniformity in wet etching, a certain damage exists in a local area of the quartz glass substrate, namely the edge of the TGV hole, or a certain over-etching phenomenon exists on the surface of the substrate, so that the surface quality of the substrate needs to be improved through surface treatment processes such as polishing and the like, and the uniform surface state without microscopic defects of the quartz glass substrate is recovered. Alternatively, the roughness does not satisfy the target roughness, and thus, in some embodiments, it is necessary to perform a polishing process on the silica glass substrate using a surface polishing process (e.g., a chemical mechanical polishing process) to improve the surface smoothness of the silica glass substrate. It should be understood that the above-described polishing process is merely exemplary, and other processes are possible.
It should be noted that other descriptions may refer to the description of step c, and are not repeated herein.
504. And respectively carrying out sputtering treatment on the metal film layer on the surface of the main body of the chip substrate and the inner wall of the through hole by adopting a magnetron sputtering technology so as to generate a barrier layer and a seed layer on the inner wall of the through hole and the surface of the main body of the chip substrate.
Step 504 in this embodiment is similar to step 402 in fig. 4, and is not described herein again. It should be noted that, in one embodiment, magnetron sputtering may be used to sputter the surface (including the upper surface and the lower surface) of the quartz glass substrate and the inner wall of the through hole with a metal film layer. Specifically, the metal film layer comprises at least two layers, namely a barrier layer and a seed layer. Correspondingly, a barrier layer can be grown on the inner wall of the through hole and the surface of the quartz glass substrate, and then a seed layer is grown on the basis of the barrier layer. Namely, the seed layer covers the barrier layer, and the barrier layer is positioned between the inner wall of the through hole and the seed layer.
In one embodiment, the barrier layer may be tantalum, that is, the metal film layer corresponding to the barrier layer is a tantalum film, and the seed layer may be copper, that is, the metal film layer corresponding to the seed layer is a copper film. It is understood that, besides the above-described superconducting metal, other non-superconducting metal materials may be used, and correspondingly, other superconducting metal materials may also be used, which are not described herein in detail. Thereby ensuring that the metal film layer on the inner wall of the through hole completely covers the surface of the quartz glass substrate. It is understood that the copper film (seed layer) at this time is overlaid on the tantalum film (barrier layer).
It should be noted that other descriptions may refer to the description of step d, and are not repeated herein.
505. And carrying out metal electroplating treatment on the main body of the chip substrate by using an electroplating process so as to fill metal into the through hole to form a metal column, and covering the metal on the upper surface of the main body of the chip substrate to form a metal coating.
Step 505 in this embodiment is similar to step 403 in fig. 4, and is not described herein again.
It should be noted that, in some embodiments, an aluminum layer electroplating process may be performed using an organic solution, so as to achieve aluminum layer (metal plating) filling of the inner wall of the through hole and the upper surface of the quartz glass substrate, wherein the aluminum filled into the inner wall of the through hole forms a metal pillar (i.e., aluminum pillar) containing aluminum. It will be appreciated that the above-described alternative plating schemes are merely illustrative and that other scenarios are possible.
In some other embodiments, the quartz glass substrate may be further subjected to a metal plating process using an electroplating process, so that copper or gold is filled into the through hole to form a copper pillar or a gold pillar, and the copper or gold is covered on the upper surface of the main body of the chip substrate to form a metal plating layer, wherein the metal pillar is a copper pillar or a gold pillar, and the metal plating layer covers the metal film layer on the upper surface of the chip substrate. According to this embodiment, the metal corresponding to the metal plating layer or the metal pillar may be gold or copper. However, it may be modified and in some embodiments, plated from other metals. And are not specifically limited herein.
It should be noted that other descriptions may refer to the description of step e, and are not repeated herein.
506. And etching the main body of the chip substrate by adopting wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate.
Since in step 505, during the metal electroplating process, there may be a situation of metal plating layer overplating, and at the same time, it is also necessary to remove the metal plating layer or the metal film layer covering the upper surface of the quartz glass substrate and the metal film layer covering the lower surface of the quartz glass substrate, in some embodiments, the surface (upper surface and lower surface) of the quartz glass substrate may be etched by wet etching, so as to remove the metal plating layer (see step 505) and the metal film layer (see step 504) covered by the upper surface of the quartz glass substrate and the metal film layer (see step 504) covered by the lower surface of the quartz glass substrate. It should be understood that the above selected etching schemes are only exemplary, and other situations are also possible.
507. And polishing the surface of the etched main body of the chip substrate by using a chemical mechanical polishing process so as to smooth the surface of the main body of the chip substrate and ensure that the thickness of the main body of the chip substrate meets the target thickness.
Because the wet etching has a certain non-uniformity, the edge of the TGV hole in the local area of the quartz glass substrate has a certain damage or the surface of the substrate has a certain over-etching phenomenon, the surface quality of the substrate needs to be improved by surface treatment processes such as a chemical mechanical polishing process and the like, and the uniform surface state without microscopic defects of the quartz glass substrate is recovered.
Specifically, in some embodiments, the surface of the quartz glass substrate is polished by a chemical mechanical polishing process to remove the metal film layer (including at least the barrier layer and the seed layer) and the metal plating layer in the through hole beyond the surface (upper surface and lower surface) of the quartz glass substrate, thereby smoothing the surface of the body of the chip substrate. Meanwhile, since the target thickness of the quartz glass substrate is determined to be 300 μm, when the thickness of the quartz glass substrate does not satisfy the target thickness in the above step, at this time, the quartz glass substrate may be further polished by a chemical mechanical polishing process to finely adjust the thickness of the quartz glass substrate so that the thickness of the quartz glass substrate satisfies the target thickness.
Based on the above embodiment, the polishing pad is a porous polyurethane polishing pad, and the polishing solution is SiO 2 Polishing solution with fine (nanometer) abrasive grain diameter and using alkaline SiO 2 The colloid polishing has the characteristic of typical chemical mechanical polishing process for micro polishing of the surface of a substrate, namely SiO 2 The abrasive particle suspension has good dispersibility and fluidity, can effectively remove the passive film formed on the surface of the quartz glass, and simultaneously cuts off the Si-O-Si bonds on the surface of the quartz glass through mechanical action, because of SiO 2 The hardness is low, the grain size is small, the silica sol is easy to generate gelation, and the chemical reaction and the mechanical friction are alternately and circularly carried out in the whole polishing process to carry out micro and precise surface processing on the quartz glass substrate. It should be understood that the above-described polishing schemes are merely exemplary, and other scenarios are possible.
It should be noted that other descriptions in step 506 to step 507 may refer to the description of step f, and are not described herein again.
And finally, after wet etching and polishing treatment are carried out on the quartz glass substrate, the quartz glass substrate can be treated, and thus the substrate of the superconducting quantum chip is formed.
508. And growing a superconducting metal bottom film on the substrate of the superconducting quantum chip so as to grow the superconducting metal bottom film on the upper surface of the substrate of the superconducting quantum chip.
After the through holes are processed, in order to enable different through holes to have good vertical interconnection performance, a superconducting metal bottom film is grown on a substrate of the superconducting quantum chip, and the superconducting metal bottom film is grown on the upper surface of the substrate of the superconducting quantum chip, so that the through holes on the substrate of the superconducting quantum chip form circuit connection.
Specifically, a superconducting metal base film can be grown on the substrate of the superconducting quantum chip by adopting processes such as magnetron sputtering or electron beam evaporation. It will be appreciated that the above growth schemes are merely exemplary and that other scenarios are possible. Wherein the superconducting metal base film comprises at least an aluminum film, a tantalum film or a niobium film.
Correspondingly, in some embodiments, if the metal plated in step 505 is aluminum, i.e., the metal included in the metal pillar is aluminum, the superconducting metal base film comprises at least an aluminum film, a niobium film or a tantalum film. If the metal plated in step 505 is gold, i.e., the metal included in the metal pillar is gold, the superconducting metal base film at least includes a gold film, a tantalum film, a niobium film or a copper film. If the metal plated in step 505 is copper, i.e. the metal contained in the metal pillar is copper, the superconducting metal base film includes at least a copper film, a niobium film or a tantalum film. In one embodiment, it is understood that the metal contained in the base superconducting metal film is not affected by the metal contained in the base of the superconducting quantum chip.
It should be noted that other descriptions may refer to the description of step g, and are not repeated herein.
509. And carrying out chip processing on the substrate of the superconducting quantum chip on which the superconducting metal bottom film grows to form the superconducting quantum chip.
After the superconducting metal base film grows on the substrate of the superconducting quantum chip, the substrate of the superconducting quantum chip can be correspondingly processed, and thus the superconducting quantum chip is formed.
It should be further noted that steps 508 to 509 may be understood as steps of processing the substrate of the superconducting quantum chip, and steps 508 to 509 may not be executed in the step of manufacturing the substrate of the superconducting quantum chip, which is not limited herein.
The embodiment designs a manufacturing method of the main body of the superconducting quantum chip substrate, which has a relatively simple processing technology and can realize crosstalk inhibition. The method comprises the steps of utilizing a semiconductor processing technology, adopting quartz glass as a substrate, utilizing a TGV technology to manufacture a through hole in a wet etching mode, a laser drilling mode and the like, and filling superconducting metal in the through hole to achieve the purpose of inhibiting crosstalk. Moreover, the manufacturing method can realize the suppression of the substrate crosstalk without a sample box, and the thickness of the quartz glass and the structure of the through hole can be selected according to actual requirements. Compared with the TSV process, the TGV product has better microwave performance, the process can be simplified, parasitic capacitance can be reduced, electromagnetic interference of a through hole is reduced, the glass wafer has the same order of magnitude and has huge price advantage compared with a silicon wafer, and the processing process is simple, so that the cost is lower than that of a silicon substrate.
The invention also provides a substrate of the superconducting quantum chip, which comprises but is not limited to a main body of the chip substrate and a through hole penetrating through the upper surface and the lower surface of the main body, wherein the inner wall of the through hole is covered with a metal film layer, a metal column is filled in the through hole covered with the metal film layer, the metal film layer at least comprises a seed layer and a barrier layer, the seed layer covers the barrier layer, the barrier layer is positioned between the inner wall of the through hole and the seed layer, and the main body is made of quartz glass.
The present invention also provides a superconducting quantum chip including a base of the superconducting quantum chip manufactured by the above-described fig. 4 to 5, a superconducting metal base film, and a circuit structure disposed on the superconducting metal base film.
As can be seen from the above description, the substrate of the superconducting quantum chip may be made by the process steps of the method for manufacturing the substrate of the superconducting quantum chip described in fig. 1 to 3, or the method flows of the method for manufacturing the substrate of the superconducting quantum chip described in fig. 4 to 5, or may be made by other manufacturing methods in other embodiments, which are not described herein again.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.
The features of the above-described embodiments are useful for understanding embodiments of the present invention by those of ordinary skill in the art. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent substitutions do not depart from the spirit and scope of the present invention, and that they may be changed, substituted, or altered without departing from the spirit and scope of the present invention.
Claims (13)
1. A method of fabricating a substrate for a superconducting quantum chip, the method comprising:
manufacturing a through hole on a main body of a chip substrate;
performing film sputtering treatment on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate, wherein the surface comprises an upper surface and a lower surface;
performing metal electroplating treatment on the main body of the chip substrate subjected to the film sputtering treatment to form a metal column filled in the through hole and a metal coating covering the upper surface of the main body of the chip substrate;
and smoothing the surface of the main body of the chip substrate subjected to metal electroplating treatment to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate, so as to form the substrate of the superconducting quantum chip.
2. The method of claim 1, wherein before the forming the via hole in the body of the chip substrate, the method further comprises:
cleaning the surface of the main body of the chip substrate by using an organic solvent to remove surface attachments of the main body of the chip substrate.
3. The method of claim 1, wherein the forming the via hole in the body of the chip substrate comprises:
and manufacturing the through hole on the main body of the chip substrate by adopting a laser-induced etching technology, wherein the width of the through hole meets the target width.
4. The method of claim 1, wherein after the via is formed in the body of the chip substrate, the method further comprises:
thinning the main body of the chip substrate by adopting a thinning process so that the thickness of the main body of the chip substrate meets a target thickness;
and polishing the thinned main body of the chip substrate to enable the surface smoothness of the main body of the chip substrate to meet the target smoothness.
5. The method of claim 1, wherein the step of performing a film sputtering process on the main body of the chip substrate to grow a metal film on the inner wall of the through hole and the surface of the main body of the chip substrate comprises:
respectively carrying out sputtering treatment on a metal film layer on the surface of the main body of the chip substrate and the inner wall of the through hole by adopting a magnetron sputtering technology so as to generate barrier layers on the inner wall of the through hole and the surface of the main body of the chip substrate;
after the barrier layer is generated on the inner wall of the through hole and the surface of the main body of the chip substrate, a seed layer is generated on the inner wall of the through hole and the surface of the main body of the chip substrate so that the seed layer covers the barrier layer; wherein the metal film layer comprises the barrier layer and the seed layer.
6. The manufacturing method according to claim 1, wherein the smoothing of the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate comprises:
and carrying out aluminum layer electroplating treatment on the main body of the chip substrate by using an organic solvent so as to fill aluminum into the through hole to form an aluminum column, and covering the aluminum on the upper surface of the main body of the chip substrate to form the metal coating, wherein the metal column is the aluminum column.
7. The manufacturing method according to claim 1, wherein the smoothing of the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate comprises:
and carrying out metal electroplating treatment on the main body of the chip substrate by using an electroplating process so as to fill copper or gold into the through hole to form a copper column or a gold column, and covering the copper or the gold on the upper surface of the main body of the chip substrate to form the metal plating layer, wherein the metal column is the copper column or the gold column.
8. The manufacturing method according to claim 1, wherein the smoothing the surface of the main body of the chip substrate subjected to the metal plating process to remove the metal film layer on the surface of the main body of the chip substrate and the metal plating layer on the upper surface of the main body of the chip substrate comprises:
etching the main body of the chip substrate by adopting wet etching to remove the metal film layer on the surface of the main body of the chip substrate and the metal coating on the upper surface of the main body of the chip substrate;
and polishing the surface of the etched main body of the chip substrate by adopting a chemical mechanical polishing process so as to ensure that the surface of the main body of the chip substrate is smooth and the thickness of the main body of the chip substrate meets a target thickness.
9. The production method according to any one of claims 1 to 8, wherein the main body of the chip substrate includes at least quartz glass.
10. A substrate for a superconducting quantum chip, comprising: the metal column-filled metal film comprises a main body and a through hole penetrating through the upper surface and the lower surface of the main body, wherein a metal film layer covers the inner wall of the through hole, a metal column is filled in the through hole of the metal film layer, the metal film layer at least comprises a seed layer and a barrier layer, the seed layer covers the barrier layer, the barrier layer is located between the inner wall of the through hole and the seed layer, and the main body is at least made of quartz glass.
11. The substrate of a superconducting quantum chip of claim 10, wherein the seed layer is a metal film layer comprising copper and the barrier layer is a metal film layer comprising tantalum.
12. A substrate for a superconducting quantum chip according to claim 10, wherein the substrate is fabricated by the method of any one of claims 1-9.
13. A superconducting quantum chip, comprising a substrate of the superconducting quantum chip, a superconducting metal bottom film covering an upper surface of the substrate, and a circuit structure disposed on the superconducting metal bottom film, wherein the substrate of the superconducting quantum chip is the substrate according to any one of claims 10 to 12.
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