CN115840487A - Voltage generation circuit with adjustable differential mode range and common mode level - Google Patents
Voltage generation circuit with adjustable differential mode range and common mode level Download PDFInfo
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- CN115840487A CN115840487A CN202211515654.9A CN202211515654A CN115840487A CN 115840487 A CN115840487 A CN 115840487A CN 202211515654 A CN202211515654 A CN 202211515654A CN 115840487 A CN115840487 A CN 115840487A
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Abstract
The invention belongs to the field of analog integrated circuit design, and particularly relates to a voltage generation circuit with adjustable differential mode range and common mode level. The invention utilizes two constant currents to cooperate with the adjustable resistor to generate linearly-changed voltage, and then combines a circuit network consisting of an operational amplifier and a resistor to generate voltage with adjustable differential mode range and common mode level.
Description
Technical Field
The invention belongs to the field of analog integrated circuit design, and particularly relates to a voltage generation circuit with adjustable differential mode range and common mode level.
Background
In an analog integrated circuit, many scenarios require a reference voltage, and the circuit usually adopts a differential structure, and the reference voltage is mostly presented in pairs of positive and negative phases. The reference voltage in a general circuit is set to be a fixed voltage, but in some complex circuits, it is desirable that the reference voltage is adjustable to achieve more functions and even improve the performance of a circuit system.
Disclosure of Invention
In view of the above, the present invention provides a voltage generating circuit with adjustable differential mode range and common mode level, as shown in fig. 1. The invention utilizes two constant currents to generate linearly-changed voltage in cooperation with an adjustable resistor, and then generates voltage with adjustable differential mode range and common mode level by combining a circuit network consisting of an operational amplifier and a resistor.
The technical scheme of the invention is as follows:
a voltage generating circuit with adjustable differential mode range and common mode level comprises a first current source I1, a second current source I2, a first adjustable resistor RV1, a second adjustable resistor RV2, a first amplifier AMP1, a second amplifier AMP2, a third amplifier AMP3, a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7.
A first connection end of the first current source I1 is connected with a power supply voltage VDD, and a second connection end is connected with a first connection end of the first adjustable resistor RV1 and a positive phase input end of the first amplifier AMP 1;
a first connecting end of the second current source I2 is connected with the power supply voltage VDD, and a second connecting end is connected with a first connecting end of the second adjustable resistor RV2 and an inverting input end of the third amplifier AMP 3;
a first connection end of the first adjustable resistor RV1 is connected with a second connection end of the first current source I1 and a positive phase input end of the first amplifier AMP1, and a second connection end thereof is connected with a ground end GND;
a first connecting end of the second adjustable resistor RV2 is connected with a second connecting end of the second current source I2 and an inverting input end of the third amplifier AMP3, and a second connecting end thereof is connected with a ground end GND;
the inverting input end of the first amplifier AMP1 is connected with the output end of the first amplifier AMP1, the non-inverting input end of the first amplifier AMP1 is connected with the first connection end of the first adjustable resistor RV1 and the second connection end of the first current source I1, and the output end of the first amplifier AMP1 is connected with the first connection end of the first resistor R1;
the inverting input end of the second amplifier AMP2 is connected to the second connection end of the fifth resistor R5 and the first connection end of the sixth resistor R6, the non-inverting input end is connected to the second connection end of the first resistor R1 and the first connection end of the second resistor R2, and the output end is connected to the gate of the first transistor M1 and the first connection end of the first capacitor C1;
the inverting input end of the third amplifier AMP3 is connected to the second connection end of the second current source I2 and the first connection end of the second adjustable resistor RV2, the non-inverting input end is connected to the second connection end of the third resistor R3 and the second connection end of the fourth resistor R4, and the output end is connected to the gate of the second transistor M2 and the second connection end of the second capacitor C2;
a first connection end of the first capacitor C1 is connected with the gate of the first transistor M1 and the output end of the second amplifier AMP2, and a second connection end is connected with the drain of the first transistor M1 and a first connection end of the seventh resistor R7;
a first connection end of the second capacitor C2 is connected to the drain of the second transistor M2 and a second connection end of the seventh resistor R7, and the second connection end is connected to the gate of the second transistor M2 and the output end of the third amplifier AMP 3;
the grid electrode of the first transistor M1 is connected with the first connection end of the first capacitor C1 and the output end of the second amplifier AMP2, the source electrode of the first transistor M1 is connected with a power supply voltage VDD, and the drain electrode of the first transistor M1 is used as a first output port VA and is connected with the first connection end of the seventh resistor R7;
the gate of the second transistor M2 is connected to the second connection terminal of the second capacitor C2 and the output terminal of the third amplifier AMP3, the source is connected to the ground GND, and the drain is used as the second output port VB and connected to the second connection terminal of the seventh resistor R7;
the first connection end of the first resistor R1 is connected with the output end of the first amplifier AMP1, and the second connection end of the first resistor R1 is connected with the first connection end of the second resistor R2;
the first connection end of the second resistor R2 is connected with the second connection end of the first resistor R1 and the positive phase input end of the second amplifier AMP2, and the second connection end is connected with the first connection end of the third resistor R3 and the second connection end of the seventh resistor R7;
a first connection end of the third resistor R3 is connected to a second connection end of the second resistor R2 and a second connection end of the seventh resistor R7, and the second connection end is connected to a second connection end of the fourth resistor R4 and a positive phase input end of the third amplifier AMP 3;
the first connection end of the fourth resistor R4 is connected with the first connection end of the fifth resistor R5 and the first connection end of the seventh resistor R7, and the second connection end is connected with the second connection end of the third resistor R3 and the positive-phase input end of the third amplifier AMP 3;
the first connection end of the fifth resistor R5 is connected with the first connection end of the fourth resistor R4 and the first connection end of the seventh resistor R7, and the second connection end is connected with the first connection end of the sixth resistor R6 and the inverting input end of the second amplifier AMP 2;
a first connection end of the sixth resistor R6 is connected with a second connection end of the fifth resistor R5 and the inverted input end of the second amplifier AMP2, and the second connection end is connected with a ground end GND;
a first connecting end of the seventh resistor R7 is connected to the drain of the first transistor M1 and the output port VA, and a second connecting end is connected to the drain of the second transistor M2 and the output port VB;
the first current source I1, the first adjustable resistor RV1, the second current source I2 and the second adjustable resistor RV2 generate two voltages V1 and V2 which change linearly along with the resistance value of the resistors, and finally a group of voltages VA and VB with adjustable differential mode ranges and common mode levels are output through a subsequent circuit network.
The invention has the beneficial effects that: the invention generates a group of voltages with adjustable differential mode range and common mode level, has higher flexibility and practicability compared with fixed level, and can be suitable for circuit systems under different conditions.
Drawings
Fig. 1 is a schematic diagram of an inventive voltage generation circuit with adjustable differential mode range and common mode level.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be noted that, in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. For example, the first connection end and the second connection end of the capacitor and the resistor only represent two connection ends of the capacitor and the resistor, and the first connection end and the second connection end can be interchanged.
The invention provides a voltage generating circuit with adjustable differential mode range and common mode level, which comprises a first current source I1, a second current source I2, a first adjustable resistor RV1, a second adjustable resistor RV2, a first amplifier AMP1, a second amplifier AMP2, a third amplifier AMP3, a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7. A first connection end of the first current source I1 is connected with a power supply voltage VDD, and a second connection end is connected with a first connection end of the first adjustable resistor RV1 and a positive phase input end of the first amplifier AMP 1; a first connecting end of the second current source I2 is connected with the power supply voltage VDD, and a second connecting end is connected with a first connecting end of the second adjustable resistor RV2 and an inverting input end of the third amplifier AMP 3; a first connection end of the first adjustable resistor RV1 is connected with a second connection end of the first current source I1 and a positive phase input end of the first amplifier AMP1, and a second connection end thereof is connected with a ground end GND; a first connecting end of the second adjustable resistor RV2 is connected with a second connecting end of the second current source I2 and an inverting input end of the third amplifier AMP3, and a second connecting end thereof is connected with a ground end GND; the inverting input end of the first amplifier AMP1 is connected with the output end of the first amplifier AMP1, the non-inverting input end of the first amplifier AMP1 is connected with the first connection end of the first adjustable resistor RV1 and the second connection end of the first current source I1, and the output end of the first amplifier AMP1 is connected with the first connection end of the first resistor R1; the inverting input end of the second amplifier AMP2 is connected to the second connection end of the fifth resistor R5 and the first connection end of the sixth resistor R6, the non-inverting input end is connected to the second connection end of the first resistor R1 and the first connection end of the second resistor R2, and the output end is connected to the gate of the first transistor M1 and the first connection end of the first capacitor C1; the inverting input end of the third amplifier AMP3 is connected to the second connection end of the second current source I2 and the first connection end of the second adjustable resistor RV2, the non-inverting input end is connected to the second connection end of the third resistor R3 and the second connection end of the fourth resistor R4, and the output end is connected to the gate of the second transistor M2 and the second connection end of the second capacitor C2; a first connection end of the first capacitor C1 is connected with the gate of the first transistor M1 and the output end of the second amplifier AMP2, and a second connection end is connected with the drain of the first transistor M1 and a first connection end of the seventh resistor R7; a first connection end of the second capacitor C2 is connected to the drain of the second transistor M2 and a second connection end of the seventh resistor R7, and the second connection end is connected to the gate of the second transistor M2 and the output end of the third amplifier AMP 3; the grid electrode of the first transistor M1 is connected with the first connection end of the first capacitor C1 and the output end of the second amplifier AMP2, the source electrode is connected with the power supply voltage VDD, and the drain electrode is used as the output port VA and is connected with the first connection end of the seventh resistor R7; the gate of the second transistor M2 is connected to the second connection terminal of the second capacitor C2 and the output terminal of the third amplifier AMP3, the source is connected to the ground GND, and the drain is used as the output port VB and connected to the second connection terminal of the seventh resistor R7; the first connection end of the first resistor R1 is connected with the output end of the first amplifier AMP1, and the second connection end of the first resistor R1 is connected with the first connection end of the second resistor R2; the first connection end of the second resistor R2 is connected with the second connection end of the first resistor R1 and the positive phase input end of the second amplifier AMP2, and the second connection end is connected with the first connection end of the third resistor R3 and the second connection end of the seventh resistor R7; a first connection end of the third resistor R3 is connected to a second connection end of the second resistor R2 and a second connection end of the seventh resistor R7, and the second connection end is connected to a second connection end of the fourth resistor R4 and a positive phase input end of the third amplifier AMP 3; a first connection end of the fourth resistor R4 is connected to a first connection end of the fifth resistor R5 and a first connection end of the seventh resistor R7, and a second connection end is connected to a second connection end of the third resistor R3 and a positive phase input end of the third amplifier AMP 3; a first connection end of the fifth resistor R5 is connected with a first connection end of the fourth resistor R4 and a first connection end of the seventh resistor R7, and a second connection end is connected with a first connection end of the sixth resistor R6 and an inverting input end of the second amplifier AMP 2; a first connection end of the sixth resistor R6 is connected with a second connection end of the fifth resistor R5 and the inverted input end of the second amplifier AMP2, and the second connection end is connected with a ground end GND; a first connecting end of the seventh resistor R7 is connected with the drain end of the first transistor M1 and the output port VA, and a second connecting end is connected with the drain end of the second transistor M2 and the output port VB; the first current source I1, the first adjustable resistor RV1, the second current source I2 and the second adjustable resistor RV2 generate two voltages V1 and V2 which change linearly along with the resistance value of the resistors, and finally a group of voltages VA and VB with adjustable differential mode ranges and common mode levels are output through a subsequent circuit network.
Fig. 1 is a voltage generating circuit with adjustable differential mode range and common mode level, wherein the resistances of the resistors are the same, the voltage drop across the first resistor R1 is Δ V1, and the voltage drop across the fourth resistor R4 is Δ V2, and we can list the following equations according to the schematic diagram of the circuit:
from the system of equations:
from this solution it can be derived that the resulting voltages VA and VB have a differential mode range equal to V1 and a common mode level equal to V2.
Specifically, V1 is generated by a first current source I1 and a first adjustable resistor RV1, and the adjustment of the differential mode range can be realized by adjusting the resistance value of the first adjustable resistor RV 1; v2 is produced by second current source I2 and second adjustable resistor RV2, and the adjustment of common mode level can be realized to the resistance of adjusting second adjustable resistor RV 2.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (1)
1. A voltage generating circuit with adjustable differential mode range and common mode level is characterized by comprising a first current source I1, a second current source I2, a first adjustable resistor RV1, a second adjustable resistor RV2, a first amplifier AMP1, a second amplifier AMP2, a third amplifier AMP3, a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7; wherein,
a first connection end of the first current source I1 is connected with a power supply voltage VDD, and a second connection end is connected with a first connection end of the first adjustable resistor RV1 and a positive phase input end of the first amplifier AMP 1;
a first connecting end of the second current source I2 is connected with the power supply voltage VDD, and a second connecting end is connected with a first connecting end of the second adjustable resistor RV2 and an inverting input end of the third amplifier AMP 3;
a first connection end of the first adjustable resistor RV1 is connected with a second connection end of the first current source I1 and a positive phase input end of the first amplifier AMP1, and a second connection end thereof is connected with a ground end GND;
a first connecting end of the second adjustable resistor RV2 is connected with a second connecting end of the second current source I2 and an inverting input end of the third amplifier AMP3, and a second connecting end thereof is connected with a ground end GND;
the inverting input end of the first amplifier AMP1 is connected with the output end of the first amplifier AMP1, the non-inverting input end of the first amplifier AMP1 is connected with the first connection end of the first adjustable resistor RV1 and the second connection end of the first current source I1, and the output end of the first amplifier AMP1 is connected with the first connection end of the first resistor R1;
the inverting input end of the second amplifier AMP2 is connected to the second connection end of the fifth resistor R5 and the first connection end of the sixth resistor R6, the non-inverting input end is connected to the second connection end of the first resistor R1 and the first connection end of the second resistor R2, and the output end is connected to the gate of the first transistor M1 and the first connection end of the first capacitor C1;
the inverting input end of the third amplifier AMP3 is connected to the second connection end of the second current source I2 and the first connection end of the second adjustable resistor RV2, the non-inverting input end is connected to the second connection end of the third resistor R3 and the second connection end of the fourth resistor R4, and the output end is connected to the gate of the second transistor M2 and the second connection end of the second capacitor C2;
a first connection end of the first capacitor C1 is connected with the gate of the first transistor M1 and the output end of the second amplifier AMP2, and a second connection end is connected with the drain of the first transistor M1 and a first connection end of the seventh resistor R7;
a first connection end of the second capacitor C2 is connected to the drain of the second transistor M2 and a second connection end of the seventh resistor R7, and the second connection end is connected to the gate of the second transistor M2 and the output end of the third amplifier AMP 3;
a grid electrode of the first transistor M1 is connected with a first connecting end of the first capacitor C1 and an output end of the second amplifier AMP2, a source electrode is connected with a power supply voltage VDD, and a drain electrode is used as a first output port and is connected with a first connecting end of the seventh resistor R7;
the gate of the second transistor M2 is connected to the second connection terminal of the second capacitor C2 and the output terminal of the third amplifier AMP3, the source is connected to the ground GND, and the drain is used as the second output port and connected to the second connection terminal of the seventh resistor R7;
the first connection end of the first resistor R1 is connected with the output end of the first amplifier AMP1, and the second connection end of the first resistor R1 is connected with the first connection end of the second resistor R2;
the first connection end of the second resistor R2 is connected with the second connection end of the first resistor R1 and the non-inverting input end of the second amplifier AMP2, and the second connection end is connected with the first connection end of the third resistor R3 and the second connection end of the seventh resistor R7;
a first connection end of the third resistor R3 is connected to a second connection end of the second resistor R2 and a second connection end of the seventh resistor R7, and the second connection end is connected to a second connection end of the fourth resistor R4 and a positive phase input end of the third amplifier AMP 3;
a first connection end of the fourth resistor R4 is connected to a first connection end of the fifth resistor R5 and a first connection end of the seventh resistor R7, and a second connection end is connected to a second connection end of the third resistor R3 and a positive phase input end of the third amplifier AMP 3;
the first connection end of the fifth resistor R5 is connected with the first connection end of the fourth resistor R4 and the first connection end of the seventh resistor R7, and the second connection end is connected with the first connection end of the sixth resistor R6 and the inverting input end of the second amplifier AMP 2;
a first connection end of the sixth resistor R6 is connected with a second connection end of the fifth resistor R5 and the inverted input end of the second amplifier AMP2, and the second connection end is connected with a ground end GND;
a first connection end of the seventh resistor R7 is connected to the drain end of the first transistor M1 and the output port VA, and a second connection end is connected to the drain end of the second transistor M2 and the output port VB.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211515654.9A CN115840487A (en) | 2022-11-30 | 2022-11-30 | Voltage generation circuit with adjustable differential mode range and common mode level |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211515654.9A CN115840487A (en) | 2022-11-30 | 2022-11-30 | Voltage generation circuit with adjustable differential mode range and common mode level |
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| CN115840487A true CN115840487A (en) | 2023-03-24 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030174023A1 (en) * | 2002-03-12 | 2003-09-18 | Tokio Miyasita | Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier |
| CN202795113U (en) * | 2012-09-12 | 2013-03-13 | 无锡华润矽科微电子有限公司 | Motor drive circuit structure for automatically adjusting output voltage |
| CN115291662A (en) * | 2022-08-02 | 2022-11-04 | 西安交通大学 | Threshold voltage generation circuit with adjustable range |
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2022
- 2022-11-30 CN CN202211515654.9A patent/CN115840487A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030174023A1 (en) * | 2002-03-12 | 2003-09-18 | Tokio Miyasita | Analog summing and differencing circuit, optical receiving circuit, optical transmitting circuit, automatic gain control amplifier, automatic frequency compensation amplifier, and limiting amplifier |
| CN202795113U (en) * | 2012-09-12 | 2013-03-13 | 无锡华润矽科微电子有限公司 | Motor drive circuit structure for automatically adjusting output voltage |
| CN115291662A (en) * | 2022-08-02 | 2022-11-04 | 西安交通大学 | Threshold voltage generation circuit with adjustable range |
Non-Patent Citations (1)
| Title |
|---|
| 杨国超: "Buck变换器建模与非线性控制方法研究", 中国优秀硕士学位论文全文数据库 (工程科技Ⅱ辑), pages 042 - 97 * |
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Application publication date: 20230324 |