CN115776102A - ESD protection circuit of driving chip - Google Patents
ESD protection circuit of driving chip Download PDFInfo
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- CN115776102A CN115776102A CN202310092121.2A CN202310092121A CN115776102A CN 115776102 A CN115776102 A CN 115776102A CN 202310092121 A CN202310092121 A CN 202310092121A CN 115776102 A CN115776102 A CN 115776102A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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Abstract
The invention relates to the technical field of integrated circuit ESD protection, and particularly discloses an ESD protection circuit of a driving chip, which comprises a clamping protection circuit, a resistor R resistance value adjusting circuit and a chip working state detection circuit, wherein the clamping protection circuit is electrically connected with the resistor R resistance value adjusting circuit, and the chip working state detection circuit is used for controlling the resistor R adjusting circuit; the invention selects proper RC time constant by detecting the working state of the chip through the chip working state detection circuit, thereby ensuring that the chip keeps good ESD performance under the condition of no power-on or power-on standby.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an ESD protection circuit of a driving chip.
Background
Electrostatic discharge, ESD, refers to the transfer of electrostatic charge between objects at different potentials due to direct contact or electrostatic induction. With the electrostatic discharge, there is often a transfer of electrical quantity and a generation of current. The material from which integrated circuit chips are fabricated is a semiconductor material, typically silicon, which when subjected to an ESD event generates excessive thermal energy that can cause permanent damage to the silicon material. Thereby affecting the normal use of the chip and therefore making ESD protection of the chip very necessary.
In order to prevent electrostatic discharge (ESD) from damaging the chip, the ESD protection circuit provides an ESD current discharge path to prevent current from flowing into the internal circuit of the chip and causing damage during ESD discharge. As shown in fig. 3, when an ESD voltage appears between the power supply and the ground, a transient positive pulse voltage is generated at the gate of the node NM2 by utilizing the characteristic of the extreme speed change of the ESD discharge transient voltage, so that the large-sized NMOS transistor NM2 is turned on to discharge the ESD current.
When the driving chip drives a high-power load, because parasitic inductance exists in chip binding wires and PCB wiring, when the edge of a clock signal jumps, peak voltage can be generated on a power supply inside the chip, which is similar to the situation of ESD discharging transient voltage, and an ESD protection circuit cannot distinguish the ESD discharging transient voltage or the peak voltage in normal working, but when the driving chip works normally, peak voltage can be generated on each clock edge power supply, so that each clock edge ESD protection circuit can generate peak discharge current, and the power consumption of the chip is obviously increased. In order to solve the problem that the ESD protection circuit of the driver chip leaks electricity during normal operation, there are two general solutions: first, various measures are taken to reduce the peak voltage on the power supply, leaving it from triggering the ESD protection circuit. For example, a package method with short binding wires is adopted, and a large filter capacitor is added between a power supply and the ground inside a chip, which results in an increase in chip area and an increase in package cost. And secondly, the discharge threshold voltage of the ESD protection circuit is improved, and the power consumption performance of the chip is ensured by reducing the protection level of the ESD. Therefore, a solution that is low in cost and does not reduce the ESD protection level is needed to solve the above-mentioned existing problems of the driver chip.
Disclosure of Invention
The invention aims to provide an ESD protection circuit of a driving chip, which can ensure that the chip keeps good ESD performance under the condition of no power-on or power-on standby by detecting the working state of the chip through a chip working state detection circuit to select a proper RC time constant, and can prevent the chip from leaking electricity due to the ESD protection circuit by improving the discharge threshold voltage of the ESD protection circuit when the chip works normally. The chip cost is saved, and meanwhile, the probability that the chip is damaged by ESD is greatly reduced, so that the problems in the background technology are solved.
In order to achieve the purpose, the invention adopts the following technical scheme:
the ESD protection circuit of the driving chip comprises a clamping protection circuit, a resistor R resistance value adjusting circuit and a chip working state detection circuit, wherein the clamping protection circuit is electrically connected with the resistor R resistance value adjusting circuit, and the chip working state detection circuit is used for controlling the resistor R resistance value adjusting circuit.
The chip working state detection circuit comprises a power supply voltage detection circuit, a clock signal starting and ending detection circuit and an RS latching logic circuit, wherein the clock signal starting and ending detection circuit is connected with the RS latching logic circuit;
the clamp protection circuit comprises a resistor capacitor RC, a source electrode follower and an ESD discharge tube, wherein the resistor capacitor RC is electrically connected with the source electrode follower, and the source electrode follower is electrically connected with the ESD discharge tube.
Preferably, the resistor-capacitor RC includes a capacitor C and resistors R1 and R2, the resistors R1 and R2 are connected in series to the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM1 is connected to the connection end of the capacitor C and the resistor R1.
Preferably, the source electrode follower comprises an NMOS (N-channel metal oxide semiconductor) tube NM1, a resistor R3 and a resistor R4, wherein the resistor R3 and the resistor R4 are connected in series with a source electrode of the NMOS tube NM1, the ESD discharge tube is an NMOS tube NM2, a grid electrode of the NMOS tube NM2 is connected with the source electrode of the NMOS tube NM1 and the resistor R3, and a drain electrode of the NMOS tube NM2 and a drain electrode of the NMOS tube NM1 are connected to a power supply VDD.
Preferably, the resistance value adjusting circuit of the resistor R comprises a control switch tube NM3 and a switch tube NM4, the drain electrode and the source electrode of the switch tube NM3 are respectively connected to two ends of the resistor R2, the drain electrode and the source electrode of the switch tube NM4 are respectively connected to two ends of the resistor R4, and grid electrodes of the switch tube NM3 and the switch tube NM4 are connected to the sw _ esd node.
Preferably, when an ESD voltage appears between the chip power supply and the ground, the capacitor C is coupled to generate a transient positive pulse voltage Vg1, and then a source follower composed of the NMOS transistor NM1, the resistor R3, and the resistor R4 generates a transient positive pulse voltage Vg2 to drive the large-sized NMOS transistor NM2 to be turned on to discharge the ESD current.
Preferably, when the switch tube NM3 and the switch tube NM4 are disconnected, the RC time constant is large, the duration time of the transient positive pulses Vg1 and Vg2 is long, the on time of the NMOS tube NM2 is long, and the ESD current is quickly discharged; when the switch tube NM3 and the switch tube NM4 are closed, the resistor R2 and the resistor R4 are bypassed to the ground by the switch, the RC time constant is reduced, the duration time of transient positive pulses Vg1 and Vg2 is short, the conduction time of the NMOS tube NM2 is short, and ESD current is discharged slowly.
Preferably, the clock signal start and end detection circuit is provided with a sig pin, a sig _ stop node and a sig _ str node, the sig _ stop node and the sig _ str node are both connected with the RS latch logic circuit, and the sig pin is a clock input pin of the driving chip.
Preferably, the power supply voltage detection circuit is provided with a ven node, and when the chip is not powered on or the power supply voltage does not reach the normal voltage working range, the ven node is 0, so that the node sw _ ESD signal is 0, the switching tube NM3 and the switching tube NM4 are controlled to be disconnected, and the RC time constant of ESD is large.
Preferably, when the power supply voltage of the chip is normally powered on, the ven node is 1, the sw _ ESD signal of the node is controlled by the clock signal start and end detection circuit, when the sig pin has no clock signal, the sig _ stop node is 1, the sig _ str node is 0, and after the RS latch logic circuit, the sw _ ESD signal of the node is 0, so that the switching tube NM3 and the switching tube NM4 are controlled to be disconnected, and the RC time constant of ESD is large; when the sig pin has a clock signal, the sig _ stop node is 0, the sig _ str node is 1, after the RS latch logic circuit, the node sw _ ESD signal is 1, the switch tube NM3 and the switch tube NM4 are controlled to be closed, and the RC constant of ESD is small at the moment.
Preferably, the chip working state detection circuit selects a proper RC time constant by detecting the working state of the chip, so that the chip is ensured to keep good ESD performance under the condition of no power-on or power-on standby, and the chip is prevented from electric leakage caused by the ESD protection circuit by improving the discharge threshold voltage of the ESD protection circuit in a normal working mode of the chip.
Compared with the prior art, the ESD protection circuit of the driving chip provided by the invention has the following advantages:
according to the invention, the clamping protection circuit, the resistor R resistance value adjusting circuit and the chip working state detection circuit are matched, and the chip working state detection circuit is used for detecting the working state of the chip to select a proper RC time constant, so that the chip is ensured to keep good ESD performance under the condition of no power-on or power-on standby.
Drawings
FIG. 1 is a circuit diagram of the chip operation status detection circuit of the present invention;
FIG. 2 is a circuit diagram of a clamp protection circuit and a resistance value adjusting circuit of a resistor R according to the present invention;
fig. 3 is a circuit diagram of a conventional ESD protection circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The specific embodiments described herein are merely illustrative of the invention and do not delimit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides an ESD protection circuit of a driving chip as shown in figures 1-2, which comprises a clamping protection circuit, a resistor R resistance value adjusting circuit and a chip working state detection circuit, wherein the clamping protection circuit is electrically connected with the resistor R resistance value adjusting circuit, and the chip working state detection circuit is used for controlling the resistor R resistance value adjusting circuit.
The clamp protection circuit comprises a resistor capacitor RC, a source electrode follower and an ESD discharge tube, wherein the resistor capacitor RC is electrically connected with the source electrode follower, and the source electrode follower is electrically connected with the ESD discharge tube.
Resistance capacitance RC includes electric capacity C and resistance R1, R2, resistance R1 and R2 establish ties at NMOS pipe NM 1's grid, just NMOS pipe NM 1's grid is connected with electric capacity C and resistance R1's link.
The source electrode follower comprises an NMOS (N-channel metal oxide semiconductor) tube NM1, a resistor R3 and a resistor R4, wherein the resistor R3 and the resistor R4 are connected in series at the source electrode of the NMOS tube NM1, the ESD release tube is an NMOS tube NM2, the grid electrode of the NMOS tube NM2 is connected with the source electrode of the NMOS tube NM1 and the resistor R3, and the drain electrode of the NMOS tube NM2 and the drain electrode of the NMOS tube NM1 are connected to a power supply VDD.
The resistance value adjusting circuit of the resistor R comprises a control switch tube NM3 and a switch tube NM4, the drain electrode and the source electrode of the switch tube NM3 are connected to two ends of the resistor R2 respectively, the drain electrode and the source electrode of the switch tube NM4 are connected to two ends of the resistor R4 respectively, and grid electrodes of the switch tube NM3 and the switch tube NM4 are connected to a sw _ esd node.
When an ESD voltage appears between a power supply and the ground, the capacitor C is coupled to generate a transient positive pulse voltage Vg1, and then a source follower consisting of an NMOS tube NM1, a resistor R3 and a resistor R4 generates a transient positive pulse voltage Vg2 to drive a large-size NMOS tube NM2 to be conducted to discharge the ESD current. The duration of the transient positive pulse voltage Vg1 can be changed by adjusting the resistances of the resistor R1 and the resistor R2, the duration of the transient positive pulse voltage Vg2 can be changed by adjusting the resistances of the resistor R3 and the resistor R4, and the conduction time of the NMOS tube NM2 is determined by the pulse width of the Vg2, so that the discharge capacity of ESD current is determined.
When the switch tube NM3 and the switch tube NM4 are disconnected, the RC time constant is large, the duration time of transient positive pulses Vg1 and Vg2 is long, the on-time of the NMOS tube NM2 is long, ESD current is quickly discharged, the ESD performance is improved, and meanwhile, the transient positive pulses are easily triggered by power supply peak voltage generated during working to cause electric leakage; when switch tube NM3 and switch tube NM4 are closed, resistance R2 and resistance R4 are by-passed to ground by the switch, RC time constant diminishes, transient positive pulse Vg1 and Vg 2's duration is short, NMOS pipe NM2 on-time is short, ESD current discharges slowly, when the power peak voltage that produces when the during operation makes transient positive pulse Vg2 be less than NMOS pipe NM 2's opening threshold voltage, just there will not be the electric leakage, but ESD protection level performance can descend simultaneously.
The chip working state detection circuit comprises a power supply voltage detection circuit, a clock signal starting and ending detection circuit and an RS latching logic circuit, wherein the clock signal starting and ending detection circuit is connected with the RS latching logic circuit;
the clock signal starting and ending detection circuit is provided with a sig pin, a sig _ stop node and a sig _ str node, the sig _ stop node and the sig _ str node are both connected with the RS latching logic circuit, and the sig pin is a driving chip clock signal input pin.
The power supply voltage detection circuit is provided with a ven node, when the chip is not powered on or the power supply voltage does not reach the normal voltage working range, the ven node is 0, so that a node sw _ ESD signal is 0, the switching tube NM3 and the switching tube NM4 are controlled to be disconnected, at the moment, the ESD RC time constant is large, and the ESD performance is good; when the power supply voltage of the chip is normally powered on, the ven node is 1, the node sw _ ESD signal is controlled by a clock signal start and end detection circuit, as shown in fig. 1, when the sig pin has no clock signal, the sig _ stop node is 1, the sig _ str node is 0, and after passing through the RS latch logic circuit, the node sw _ ESD signal is 0, so that the switching tube NM3 and the switching tube NM4 are controlled to be disconnected, at this time, the RC time constant of ESD is large, and the ESD performance is good; when the sig pin has a clock signal, the sig _ stop node is 0, the sig _ str node is 1, after the signal passes through the RS latch logic circuit, the node sw _ ESD signal is 1, the switch tube NM3 and the switch tube NM4 are controlled to be closed, the RC constant of ESD is small at the moment, and the ESD performance is reduced.
Static electricity is a natural phenomenon, and is usually generated by contact, friction and the like, and the damage of a chip by ESD is random, and may occur in the processes of production, packaging, testing, transportation, mounting, use and the like. In the whole process, the chip is in a state of no power-on or power-on standby for most of time. The ESD protection circuit is designed into two groups of different RC time constants, the chip working state detection circuit selects a proper RC time constant by detecting the working state of the chip, so that the chip is ensured to keep good ESD performance under the condition of no power-on or power-on standby, the chip is prevented from electric leakage caused by the ESD protection circuit by improving the discharge threshold voltage of the ESD protection circuit in a normal working mode of the chip, the cost of the chip is saved, and the probability of damaging the chip by ESD is greatly reduced.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still make modifications to the technical solutions described in the foregoing embodiments, or make equivalent substitutions and improvements to part of the technical features of the foregoing embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An ESD protection circuit of a driving chip is characterized in that: the circuit comprises a clamping protection circuit, a resistor R resistance value adjusting circuit and a chip working state detection circuit, wherein the clamping protection circuit is electrically connected with the resistor R resistance value adjusting circuit;
the chip working state detection circuit comprises a power supply voltage detection circuit, a clock signal starting and ending detection circuit and an RS latching logic circuit, wherein the clock signal starting and ending detection circuit is connected with the RS latching logic circuit;
the clamp protection circuit comprises a resistor capacitor RC, a source electrode follower and an ESD discharge tube, wherein the resistor capacitor RC is electrically connected with the source electrode follower, and the source electrode follower is electrically connected with the ESD discharge tube.
2. The ESD protection circuit of driver chip according to claim 1, wherein: resistance capacitance RC includes electric capacity C and resistance R1, R2, resistance R1 and R2 establish ties at NMOS pipe NM 1's grid, just NMOS pipe NM 1's grid is connected with electric capacity C and resistance R1's link.
3. The ESD protection circuit for driver chip of claim 2, wherein: the source electrode follower comprises an NMOS (N-channel metal oxide semiconductor) tube NM1, a resistor R3 and a resistor R4, wherein the resistor R3 and the resistor R4 are connected in series at the source electrode of the NMOS tube NM1, the ESD discharge tube is an NMOS tube NM2, the grid electrode of the NMOS tube NM2 is connected with the source electrode of the NMOS tube NM1 and the resistor R3, and the drain electrode of the NMOS tube NM2 and the drain electrode of the NMOS tube NM1 are connected to a power supply VDD.
4. The ESD protection circuit for driver chip of claim 2, wherein: the resistance value adjusting circuit of the resistor R comprises a control switch tube NM3 and a switch tube NM4, the drain electrode and the source electrode of the switch tube NM3 are connected to two ends of the resistor R2 respectively, the drain electrode and the source electrode of the switch tube NM4 are connected to two ends of the resistor R4 respectively, and grid electrodes of the switch tube NM3 and the switch tube NM4 are connected to a sw _ esd node.
5. The ESD protection circuit of the driver chip according to claim 4, wherein: when ESD voltage appears between a chip power supply and the ground, the capacitor C is coupled to generate a transient positive pulse voltage Vg1, and then a source follower consisting of an NMOS tube NM1, a resistor R3 and a resistor R4 generates a transient positive pulse voltage Vg2 to drive a large-size NMOS tube NM2 to be conducted to discharge ESD current.
6. The ESD protection circuit of the driver chip according to claim 5, wherein: when the switch tube NM3 and the switch tube NM4 are disconnected, the RC time constant is large, the duration time of transient positive pulses Vg1 and Vg2 is long, the conduction time of the NMOS tube NM2 is long, and ESD current is discharged quickly; when the switch tube NM3 and the switch tube NM4 are closed, the resistor R2 and the resistor R4 are bypassed to the ground by the switch, the RC time constant is reduced, the duration time of the transient positive pulse Vg1 and Vg2 is short, the conduction time of the NMOS tube NM2 is short, and ESD current is discharged slowly.
7. The ESD protection circuit of the driver chip according to claim 6, wherein: the clock signal starting and ending detection circuit is provided with a sig pin, a sig _ stop node and a sig _ str node, the sig _ stop node and the sig _ str node are both connected with the RS latching logic circuit, and the sig pin is a driving chip clock signal input pin.
8. The ESD protection circuit of driver chip according to claim 7, wherein: the power supply voltage detection circuit is provided with a ven node, when the chip is not powered on or the power supply voltage does not reach the normal voltage working range, the ven node is 0, so that the node sw _ ESD signal is 0, the switch tube NM3 and the switch tube NM4 are controlled to be disconnected, and the RC time constant of ESD is large.
9. The ESD protection circuit for driver chip according to claim 8, wherein:
when the power supply voltage of the chip is normally electrified, the ven node is 1, the sw _ ESD signal of the node is controlled by a clock signal start and end detection circuit, when the sig pin has no clock signal, the sig _ stop node is 1, the sig _ str node is 0, and after the RS latch logic circuit, the sw _ ESD signal of the node is 0, so that the switching tube NM3 and the switching tube NM4 are controlled to be disconnected, and the RC time constant of ESD is large; when the sig pin has a clock signal, the sig _ stop node is 0, the sig _ str node is 1, after the RS latch logic circuit, the node sw _ ESD signal is 1, the switch tube NM3 and the switch tube NM4 are controlled to be closed, and the RC constant of ESD is small at the moment.
10. The ESD protection circuit for driver chip of claim 1, wherein: the chip working state detection circuit selects a proper RC time constant by detecting the working state of the chip, thereby ensuring that the chip keeps good ESD performance under the condition of no power-on or power-on standby, and under the normal working mode of the chip, the chip can not leak electricity due to the ESD protection circuit by improving the discharge threshold voltage of the ESD protection circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310092121.2A CN115776102B (en) | 2023-02-10 | 2023-02-10 | ESD protection circuit of driving chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310092121.2A CN115776102B (en) | 2023-02-10 | 2023-02-10 | ESD protection circuit of driving chip |
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| CN115776102A true CN115776102A (en) | 2023-03-10 |
| CN115776102B CN115776102B (en) | 2023-04-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117613834A (en) * | 2023-11-23 | 2024-02-27 | 上海类比半导体技术有限公司 | Ultra-low leakage ESD protection circuit and chip |
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2023
- 2023-02-10 CN CN202310092121.2A patent/CN115776102B/en active Active
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| US20150077890A1 (en) * | 2013-09-17 | 2015-03-19 | Megachips Corporation | Esd protection circuit |
| US20150280415A1 (en) * | 2014-03-27 | 2015-10-01 | Texas Instruments Incorporated | Logging esd events |
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| CN115776102B (en) | 2023-04-28 |
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