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CN115459578B - Output clamping protection module, method, chip and driving protection system - Google Patents

Output clamping protection module, method, chip and driving protection system Download PDF

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Publication number
CN115459578B
CN115459578B CN202211138899.4A CN202211138899A CN115459578B CN 115459578 B CN115459578 B CN 115459578B CN 202211138899 A CN202211138899 A CN 202211138899A CN 115459578 B CN115459578 B CN 115459578B
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CN
China
Prior art keywords
tube
nmos tube
nmos
resistor
output
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CN202211138899.4A
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Chinese (zh)
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CN115459578A (en
Inventor
王青松
李妍
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention provides an output clamping protection module, an output clamping protection method, a chip and a driving protection system, which comprise the following steps: the first NMOS tube and the second NMOS tube are connected in series; the first resistor is connected between the output end and the grid electrode of the second NMOS tube; the first PMOS tube and the current-limiting anti-reflection unit are connected in series between the output end and the grid electrode of the second NMOS tube; the clamp control unit generates a control signal of the first PMOS tube based on the voltage detection signal, and when the power supply voltage is powered down or undervoltage, the first PMOS tube is turned on, and when the power supply voltage is normal, the first PMOS tube is turned off. According to the invention, when the power supply is under-voltage, the gate potential of the second NMOS tube is quickly raised by the passage, so that the drain and source of the second NMOS tube are conducted, the gate potential of the sixth NMOS tube is lowered, and the sixth NMOS tube cannot be conducted to form a short circuit passage from the bus voltage to the ground; and meanwhile, the power supply voltage is recovered to normally back out of operation, so that the normal operation of the circuit is not influenced.

Description

Output clamping protection module, method, chip and driving protection system
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to an output clamp protection module, method, chip, and drive protection system.
Background
Fig. 1 shows a circuit for driving and controlling MOS transistors by using a conventional driving chip, which includes a driving chip 1 and external power NMOS transistors (Q1 and Q2). When the gate-source voltage of the external power NMOS transistor Q2 is larger than the threshold voltage, namely the conduction condition of the MOS transistor is achieved, the drain-source of the external power NMOS transistor Q2 is conducted. The drain electrode of the external power NMOS tube Q1 is connected with a bus voltage VBUS (generally about 600V), the grid electrode of the external power NMOS tube Q1 is connected with a grid control signal G1, the source electrode of the external power NMOS tube Q1 is connected with the drain electrode of the external power NMOS tube Q2, and the connection point is a switch node E; the output end of the driving chip 1 is connected with the grid electrode of the external power NMOS tube Q2 and drives the grid electrode of the external power NMOS tube Q2. When the external power NMOS transistor Q1 is just driven on, the voltage at the switching node E starts to increase rapidly from 0V. When the driving chip 1 is not electrified, because parasitic capacitance Cgd exists between the grid electrode and the drain electrode of the external power NMOS tube Q2, the rapidly rising voltage of the switch node E charges the grid electrode of the external power NMOS tube Q2 through the parasitic capacitance Cgd, so that the grid source voltage of the external power NMOS tube Q2 is larger than the threshold voltage of the external power NMOS tube Q2, the drain source of the external power NMOS tube Q2 is conducted, a short circuit path from the bus voltage VBUS to the ground is formed, and even the frying machine is damaged due to overheating if the short circuit path is not limited.
Therefore, how to clamp the gate of the external power NMOS Q2 and improve the safety of the circuit is one of the technical problems to be solved by those skilled in the art.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention is directed to an output clamp protection module, an output clamp protection method, a chip and a drive protection system, which are used for solving the problems of overheat damage and even frying caused by simultaneous conduction of power NMOS transistors when the drive chip is not powered on in the prior art.
To achieve the above and other related objects, the present invention provides an output clamp protection module applied to a driving circuit, the output clamp protection module at least includes:
The device comprises a first NMOS tube, a second NMOS tube, a first resistor, a first PMOS tube, a current-limiting anti-reflection unit and a clamping control unit;
The drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and used as the output end of the output clamping protection module to output a driving signal;
The grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded;
one end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube;
the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reflection unit;
The second end of the current-limiting anti-reflection unit is connected with the grid electrode of the second NMOS tube and is used for limiting the magnitude of current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube;
The clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, and turns on the first PMOS tube when the power supply voltage is powered down or is undervoltage, and turns off the first PMOS tube when the power supply voltage is normal.
Optionally, the current-limiting anti-reflection unit comprises a diode and a second resistor connected in series, and the second resistor is used for current-limiting protection of the diode.
Optionally, the output clamp protection module further includes a first voltage stabilizing tube, an anode of the first voltage stabilizing tube is connected to a gate of the first PMOS tube, and a cathode of the first voltage stabilizing tube is connected to a source of the first PMOS tube.
Optionally, the clamp control unit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a second PMOS transistor, a third resistor, and a fourth resistor;
The source electrode of the third NMOS tube is grounded, the grid electrode is connected with the voltage detection signal, and the drain electrode is connected with the source electrode of the first PMOS tube through the third resistor;
The source electrode of the fourth NMOS tube is grounded, the grid electrode is connected with the voltage detection signal, and the drain electrode is connected with the source electrode of the first PMOS tube through the fourth resistor;
The source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the second PMOS tube and outputs the control signal of the first PMOS tube;
and the grid electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube.
More optionally, the clamp control unit further includes a fifth resistor and a sixth resistor;
The fifth resistor is connected between the drain electrode of the fourth NMOS tube and the grid electrode of the second PMOS tube, the sixth resistor is connected between the drain electrode of the fifth NMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube outputs the control signal of the first PMOS tube.
More optionally, the clamp control unit further includes a second voltage regulator tube and a third voltage regulator tube;
The anode of the second voltage stabilizing tube is grounded, and the cathode of the second voltage stabilizing tube is connected with the grid electrode of the fifth NMOS tube; and the anode of the third voltage stabilizing tube is connected with the grid electrode of the second PMOS tube, and the cathode of the third voltage stabilizing tube is connected with the source electrode of the second PMOS tube.
Optionally, the first resistance is set to be 500k ohms or more.
To achieve the above and other related objects, the present invention provides a chip including at least the above output clamp protection module.
To achieve the above and other related objects, the present invention provides a drive protection system including at least:
a driving circuit and a half-bridge circuit;
The driving circuit comprises a driving control module and the output clamping protection module, and is used for providing a driving signal with clamping characteristics; the driving control module provides a control signal for the output clamping protection module;
the half-bridge circuit is connected to the output end of the driving circuit and works based on the driving signal provided by the driving circuit; the half-bridge circuit comprises a sixth NMOS tube and a seventh NMOS tube; the source electrode of the sixth NMOS tube is grounded, the grid electrode is connected with the output end of the driving circuit, and the drain electrode is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with a third control signal, and the drain electrode of the seventh NMOS tube is connected with bus voltage; and the bus voltage is larger than the power supply voltage of the output clamping protection module.
To achieve the above and other related objects, the present invention provides an output clamp protection method, implemented based on the above-mentioned driving protection system, including at least:
under the conditions that the seventh NMOS tube is conducted and the power supply voltage of the output clamp protection module is powered off or undervoltage, the first PMOS tube is conducted, the grid potential of the second NMOS tube is pulled up by the first PMOS tube, the passage where the current-limiting anti-reflection unit is located and the passage where the first resistor is located, the second NMOS tube is conducted, a pull-down channel is provided for the grid of the sixth NMOS tube, and the sixth NMOS tube is turned off;
And under the condition that the power supply voltage of the output clamping protection module is normal, the first PMOS tube and the current-limiting anti-reflection unit are switched off.
Optionally, the current-limiting anti-reflection unit includes a diode and a second resistor connected in series, and when the difference between the gate potential of the sixth NMOS and the gate potential of the second NMOS is greater than or equal to the turn-on voltage of the diode, the gate potential of the second NMOS is pulled up by the first PMOS and the path where the current-limiting anti-reflection unit is located under the condition that the seventh NMOS is turned on and the power supply voltage of the output clamp protection module is powered down or under the condition that the power supply voltage of the output clamp protection module is under the undervoltage; when the difference between the gate potential of the sixth NMOS tube and the gate potential of the second NMOS tube is smaller than the starting voltage of the diode, the channel where the first PMOS tube and the current-limiting anti-reflection unit are located is not conducted, and the gate potential of the second NMOS tube is pulled up by the channel where the first resistor is located.
As described above, the output clamp protection module, the output clamp protection method, the output clamp protection chip and the drive protection system have the following beneficial effects:
According to the output clamping protection module, the method, the chip and the driving protection system, when the power supply is under-voltage, a passage is provided to quickly pull up the grid potential of the second NMOS tube, so that the drain source of the second NMOS tube is conducted, the grid potential of the sixth NMOS tube is pulled down, and the sixth NMOS tube cannot be conducted to form a short circuit passage from the bus voltage to the ground; and meanwhile, the power supply voltage is recovered to normally back out of operation, so that the normal operation of the circuit is not influenced.
The output clamping protection module is simple in structure, easy to realize and high in safety performance.
Drawings
Fig. 1 is a schematic circuit diagram of a driving chip driving control MOS transistor in the prior art.
Fig. 2 is a schematic circuit diagram of a driving chip with a pull-down protection function for driving and controlling a MOS transistor.
Fig. 3 is a schematic diagram of an output clamp protection module according to the present invention.
Fig. 4 is a schematic diagram of a driving protection system according to the present invention.
Description of element reference numerals
1. Driving chip
2. Output clamp protection module
21. Current-limiting anti-reverse unit
22. Clamping control unit
3. Driving circuit
4. Half-bridge circuit
5. Drive control module
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 2-4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In order to solve the problem that the power NMOS tube is simultaneously conducted, a resistor Ra is arranged in the driving chip 1 to raise the grid potential of the driving lower tube, and then the output potential is pulled down. As shown in fig. 2, the driving chip 1 mainly includes a power supply terminal VCC, a ground terminal VSS, NMOS transistors Q3 and Q4, and a resistor Ra. The drain electrode of the NMOS tube Q3 is connected with a power supply end VCC, the grid electrode is connected with a grid control signal G2, and the source electrode is connected with the drain electrode of the NMOS tube Q4 to serve as an output end OUT of the driving chip 1; the grid electrode of the NMOS tube Q4 is connected with a grid control signal G3, and the source electrode is grounded to the VSS; one end of the resistor Ra is connected with the output end OUT, and the other end of the resistor Ra is connected with the grid electrode of the NMOS tube Q4. When the external power NMOS transistor Q1 is just driven to be turned on, the rapidly rising voltage of the switch node E charges the gate of the external power NMOS transistor Q2 through the parasitic capacitor Cgd, the gate potential of the external power NMOS transistor Q2 is pulled up (i.e., the output terminal OUT potential of the driving chip 1 is pulled up), and then the gate potential of the NMOS transistor Q4 is pulled up through the resistor Ra, so that the gate-source voltage of the NMOS transistor Q4 is greater than the threshold voltage thereof, the drain-source of the NMOS transistor Q4 is turned on, a path from the output terminal OUT of the driving chip 1 to the ground VSS is formed, the gate potential of the external power NMOS transistor Q2 is pulled down to be below the threshold voltage thereof, and the external power NMOS transistor Q2 is turned off, thereby solving the short circuit path from the bus voltage formed by the drain-source conduction of the external power NMOS transistor Q2 to the ground.
As shown in fig. 2, if the resistor Ra is implemented with a small resistor, the pull-down speed is increased, but when the front-stage circuit (driving control circuit) inside the driving chip 1 drives the gate of the NMOS transistor Q4, the generated current flows from the gate of the NMOS transistor Q4 to the output terminal OUT of the driving chip 1, and there is an energy exchange between the OUT terminal and the gate of the NMOS transistor Q4, thereby increasing the power consumption of the driving chip 1. Therefore, the resistor Ra is generally implemented by a large resistor (for example, the resistance value of the resistor Ra is greater than or equal to 500k ohms), but the speed of the pull-down potential of the large resistor is correspondingly slowed down, and the pull-down time to the required potential is too long, so that the drain-source conduction time of the external power NMOS transistor Q2 is still long, and is generally greater than 10us; during this time, the surge current may still burn out the subsequent circuitry.
Based on the reasons, the invention provides an output clamping protection module, an output clamping protection method, a chip and a driving protection system, which further improve safety.
As shown in fig. 3, the present invention provides an output clamp protection module 2, the output clamp protection module 2 including:
The device comprises a first NMOS tube NM1, a second NMOS tube NM2, a first resistor R1, a first PMOS tube PM1, a current-limiting anti-reflection unit 21 and a clamp control unit 22.
As shown in fig. 3, the drain electrode of the first NMOS transistor NM1 is connected to the power supply voltage VCC, the gate electrode receives the first control signal CTL1, and the source electrode is connected to the drain electrode of the second NMOS transistor NM 2; the grid electrode of the second NMOS tube NM2 receives a second control signal CTL2, and the source electrode is grounded to VSS; the source electrode of the first NMOS transistor NM1 and the drain electrode of the second NMOS transistor NM2 serve as the output terminal OUT of the output clamp protection module 2, and output a driving signal of an external power transistor.
Specifically, in this embodiment, the working states of the first NMOS transistor NM1 and the second NMOS transistor NM2 are opposite; when the first NMOS tube NM1 is turned on, the second NMOS tube NM2 is turned off, so that a high-level driving signal is obtained; when the first NMOS tube NM1 is cut off, the second NMOS tube NM2 is conducted so as to obtain a low-level driving signal; control over the first NMOS transistor NM1 is implemented based on the first control signal CTL1, and control over the second NMOS transistor NM2 is implemented based on the second control signal CTL 2.
As shown in fig. 3, one end of the first resistor R1 is connected to the output terminal OUT of the output clamp protection module 2, and the other end is connected to the gate of the second NMOS transistor NM 2.
Specifically, the first resistor R1 is configured to provide a first pull-up path for the gate of the second NMOS transistor NM2, and current needs to be prevented from flowing from the gate of the second NMOS transistor NM2 to the output terminal OUT of the output clamp protection module 2; the resistance value of the first resistor R1 can be set to meet the above conditions; in this embodiment, the resistance value of the first resistor R1 is greater than or equal to 500K ohms, including but not limited to 510K ohms, 550K ohms, 570K ohms, 600K ohms, and 700K ohms, which may be set according to the needs in actual use, and is not limited to this embodiment.
As shown in fig. 3, the source of the first PMOS PM1 is connected to the output terminal OUT of the output clamp protection module 2, and the drain is connected to the first end of the current-limiting anti-reflection unit 21. The second end of the current limiting anti-reflection unit 21 is connected to the gate of the second NMOS transistor NM2, and is configured to limit the magnitude of the current flowing into the gate of the second NMOS transistor NM2, and prevent the current from flowing from the gate of the second NMOS transistor to the output end OUT of the output clamp protection module 2 through the first PMOS transistor PM 1.
Specifically, the first PMOS PM1 and the current limiting and anti-reflection unit 21 form a channel for providing a second pull-up channel for the gate of the second NMOS NM 2. In this embodiment, the current limiting anti-reflection unit 21 includes a diode D and a second resistor R2 connected in series, where the diode D is configured to prevent a current from flowing from the gate of the second NMOS transistor NM2 to the output terminal OUT of the output clamp protection module 2 through the first PMOS transistor PM1 and the current limiting anti-reflection unit 21 when the gate potential of the second NMOS transistor NM2 is higher than the potential of the output terminal OUT of the output clamp protection module 2; the second resistor R2 is configured to perform current limiting protection on the diode D to prevent the diode D from being burnt out due to excessive current, and the resistance value of the second resistor R2 is determined to be capable of protecting the diode D, which is not described in detail herein. As an example, the anode of the diode D is connected to the drain of the first PMOS PM1, and the cathode is connected to the second resistor R2; in practical use, the positions of the diode D and the second resistor R2 may be interchanged, so that the current-limiting anti-reflection function of the present invention may be implemented, which is not limited by the present embodiment.
As shown in fig. 3, the clamp control unit 22 receives a voltage detection signal UVB, generates a control signal of the first PMOS transistor PM1 based on the voltage detection signal UVB, turns on the first PMOS transistor PM1 when the power supply voltage VCC is powered down or is undervoltage, and turns off the first PMOS transistor PM1 when the power supply voltage VCC is normal.
Specifically, in the present embodiment, the clamp control unit 22 includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a second PMOS transistor PM2, a third resistor R3, and a fourth resistor R4. The source electrode of the third NMOS transistor NM3 is grounded GND, the gate electrode is connected to the voltage detection signal UVB, and the drain electrode is connected to the source electrode of the first PMOS transistor PM1 (i.e., the output terminal OUT of the output clamp protection module 2) via the third resistor R3. The source electrode of the fourth NMOS transistor NM4 is grounded GND, the gate electrode is connected to the voltage detection signal UVB, and the drain electrode is connected to the source electrode of the first PMOS transistor PM1 via the fourth resistor R4. The source electrode of the fifth NMOS tube NM5 is grounded GND, the grid electrode is connected with the drain electrode of the third NMOS tube NM3, and the drain electrode is connected with the drain electrode of the second PMOS tube PM2 and outputs the control signal of the first PMOS tube PM 1. And the grid electrode of the second PMOS tube PM2 is connected with the drain electrode of the fourth NMOS tube NM4, and the source electrode of the second PMOS tube PM1 is connected with the source electrode of the first PMOS tube PM 1.
More specifically, when the power supply voltage VCC is powered down or undervoltage, the voltage detection signal UVB is at a low level (as an example, uvb=0), the gate-source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are smaller than the threshold voltages thereof, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in an off state, and the current flowing through the third resistor R3 and the fourth resistor R4 is zero, and then the electric potentials at the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are equal to the electric potential of the output terminal OUT of the output clamp protection module 2; the gate-source voltage of the fifth NMOS transistor NM5 is greater than the threshold voltage thereof, so that the fifth NMOS transistor NM5 is in a conductive state; the gate-source voltage of the second PMOS tube PM2 is greater than the threshold voltage thereof, so that the second PMOS tube PM2 is in an off state, thereby enabling the first PMOS tube PM1 to be in an on state, and forming a path from the output terminal OUT of the output clamp protection module 2 to the gate of the second NMOS tube NM2 via the first PMOS tube PM1, the diode D, and the second resistor R2 in sequence. When the power supply voltage VCC is normal, the voltage detection signal UVB is at a high level (as an example, uvb=5v), the gate-source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are greater than the threshold voltages thereof, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are both in a conductive state, and the electric potentials at the drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are pulled down to be close to 0V; the gate-source voltage of the fifth NMOS transistor NM5 is less than the threshold voltage thereof, so that the fifth NMOS transistor NM5 is in an off state; the gate-source voltage of the second PMOS tube PM2 is smaller than the threshold voltage thereof, so the second PMOS tube PM2 is in an on state, the gate potential of the first PMOS tube PM1 is pulled up to be close to the potential of the output end OUT of the output clamp protection module 2, and the gate-source voltage of the first PMOS tube PM1 is larger than the threshold voltage thereof, so that the first PMOS tube PM1 is in an off state, and a path from the output end OUT of the output clamp protection module 2 to the gate of the second NMOS tube NM2 is not opened sequentially through the first PMOS tube PM1, the diode D, and the second resistor R2.
Specifically, as another implementation manner of the present invention, the clamping control unit 22 further includes a fifth resistor R5 and a sixth resistor R6. The fifth resistor R5 is connected between the drain of the fourth NMOS transistor NM4 and the gate of the second PMOS transistor PM2, the sixth resistor R6 is connected between the drain of the fifth NMOS transistor NM5 and the drain of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 outputs the control signal of the first PMOS transistor PM 1.
The resistors in the clamp control unit 22 serve as current limiting and level switching.
Specifically, as a further implementation manner of the present invention, the clamping control unit 22 further includes a second voltage stabilizing tube Dz2 and a third voltage stabilizing tube Dz3. The anode of the second voltage stabilizing tube Dz2 is grounded GND, and the cathode of the second voltage stabilizing tube Dz2 is connected with the grid electrode of the fifth NMOS tube NM 5; and the anode of the third voltage stabilizing tube Dz3 is connected with the grid electrode of the second PMOS tube PM2, and the cathode is connected with the source electrode of the second PMOS tube PM 2. The second voltage stabilizing tube Dz2 and the third voltage stabilizing tube Dz3 are used for protecting corresponding MOS tubes and limiting the voltage between the grid electrode and the source electrode so as to prevent the MOS tubes from being damaged due to high voltage caused by surge or other factors.
As shown in fig. 3, as an implementation manner of the present invention, the output clamp protection module 2 further includes a first voltage stabilizing tube Dz1, where an anode of the first voltage stabilizing tube Dz1 is connected to a gate of the first PMOS tube PM1, and a cathode of the first voltage stabilizing tube Dz1 is connected to a source of the first PMOS tube PM 1. The first voltage stabilizing tube Dz1 is used for protecting the first PMOS tube PM1 and preventing the first PMOS tube PM1 from being damaged by high voltage caused by surge or other factors.
The invention also provides a chip, which at least comprises the output clamping protection module 2, and other modules can be arranged according to the needs, and are not described in detail herein.
As shown in fig. 4, the present invention provides a drive protection system including: a driving circuit 3 and a half-bridge circuit 4.
As shown in fig. 4, the driving circuit 3 includes a driving control module 5 and the output clamp protection module 2, for providing a driving signal with a clamp characteristic; the drive control module 3 provides a control signal for the output clamp protection module 2.
Specifically, the driving control module 5 generates control signals (CTL 1 and CTL 2) of the first NMOS transistor NM1 and the second NMOS transistor NM2, wherein the control signals of the first NMOS transistor NM2 and the second NMOS transistor NM2 include, but are not limited to, PWM signals, and are set according to actual needs. When the power supply voltage VCC works normally, the output clamp protection module 2 generates a driving signal of the half-bridge circuit 4 based on a control signal provided by the driving control module 3; when the power supply voltage VCC is powered down or is undervoltage, the output clamping protection module 2 clamps an output terminal OUT of the output clamping protection module 2 based on a path formed by the first PMOS PM1 and the current limiting anti-reflection unit 21, and the first resistor R1.
As shown in fig. 4, the half-bridge circuit 4 is connected to the output terminal of the driving circuit 3, and operates based on the driving signal supplied from the driving circuit 3. The half-bridge circuit 4 includes a sixth NMOS transistor NM6 and a seventh NMOS transistor NM7; the source electrode of the sixth NMOS tube NM6 is grounded, the grid electrode is connected with the output end of the driving circuit 3, and the drain electrode is connected with the source electrode of the seventh NMOS tube NM7; the grid electrode of the seventh NMOS tube NM7 is connected with a third control signal CTL3, and the drain electrode is connected with a bus voltage VBUS; wherein the bus voltage VBUS is greater than the supply voltage VCC of the output clamp protection module 2.
Specifically, in this embodiment, the bus voltage VBUS is about 600V, the power supply voltage VCC of the output clamp protection module 2 is 8V to 24V, and in actual use, the values of the bus voltage VBUS and the power supply voltage VCC of the output clamp protection module 2 may be set as required, and as an example, the ratio of the bus voltage VBUS to the power supply voltage VCC of the output clamp protection module 2 is greater than or equal to 20 and less than or equal to 100.
It should be noted that the third control signal CTL3 may be provided by the driving circuit 3 or may be provided by other circuits, which are not described herein. In normal operation, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are not turned on at the same time.
The working principle of the driving protection system is as follows:
for an NMOS tube, when the voltage between the grid and the source, namely the grid source voltage, is larger than the threshold voltage, the drain and the source are conducted; wherein the gate-source voltage and the threshold voltage of the NMOS tube are both positive.
For the PMOS tube, when the voltage between the grid electrode and the source electrode, namely the grid source voltage is smaller than the threshold voltage, the drain electrode and the source electrode are conducted; the gate-source voltage and the threshold voltage of the PMOS tube are negative.
1) The seventh NMOS transistor NM7 is turned on and the power supply voltage VCC of the output clamp protection module 2 is powered down or is undervoltage: the first PMOS PM1 and the current limiting and anti-reflection unit 21 are on, the first PMOS PM1, the current limiting and anti-reflection unit 21, and the first resistor R1 pull up the gate potential of the second NMOS NM2, the second NMOS NM2 is on and provides a pull-down channel for the gate of the sixth NMOS NM6, and the sixth NMOS NM6 is off, so as to avoid the situation that the seventh NMOS NM7 and the sixth NMOS NM6 are on at the same time.
Specifically, when the seventh NMOS transistor NM7 is just driven to be turned on by the third control signal CTL3, the source voltage of the seventh NMOS transistor NM7 rapidly rises and charges the gate of the sixth NMOS transistor NM6 through the parasitic capacitance Cgd, and the gate potential of the sixth NMOS transistor NM6 is raised. The clamp control unit 22 controls the first PMOS PM1 to be turned on (i.e., the first PMOS PM1 and the current limiting and anti-reflection unit 21 are turned on), so that current flows from the output terminal OUT of the output clamp protection module 2 to the gate of the second NMOS NM2 via the first PMOS PM1 and the current limiting and anti-reflection unit 21, the gate potential of the second NMOS NM2 is quickly pulled up, the second NMOS NM2 is turned on, a pull-down path from the gate of the sixth NMOS NM6 to the ground VSS is formed (the gate potential of the sixth NMOS NM6 is quickly pulled down), the gate-source voltage of the sixth NMOS NM6 is smaller than the threshold voltage thereof, and the sixth NMOS is turned off. With the charging, the gate potential of the sixth NMOS NM6 is continuously increased, at this time, the paths of the first PMOS PM1 and the current limiting and anti-reflection unit 21 are kept in an on state, when the gate potential of the second NMOS NM2 is pulled up to be close to the gate potential of the sixth NMOS NM6, the gate potential difference between the gate potential of the sixth NMOS NM6 and the gate potential of the second NMOS NM2 does not reach the on voltage of the diode D, so that the paths of the first PMOS PM1 and the current limiting and anti-reflection unit 21 are not turned on, the paths of the first resistor R1 are continuously pulled up to be in an on state of the second NMOS NM2, and the gate potential of the sixth NMOS NM6 is pulled down to be in an off state of the sixth NMOS NM 6.
More specifically, in the present embodiment, when the difference between the gate potential of the sixth NMOS transistor NM6 and the gate potential of the second NMOS transistor NM2 is greater than 0.7V (the turn-on voltage of the diode D), the gate potential of the second NMOS transistor NM2 is pulled up by the path in which the first PMOS transistor PM1 and the current limiting and anti-reflection unit 21 are located; when the difference between the gate potential of the sixth NMOS transistor NM6 and the gate potential of the second NMOS transistor NM2 is within 0.7V (the difference is less than 0.7V, and the conduction condition of the diode D is not reached, so that the paths of the first PMOS transistor PM1 and the current limiting and anti-reflection unit 21 are not conducted), the gate potential of the second NMOS transistor NM2 is pulled up by the path of the first resistor R1. As an example, when the gate-source voltage of the sixth NMOS transistor NM6 is 2V, the drain-source is turned on, and the turn-on voltage drop of the diode is 0.7V, so that when the gate potential of the second NMOS transistor NM2 is less than or equal to 1.3V, the gate potential of the second NMOS transistor NM2 is quickly pulled up through the path where the first PMOS transistor PM1 and the current limiting and anti-reflection unit 21 are located; when the gate potential of the second NMOS transistor NM2 is greater than 1.3V, the gate potential of the second NMOS transistor NM2 is continuously pulled up by the path where the first resistor R1 is located.
2) The power supply voltage VCC of the output clamp protection module 2 is normal: the first PMOS PM1 and the current limiting and anti-reflection unit 21 are turned off.
Specifically, when the power supply voltage VCC of the output clamp protection module 2 is normal, the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are controlled by respective gate control signals, and the gate voltage of the sixth NMOS transistor NM6 is not pulled high to be conductive due to the parasitic capacitance Cgd (when the seventh NMOS transistor NM7 is conductive, there is a pull-down channel at the gate of the sixth NMOS transistor NM6, and the sixth NMOS transistor NM6 is not conductive). At this time, the paths of the first PMOS PM1 and the current limiting and anti-reflection unit 21 are turned off, and only the paths from the output terminal OUT of the output clamp protection module 2 to the gate of the second NMOS NM2 through the first resistor R1 are present; the second NMOS transistor NM2 is turned on or off under the control of the second control signal CTL 2; since the resistance value of the first resistor R1 is relatively large, the output terminal OUT of the output clamp protection module 2 has little influence on the gate potential of the second NMOS transistor NM2, and the output clamp protection module 2 works normally.
According to the output clamping protection module, the method, the chip and the driving protection system, when the power supply is undervoltage or power failure, the grid potential of the second NMOS tube is quickly pulled up, so that the drain-source conduction of the second NMOS tube forms a channel for quickly pulling down the potential of the output end OUT, the grid voltage of the sixth NMOS tube is lower than the threshold voltage and cannot be conducted, and the seventh NMOS tube and the sixth NMOS tube are prevented from being conducted simultaneously to form a short circuit channel from the bus voltage to the ground; the circuit is not adversely affected, and the working state of the chip when the power supply voltage is normal is not affected.
In summary, the present invention provides an output clamp protection module, method, chip and drive protection system, including: the device comprises a first NMOS tube, a second NMOS tube, a first resistor, a first PMOS tube, a current-limiting anti-reflection unit and a clamping control unit; the drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and used as the output end of the output clamping protection module to output a driving signal; the grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded; one end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube; the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reflection unit; the second end of the current-limiting anti-reflection unit is connected with the grid electrode of the second NMOS tube and is used for limiting the magnitude of current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube; the clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, and turns on the first PMOS tube when the power supply voltage is powered down or is undervoltage, and turns off the first PMOS tube when the power supply voltage is normal. According to the output clamping protection module, the method, the chip and the driving protection system, when the power supply is under-voltage, a passage is provided to quickly pull up the grid potential of the second NMOS tube, so that the drain source of the second NMOS tube is conducted, the grid potential of the sixth NMOS tube is pulled down, and the sixth NMOS tube cannot be conducted to form a short circuit passage from the bus voltage to the ground; and meanwhile, the power supply voltage is recovered to normally back out of operation, so that the normal operation of the circuit is not influenced. The output clamping protection module is simple in structure, easy to realize and high in safety performance. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A drive protection system, the drive protection system comprising at least:
a driving circuit and a half-bridge circuit;
the driving circuit comprises a driving control module and an output clamping protection module, and is used for providing a driving signal with clamping characteristics; the driving control module provides a control signal for the output clamping protection module;
the half-bridge circuit is connected to the output end of the driving circuit and works based on the driving signal provided by the driving circuit; the half-bridge circuit comprises a sixth NMOS tube and a seventh NMOS tube; the source electrode of the sixth NMOS tube is grounded, the grid electrode is connected with the output end of the driving circuit, and the drain electrode is connected with the source electrode of the seventh NMOS tube; the grid electrode of the seventh NMOS tube is connected with a third control signal, and the drain electrode of the seventh NMOS tube is connected with bus voltage; wherein the bus voltage is greater than the power supply voltage of the output clamp protection module;
Wherein, output clamp protection module includes: the device comprises a first NMOS tube, a second NMOS tube, a first resistor, a first PMOS tube, a current-limiting anti-reflection unit and a clamping control unit;
The drain electrode of the first NMOS tube is connected with a power supply voltage, the grid electrode receives a first control signal, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and used as the output end of the output clamping protection module to output a driving signal;
The grid electrode of the second NMOS tube receives a second control signal, and the source electrode of the second NMOS tube is grounded;
One end of the first resistor is connected with the output end of the output clamping protection module, and the other end of the first resistor is connected with the grid electrode of the second NMOS tube; the first resistor is used for providing a first pull-up path for the grid electrode of the second NMOS tube and preventing current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module;
the source electrode of the first PMOS tube is connected with the output end of the output clamping protection module, and the drain electrode of the first PMOS tube is connected with the first end of the current-limiting anti-reflection unit;
The second end of the current-limiting anti-reflection unit is connected with the grid electrode of the second NMOS tube and is used for limiting the magnitude of current flowing into the grid electrode of the second NMOS tube and preventing the current from flowing from the grid electrode of the second NMOS tube to the output end of the output clamping protection module through the first PMOS tube;
The clamping control unit receives a voltage detection signal, generates a control signal of the first PMOS tube based on the voltage detection signal, and turns on the first PMOS tube when the power supply voltage is powered down or under-voltage, and turns off the first PMOS tube when the power supply voltage is normal;
When the power supply voltage works normally, the output clamping protection module generates a driving signal of the half-bridge circuit based on a control signal provided by the driving control module; when the power supply voltage is powered down or under-voltage, the output clamping protection module clamps the output end of the output clamping protection module based on a passage formed by the first PMOS tube and the current-limiting anti-reflection unit and the first resistor.
2. The drive protection system of claim 1, wherein: the current-limiting anti-reflection unit comprises a diode and a second resistor which are connected in series, and the second resistor is used for current-limiting protection of the diode.
3. The drive protection system of claim 1, wherein: the output clamping protection module further comprises a first voltage stabilizing tube, wherein the anode of the first voltage stabilizing tube is connected with the grid electrode of the first PMOS tube, and the cathode of the first voltage stabilizing tube is connected with the source electrode of the first PMOS tube.
4. The drive protection system of claim 1, wherein: the clamping control unit comprises a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a second PMOS tube, a third resistor and a fourth resistor;
The source electrode of the third NMOS tube is grounded, the grid electrode is connected with the voltage detection signal, and the drain electrode is connected with the source electrode of the first PMOS tube through the third resistor;
The source electrode of the fourth NMOS tube is grounded, the grid electrode is connected with the voltage detection signal, and the drain electrode is connected with the source electrode of the first PMOS tube through the fourth resistor;
the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the second PMOS tube and outputs the control signal of the first PMOS tube;
and the grid electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube.
5. The drive protection system of claim 4, wherein: the clamping control unit further comprises a fifth resistor and a sixth resistor;
The fifth resistor is connected between the drain electrode of the fourth NMOS tube and the grid electrode of the second PMOS tube, the sixth resistor is connected between the drain electrode of the fifth NMOS tube and the drain electrode of the second PMOS tube, and the drain electrode of the second PMOS tube outputs the control signal of the first PMOS tube.
6. The drive protection system of claim 4 or 5, wherein: the clamping control unit further comprises a second voltage stabilizing tube and a third voltage stabilizing tube;
The anode of the second voltage stabilizing tube is grounded, and the cathode of the second voltage stabilizing tube is connected with the grid electrode of the fifth NMOS tube; and the anode of the third voltage stabilizing tube is connected with the grid electrode of the second PMOS tube, and the cathode of the third voltage stabilizing tube is connected with the source electrode of the second PMOS tube.
7. The drive protection system of claim 1, wherein: the first resistance is set to 500k ohms or more.
8. A chip comprising at least a drive protection system according to any one of claims 1-7.
9. An output clamp protection method implemented based on the drive protection system of any one of claims 1-7, wherein the output clamp protection method comprises at least:
under the conditions that the seventh NMOS tube is conducted and the power supply voltage of the output clamp protection module is powered off or undervoltage, the first PMOS tube is conducted, the grid potential of the second NMOS tube is pulled up by the first PMOS tube, the passage where the current-limiting anti-reflection unit is located and the passage where the first resistor is located, the second NMOS tube is conducted, a pull-down channel is provided for the grid of the sixth NMOS tube, and the sixth NMOS tube is turned off;
And under the condition that the power supply voltage of the output clamping protection module is normal, the first PMOS tube and the current-limiting anti-reflection unit are switched off.
10. The output clamp protection method of claim 9, wherein: the current-limiting anti-reflection unit comprises a diode and a second resistor which are connected in series, and when the difference value between the grid potential of the sixth NMOS tube and the grid potential of the second NMOS tube is larger than or equal to the starting voltage of the diode under the conditions that the seventh NMOS tube is conducted and the power supply voltage of the output clamping protection module is in power failure or under voltage, the grid potential of the second NMOS tube is pulled up by the first PMOS tube and a passage where the current-limiting anti-reflection unit is positioned; when the difference between the gate potential of the sixth NMOS tube and the gate potential of the second NMOS tube is smaller than the starting voltage of the diode, the channel where the first PMOS tube and the current-limiting anti-reflection unit are located is not conducted, and the gate potential of the second NMOS tube is pulled up by the channel where the first resistor is located.
CN202211138899.4A 2022-09-19 2022-09-19 Output clamping protection module, method, chip and driving protection system Active CN115459578B (en)

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