CN115328254A - High transient response LDO circuit based on multiple frequency compensation modes - Google Patents
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Abstract
The invention discloses a high transient response LDO (low dropout regulator) circuit based on multiple frequency compensation modes, which is divided into two parts, wherein the first part compares a voltage signal acquired by the second part with a reference voltage to obtain a residual voltage, samples and amplifies the residual voltage, and transmits a difference signal amplified by the residual voltage to a buffer stage circuit; the second part adjusts the conduction degree of the power tube by using the voltage signal passing through the buffer stage circuit, obtains a new voltage signal, and then transfers the new voltage signal to the first part after sampling. The frequency compensation is realized by adopting a mode of combining zero-pole tracking and Miller compensation, and the unit gain bandwidth of the system is increased while the extremely high phase margin is kept. A signal bypasses the buffer stage and is directly transmitted to the power tube through a feedforward path module when the voltage changes suddenly, so that faster transient response is realized, and the PVT circuit has good PVT characteristics while the structure is simple.
Description
Technical Field
The invention relates to a high transient response LDO circuit based on multiple frequency compensation modes, and belongs to the field of low dropout linear regulators.
Background
An LDO (Low Dropout Regulator) is a Low Dropout Regulator, which is usually used as a power management module in an integrated circuit chip to output a stable voltage for other functional modules. The LDO has a huge market share in numerous portable electronic products such as mobile phones, flat panels, intelligent household appliances and notebook computers, and the LDO chip can provide stable and low-noise voltage for subsequent circuits and has the advantages of low power consumption, high power ripple rejection ratio, good linear adjustment rate and load transient response, small chip area occupation and the like. With the change of the market and the advance of technology, the performance requirements of the LDO chip are continuously increasing. Higher conversion efficiency, lower power consumption and higher power supply noise rejection are becoming research hotspots and development trends of LDO chips.
The LDO is a typical application of a closed loop linear negative feedback system, and its main function is to provide a stable power supply voltage for the following stage circuit. As shown in fig. 1, the main structure of the LDO is divided into four modules: the voltage reference source, the error amplifier, the output power tube and the feedback resistance which are generated by the band-gap reference circuit form a voltage division feedback network. In practical application, various auxiliary circuits for improving the performance of the LDO are also provided.
The voltage stabilizing function of the LDO is mainly realized by adjusting a closed-loop negative feedback loop through an operational amplifier, and the self-stability of the negative feedback loop is adjusted to ensure that the LDO still can keep stable output voltage V under the condition that the load is changed OUT . The specific pressure stabilizing process comprises the following steps: output end load R L When decreasing, the output voltage V is constant, provided that the current through the load is constant OUT Is reduced so that the feedback voltage V between the two resistors REF And also decreases. V FB A reference voltage V fed back to the non-inverting input of the error amplifier REF In comparison, the output voltage of the error amplifier is reduced. Thereby outputting the gate-source voltage | V of the power tube GSP If l is increased, the current flowing through the power tube is also increased, and the voltage drop on the load is increased, so that the output voltage of the LDO is raised and kept stable. Otherwise, the same applies.
A load capacitor is added at the output end of the traditional LDO chip, and the capacitor and the equivalent series resistor thereof generate a low-frequency zero to stabilize the reduction of the phase margin caused by the main pole, thereby finally achieving the purpose of enhancing the system stability. The problems that arise are also apparent: firstly, the large capacitance (usually in micro-farad level) at the output end is difficult to integrate into the chip, and considerable chip area is wasted; secondly, since the equivalent series resistance is usually made larger, this will affect the transient response of the LDO; finally, due to the influence of the process level, the equivalent series resistance error of the capacitor is large, so that the position of the zero point may have deviation, if the zero point frequency is too low, the too high bandwidth of the system may cause other high-frequency poles to enter the bandwidth, and if the zero point frequency is too high, the system may exceed the unit gain bandwidth of the system, and the frequency compensation capability is lost.
From 2006, an LDO (filter-LDO) without an off-chip load capacitor gradually became a research hotspot, and the cost and the chip area cost of the completely new LDO are greatly reduced. However, the compensation effect of the off-chip large capacitor is lost, so that how to ensure the stability of the system becomes a new challenge, and the Capless-LDO without frequency compensation has no practical significance.
The essence of frequency compensation is to change the distribution of the zero poles of the system, the main pole of the system is changed into the interior of the system from the output end due to the loss of the off-chip large capacitor, many traditional frequency compensation methods such as a compensation method based on a capacitor equivalent series resistor are not applicable, and various brand new frequency compensation methods are proposed, such as a parallel voltage-controlled current source compensation method in a feedback loop, an improved Miller capacitor compensation based on the Miller effect, nested Miller compensation, an active feedback compensation and current buffering technology, damping coefficient compensation based on a control theory, and the like. However, in the prior art, it is difficult to simultaneously ensure the loop stability under light load and the fast transient response under heavy load. The invention can overcome the defects of the prior art and enhance the transient response while ensuring higher phase margin.
Disclosure of Invention
The invention adopts a mode of combining various technologies to realize frequency compensation, simultaneously provides a new mode to realize rapid transient response, and has the advantages of ultrahigh phase margin, simple structure, good PVT stability, rapid transient response and strong loading capacity.
The adopted technical scheme is that the high transient response LDO circuit based on multiple frequency compensation modes is divided into two parts, wherein the first part compares a voltage signal acquired by the second part with a reference voltage to obtain a residual voltage, samples and amplifies the residual voltage, and transmits a difference signal obtained by amplifying the residual voltage to a buffer stage circuit; the second part adjusts the conduction degree of the power tube by using the voltage signal passing through the buffer stage circuit, obtains a new voltage signal, and then transfers the new voltage signal to the first part after sampling.
The above purpose is realized by the following technical scheme:
the high transient response LDO circuit comprises five parts: the circuit comprises a folding cascode amplifier, a feed-forward circuit, a buffer stage circuit, a frequency compensation circuit (zero-pole tracking compensation and Miller compensation adopting an embedded current buffer technology) and a power stage circuit. The dynamic frequency compensation of the traditional LDO circuit is realized, and the stability of the LDO loop is ensured. As shown in fig. 2, the inverting input terminal of the folded cascode amplifier is connected to a reference voltage V REF The same-phase input terminal is connected with a feedback voltage V FB And the output end is connected with the buffer stage. And a zero pole tracking frequency compensation circuit is connected between the buffer stage and the grid electrode of the power tube. The drain of the power tube is connected with the output end, and two series feedback divider resistors R are arranged between the output end and the ground FB1 、R FB2 Feedback voltage V between two resistors FB And the output voltage is connected back to the non-inverting input end of the folded cascode amplifier to form a negative feedback loop. In order to enhance the stability of a loop, a Miller compensation circuit adopting an embedded current buffer technology is connected between the folding type cascode amplifier and the output. In order to achieve faster transient response, the present invention directly connects the feed-forward circuit from the folded cascode amplifier to the power tube gate.
Furthermore, the folded cascode amplifier circuit comprises PMOS tubes M1, M2, M7, M8, M9 and M10, NMOS tubes M3, M4, M5 and M6 and a tail current source I tail1 . Grid connection V of PMOS tube M1 FB Source connected to tail current source I tail1 Drain electrode connected to PMThe source electrode of the OS tube M3 and the drain electrode of the NMOS tube M5; grid electrode of PMOS tube M2 is connected with reference voltage V REF Source connected to tail current source I tail1 The drain electrode is connected with the source electrode of the PMOS tube M4 and the drain electrode of the NMOS tube M6; the grid electrodes of the PMOS tubes M7 and M8 are connected with the drain electrode of the PMOS tube M9, and the source electrodes are connected with V in The drain electrode is respectively connected with the source electrode of the PMOS tube M9 and the source electrode of the PMOS tube M10; the grids of the PMOS tubes M9 and M10 are both connected with a bias voltage V B1 The drain electrode is respectively connected with the drain electrode of the PMOS tube M3 and the drain electrode of the PMOS tube M4; the grids of the NMOS transistors M3 and M4 are connected with a bias voltage V B2 The source electrode is respectively connected with the drain electrodes of the NMOS tubes M5 and M6; the grids of the NMOS transistors M5 and M6 are connected with a bias voltage V B3 And the sources are all grounded.
The feedforward circuit comprises PMOS tubes M11, M12 and M13, NMOS tubes M14 and M15 and a tail current source I tail2 . The source electrodes of the PMOS tubes M11 and M12 are connected with a tail current source I tail2 The grid electrodes are respectively connected with the source electrodes of the NMOS tubes M3 and M4, the drain electrode of the PMOS tube M11 is grounded, and the drain electrode of the PMOS tube M12 is connected with the source electrode of the PMOS tube M13; the grid of the PMOS transistor M13 is connected with a limiting voltage V limit (ii) a The grid electrodes of the NMOS tubes M14 and M15 are connected with the drain electrode of the PMOS tube M13, the source electrodes are grounded, and the grid electrode of the NMOS tube M14 is in short circuit; the drain of the NMOS transistor M15 is connected to the gate of the PMOS transistor M18.
The buffer stage circuit comprises a PMOS tube M16 and a tail current source I tail3 Source-tail current source I of PMOS transistor M16 tail3 The grid is connected with the drain of the PMOS tube M10, and the drain is grounded.
The frequency compensation circuit comprises a PMOS tube M17 and a capacitor C 1 、C 2 And a resistance R 1 . The source electrode of the PMOS tube M17 is connected with V in A grid connected to a capacitor C 1 One end of (1), drain electrode is connected with a capacitor C 1 The other end of (a); resistance R 1 One end of the capacitor is connected with the source electrode of the NMOS tube M4, and the other end of the capacitor is connected with the capacitor C 2 (ii) a Capacitor C 2 The other end of the first switch is connected with the output end.
The power stage circuit comprises a divider resistor R FB1 、R FB2 And a PMOS transistor M18. The source electrode of the PMOS transistor M18 is connected with V in The grid is connected with the grid of the PMOS tube M17, and the drain is connected with the output end; voltage dividing resistor R FB1 One end is connected with the output end, and the other end is connected with the voltage dividing resistor R FB2 (ii) a Divider resistor R FB2 The other end is grounded; a feedback voltage V formed between the two voltage dividing resistors FB To the gate of PMOS transistor M1.
The invention realizes frequency compensation by adopting a mode of combining zero-pole tracking and Miller compensation, and increases the unit gain bandwidth of the system while keeping extremely high phase margin. A signal bypasses the buffer stage and is directly transmitted to the power tube through a feedforward path module when the voltage is suddenly changed, so that the faster transient response is realized, and the PVT characteristic is good while the structure is simple.
Drawings
FIG. 1 is a schematic diagram of the basic structure of LDO
FIG. 2 is a block diagram of an LDO configuration of the present invention
FIG. 3 is a schematic diagram of an LDO circuit of the present invention
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
A high transient response LDO circuit based on multiple frequency compensation modes is divided into two parts, wherein the first part compares a voltage signal acquired by the second part with a reference voltage to obtain a residual voltage, samples and amplifies the residual voltage, and transmits a difference signal obtained after amplifying the residual voltage to a buffer stage circuit; the second part adjusts the conduction degree of the power tube by using the voltage signal passing through the buffer stage circuit, obtains a new voltage signal, and then transfers the new voltage signal to the first part after sampling.
Frequency compensation principle:
the frequency compensation module is divided into two parts, wherein the first part comprises a PMOS (P-channel metal oxide semiconductor) transistor M17 and a capacitor C 1 A zero-pole tracking compensation part; the second part being a capacitor C 2 And a resistance R 1 The Miller compensation part adopting the embedded current buffer technology is formed.
Equivalent resistance and capacitance C of PMOS tube M17 working in depth linear region 1 A dynamic zero may be generated between the buffer source and ac ground. The PMOS tube M17 is connected with the grid end of the M18, and controls the grid-source voltage of the M17, thereby controlling the equivalent resistance. At the appropriate selection of PMAfter the size of the OS tube M17, the zero and the output end pole can be offset, so that the effect of zero pole tracking compensation is achieved.
Capacitor C 2 The capacitor can be considered to be bridged at two ends of the amplifier, and the Miller effect can indicate that the capacitor generates a larger equivalent capacitance to the ground at the input end, so that the low frequency in two adjacent poles shifts to a lower frequency, and the output end is similar, thereby generating 'pole splitting'. The Miller capacitor improves the stability of the system in this way, and simultaneously increases the bandwidth of the system and enhances the transient performance of the system. But it also generates a right half-plane zero point, so that the phase intersection point of the system is shifted to the left, the gain intersection point is shifted to the right, the stability of the system is influenced, and the system and the capacitor C are connected 2 Series-connected resistor R 1 It is to solve this problem. When the resistance R is 1 When the amplitude is large enough, a left half-plane zero point is generated to increase the phase margin and enhance the stability of the system.
Besides, the invention also adopts the embedded current buffer technology, and the PMOS tubes M4 and M6 are used as a part of the error amplifier and are also connected with the Miller capacitor C 2 Together forming a current buffer circuit. Because the feedback current and the feedforward current which bring negative effects flow through the Miller capacitor branch, the PMOS tubes M4 and M6 can enable the current flowing through the Miller capacitor to have directionality, block the feedforward current and eliminate the negative effects. As the embedded current buffer technology does not add a new MOS tube, no extra power consumption is generated.
Feed-forward path principle:
when the circuit is started, after the input voltage of the system changes transiently, the current of the path where the two groups of cascode transistors M1 and M3 and M2 and M4 are located changes immediately, so that the grid voltages of M11 and M12 change, and the current of the M12-M14 branch circuits is further influenced. Here M13 gate terminal limits the voltage V limit The protection tube prevents the branch circuit from overlarge current. After M15 copies the current of M14, M16 of the buffer stage is bypassed, and the gate voltage of the power tube M18 is directly influenced. The feed-forward path skips the buffer stage and directly goes from the error amplifier to the output power tube, thereby reducing the circuit from being built from the start-upThe steady state time greatly improves the transient response of the circuit.
And (3) voltage stabilization principle:
when the voltage at the output end of the LDO changes, the feedback resistor R FB1 And a resistance R FB2 And transmitting the divided sampling voltage signal to the gate end of the PMOS tube M1, comparing the divided sampling voltage signal with the reference voltage, amplifying the difference voltage of the divided sampling voltage signal and the reference voltage signal by using a folding cascode amplifier, and transmitting the amplified difference voltage to the gate end of the power tube M18 to control the conduction degree of the power tube after the source follower increases the swing amplitude. So that the current flowing through the two feedback resistors changes and the feedback voltage V between the two resistors FB And also varies accordingly, finally V FB And is fed back to M1 to form a negative feedback loop to realize voltage stabilization. Wherein, the differential input terminals M1 and M2 select PMOS tubes rather than NMOS tubes because the thermal noise of the former is smaller, and the gain-stage amplifier selects a folding type cascode structure because the gain-stage amplifier provides quite high gain and simultaneously has good transient performance.
The invention has the beneficial effects that:
the invention has no external capacitor LDO, and the finally designed circuit only needs a capacitor of several pF, thereby realizing the complete integration of the whole system, greatly improving the integration degree of the LDO, saving the chip area and reducing the chip cost. Due to the combined action of multiple compensation modes, the ultra-high phase margin of 88deg is still provided even under the condition of light load, and the stable operation of the system is guaranteed. At the same time, such a high phase margin allows the presence of a power tube of larger dimensions, which increases the maximum current that the latter can pass, i.e. the drive capacity of the system. The presence of the feed-forward path module accelerates the speed of the feedback loop, so that the system can recover to a normal operating state in a shorter time in the face of sudden changes of the input voltage.
It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (6)
1. A high transient response LDO circuit based on multiple frequency compensation mode, its characterized in that: the high transient response LDO circuit is divided into two parts, wherein the first part compares the voltage signal acquired by the second part with a reference voltage to obtain a residual voltage, samples and amplifies the residual voltage, and transmits a difference signal obtained after amplifying the residual voltage to a buffer stage circuit; the second part adjusts the conduction degree of the power tube by using the voltage signal passing through the buffer stage circuit, obtains a new voltage signal, and then transmits the new voltage signal to the first part after sampling;
the high transient response LDO circuit comprises: the circuit comprises a folding cascode amplifier, a feedforward circuit, a buffer circuit, a frequency compensation circuit and a power circuit; the inverting input end of the folding cascode amplifier is connected with a reference voltage V REF The same-phase input terminal is connected with a feedback voltage V FB The output end is connected with the buffer stage; a zero-pole tracking frequency compensation circuit is connected between the buffer stage and the grid electrode of the power tube; the drain of the power tube is connected with the output end, and two series feedback divider resistors R are arranged between the output end and the ground FB1 、R FB2 Feedback voltage V between two resistors FB The input end of the folded cascode amplifier is connected back to the in-phase input end of the folded cascode amplifier to form a negative feedback loop; in order to enhance the stability of a loop, a Miller compensation circuit adopting an embedded current buffer technology is connected between the folding cascode amplifier and the output; to achieve faster transient response, the feed-forward circuit is connected directly from the folded cascode amplifier to the power tube gate.
2. The LDO circuit with high transient response based on multiple frequency compensation modes of claim 1, wherein: the folding cascode amplifier circuit comprises PMOS tubes M1, M2, M7, M8, M9 and M10, NMOS tubes M3, M4, M5 and M6 and a tail current source I tail1 (ii) a Grid connection V of PMOS tube M1 FB Source connected to tail current source I tail1 The drain electrode is connected with the source electrode of the PMOS tube M3 and the drain electrode of the NMOS tube M5; grid electrode of PMOS tube M2 is connected with reference voltage V REF Source connected to tail current source I tail1 The drain electrode is connected with the source electrode of the PMOS tube M4 and the drain electrode of the NMOS tube M6A pole; the grid electrodes of the PMOS tubes M7 and M8 are connected with the drain electrode of the PMOS tube M9, and the source electrodes are connected with V in The drain electrode is respectively connected with the source electrode of the PMOS tube M9 and the source electrode of the PMOS tube M10; the grids of the PMOS tubes M9 and M10 are connected with a bias voltage V B1 The drain electrode is respectively connected with the drain electrode of the PMOS tube M3 and the drain electrode of the PMOS tube M4; the grids of the NMOS transistors M3 and M4 are connected with a bias voltage V B2 The source electrode is respectively connected with the drain electrodes of the NMOS tubes M5 and M6; the grids of the NMOS transistors M5 and M6 are connected with a bias voltage V B3 And the sources are all grounded.
3. The LDO circuit with high transient response based on multiple frequency compensation modes as claimed in claim 1, wherein: the feed-forward circuit comprises PMOS tubes M11, M12 and M13, NMOS tubes M14 and M15 and a tail current source I tail2 (ii) a The source electrodes of the PMOS tubes M11 and M12 are connected with a tail current source I tail2 The grid electrodes are respectively connected with the source electrodes of the NMOS tubes M3 and M4, the drain electrode of the PMOS tube M11 is grounded, and the drain electrode of the PMOS tube M12 is connected with the source electrode of the PMOS tube M13; the grid of the PMOS transistor M13 is connected with a limiting voltage V limit (ii) a The grid electrodes of the NMOS tubes M14 and M15 are connected with the drain electrode of the PMOS tube M13, the source electrodes are grounded, and the grid electrode of the NMOS tube M14 is in short circuit; the drain of the NMOS transistor M15 is connected to the gate of the PMOS transistor M18.
4. The LDO circuit with high transient response based on multiple frequency compensation modes of claim 1, wherein: the buffer stage circuit comprises a PMOS tube M16 and a tail current source I tail3 Source-tail current source I of PMOS transistor M16 tail3 The grid is connected with the drain of the PMOS tube M10, and the drain is grounded.
5. The LDO circuit with high transient response based on multiple frequency compensation modes as claimed in claim 1, wherein: the frequency compensation circuit comprises a PMOS tube M17 and a capacitor C 1 、C 2 And a resistance R 1 (ii) a The source electrode of the PMOS tube M17 is connected with V in A grid connected to a capacitor C 1 One end of (1), drain electrode is connected with a capacitor C 1 The other end of (a); resistance R 1 One end of the capacitor is connected with the source electrode of the NMOS tube M4, and the other end of the capacitor is connected with the capacitor C 2 (ii) a Capacitor C 2 The other end of the first switch is connected with the outputAnd (4) an end.
6. The LDO circuit with high transient response based on multiple frequency compensation modes of claim 1, wherein: the power stage circuit comprises a divider resistor R FB1 、R FB2 And a PMOS transistor M18; the source electrode of the PMOS transistor M18 is connected with V in The grid is connected with the grid of the PMOS tube M17, and the drain is connected with the output end; divider resistor R FB1 One end is connected with the output end, and the other end is connected with the voltage dividing resistor R FB2 (ii) a Divider resistor R FB2 The other end is grounded; a feedback voltage V formed between the two voltage dividing resistors FB To the gate of PMOS transistor M1.
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| CN116418230A (en) * | 2023-06-12 | 2023-07-11 | 上海海栎创科技股份有限公司 | Wide-range filter capacitor LDO structure, system and use method |
| CN116578152A (en) * | 2023-05-25 | 2023-08-11 | 西安电子科技大学 | Zero-setting resistor and active feedforward double-compensation non-output capacitor LDO circuit |
| CN116707467A (en) * | 2023-08-04 | 2023-09-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
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| CN116578152A (en) * | 2023-05-25 | 2023-08-11 | 西安电子科技大学 | Zero-setting resistor and active feedforward double-compensation non-output capacitor LDO circuit |
| CN116578152B (en) * | 2023-05-25 | 2024-01-09 | 西安电子科技大学 | Zero-setting resistor and active feedforward double-compensation non-output capacitor LDO circuit |
| CN116418230A (en) * | 2023-06-12 | 2023-07-11 | 上海海栎创科技股份有限公司 | Wide-range filter capacitor LDO structure, system and use method |
| CN116418230B (en) * | 2023-06-12 | 2023-09-12 | 上海海栎创科技股份有限公司 | Wide-range filter capacitor LDO structure, system and use method |
| CN116707467A (en) * | 2023-08-04 | 2023-09-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
| CN116707467B (en) * | 2023-08-04 | 2023-12-05 | 核芯互联科技(青岛)有限公司 | class-AB structure voltage buffer suitable for large capacitive load |
| CN117075673A (en) * | 2023-10-16 | 2023-11-17 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
| CN117075673B (en) * | 2023-10-16 | 2024-01-05 | 深圳前海深蕾半导体有限公司 | Nested loop low-dropout linear voltage regulator |
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