CN115274613A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115274613A CN115274613A CN202110483933.0A CN202110483933A CN115274613A CN 115274613 A CN115274613 A CN 115274613A CN 202110483933 A CN202110483933 A CN 202110483933A CN 115274613 A CN115274613 A CN 115274613A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 238000002161 passivation Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000003466 welding Methods 0.000 claims abstract description 31
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 42
- 239000003989 dielectric material Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005856 abnormality Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010008 shearing Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005728 strengthening Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a device structure and a metal interconnection layer positioned on the device structure, and the metal interconnection layer comprises a top metal layer; forming a dielectric layer and a plurality of branch openings which are positioned in the dielectric layer and expose part of the top metal layer on the surface of the substrate, wherein the peripheral edges of the openings are in a sawtooth shape, and the openings comprise main openings and a plurality of branch openings which are positioned on the periphery of the main openings and are communicated with the main openings; forming a welding pad layer in the opening; and forming a passivation layer on the surface of the dielectric layer. The shape of the opening enables the formation of a sawtooth structure to be formed on the periphery of the welding pad layer, and due to the fact that the periphery of the welding pad layer is fixed to involve and reinforce the effect, the welding pad layer is not prone to deviating from a target position, the probability of contact between the welding pad layers is reduced, and then the probability of short circuit abnormality of a device is reduced, and therefore reliability of a semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the field of semiconductor manufacturing, packaging is a process that is performed later in the production of Integrated Circuits (ICs) and is also of paramount importance. Packaging is a process of assembling an integrated circuit into a chip final product, in short, an integrated circuit Die (Die) produced by a foundry is placed on a substrate which plays a bearing role, pins are led out, and then the integrated circuit Die is fixed and packaged into a whole, so that connection between an internal chip and an external circuit is realized.
In the process of manufacturing Integrated Circuit (IC) packages, an essential link is a Wire Bonding process, which means that a metal Wire (gold Wire, aluminum Wire, etc.) is used to complete the connection of the interconnection wires inside the solid-state circuit in the microelectronic device by using a hot-pressing or ultrasonic energy source, i.e., the connection between the chip and the circuit or the lead frame.
However, the existing wire bonding process needs to be further improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a device structure and a metal interconnect layer located on the device structure, the metal interconnect layer comprising a top metal layer; the openings are positioned in the dielectric layer and the dielectric layer on the surface of the substrate and expose part of the top metal layer, the peripheral edges of the openings are in a sawtooth shape, and the openings comprise main openings and a plurality of branch openings which are positioned on the periphery of the main openings and are communicated with the main openings; a pad layer located within the opening; and the passivation layer is positioned on the surface of the dielectric layer.
Optionally, a size of a horizontal plane projection of the branch opening in a circumferential direction along the horizontal plane projection of the main opening is greater than 1.8 micrometers.
Optionally, the distance between horizontal plane projections of adjacent branch openings in the circumferential direction along the horizontal plane projection of the main opening is greater than 1.8 micrometers.
Optionally, the material of the top metal layer includes a metal.
Optionally, the material of the dielectric layer includes silicon oxide.
Optionally, the material of the pad layer includes a metal.
Optionally, the pad layer is further located on the dielectric layer, and a sidewall of the pad layer is flush with a sidewall of the top metal layer.
Optionally, the passivation layer is further located on the surface of the pad layer, and a slot is formed in the passivation layer, and a side wall of the slot is flush with a side wall of the main opening.
Optionally, the material of the passivation layer includes silicon nitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a device structure and a metal interconnection layer positioned on the device structure, and the metal interconnection layer comprises a top metal layer; forming a dielectric layer and a plurality of openings which are positioned in the dielectric layer and expose part of the top metal layer on the surface of the substrate, wherein the peripheral edges of the openings are in a sawtooth shape, and the openings comprise main openings and a plurality of branch openings which are positioned on the periphery of the main openings and are communicated with the main openings; forming a welding pad layer in the opening; and forming a passivation layer on the surface of the dielectric layer.
Optionally, the method for forming the dielectric layer, the main opening and the branch openings includes: forming a dielectric material layer on the surface of the substrate; forming a first patterning layer on the surface of the dielectric material layer, wherein the first patterning layer exposes a part of the dielectric material layer; and etching the dielectric material layer by taking the first patterning layer as a mask until part of the top metal layer is exposed to form the dielectric layer, the main opening and the branch openings.
Optionally, the forming method of the pad layer includes: forming a pad material layer in the opening and on the surface of the dielectric layer; forming a second patterned layer on the surface of the welding pad material layer; and etching the welding pad material layer by taking the second graphical layer as a mask until the part or the whole surface of the dielectric layer is exposed to form the welding pad layer.
Optionally, the forming process of the passivation layer includes: forming a passivation material layer on the surfaces of the dielectric layer and the welding pad layer; forming a third patterned layer on the surface of the passivation material layer, wherein the third patterned layer exposes a part of the passivation material layer; and etching the passivation material layer by taking the third patterning layer as a mask until part or all of the welding pad layer is exposed to form the passivation layer and a groove in the passivation layer.
Optionally, the opening groove exposes a portion of the pad layer, and the side wall of the opening groove is flush with the side wall of the main opening.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method of the semiconductor structure in the technical scheme of the invention, a dielectric layer and an opening which is positioned in the dielectric layer and exposes part of the top metal layer are formed on the surface of the substrate, the peripheral edge of the opening is in a sawtooth shape, and the opening comprises a main opening and a plurality of branch openings which are positioned on the periphery of the main opening and are communicated with the main opening; the opening is internally provided with a welding pad layer which is electrically connected with the top metal layer, and meanwhile, the shape of the opening enables the welding pad layer to be formed to have a saw-toothed structure all around.
In the semiconductor structure of the technical scheme, the periphery of the welding pad layer is provided with the saw-toothed structure, and due to the fixing, dragging and strengthening effect of the periphery of the welding pad layer, the welding pad layer is not easy to deviate from a target position when the welding pad layer is subjected to a shearing force in a direction parallel to the surface of the substrate subsequently, so that the probability of contact between the welding pad layers is reduced, the probability of short circuit abnormality of a device is further reduced, and the reliability of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;
fig. 2 to 12 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the semiconductor structure formed by the conventional wire bonding process is still to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment.
Please refer to fig. 1, which includes: a substrate, wherein the substrate comprises a base 100, a metal interconnection layer 102 located on the base 100, the top of the metal interconnection layer 102 has a top metal layer 103, the base 100 has a device structure (not shown) therein, the top metal layer 103 is electrically connected to the device structure, and the device structure comprises one or more combinations of transistors, diodes, triodes, capacitors, inductors, and conductive structures; forming a passivation layer 104 and an opening (not labeled) in the passivation layer 104 on the metal interconnection layer 102, wherein the opening exposes the top metal layer 103; a pad 105 is formed within the opening.
In the wire bonding process, the lead is well adhered to the pad 105 due to the need to apply a certain mechanical stress to the pad 105. The direction of the mechanical stress is generally not perpendicular to the substrate surface, i.e., the mechanical stress has a shearing force in a direction parallel to the substrate surface, thereby easily causing the solder pads 105 to be extruded, even if the solder pads 105 deviate from a target position in the direction parallel to the substrate surface, further increasing the probability of contact between the solder pads 105, resulting in the occurrence of abnormal phenomena of device short circuit.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein the periphery of the pad layer has a saw-toothed structure, and due to the fixing, pulling and strengthening effect of the periphery of the pad layer, the pad layer is not easy to deviate from a target position when subjected to a shearing force in a direction parallel to the surface of the substrate, so that the probability of contact between the pad layers is reduced, and further, the probability of device short circuit abnormality is reduced, thereby improving the reliability of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 12 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 2 and fig. 3, fig. 2 is a top view, and fig. 3 is a schematic cross-sectional view taken along line X1X2 in fig. 2, providing a substrate 200, where the substrate 200 includes a device structure (not shown) and a metal interconnect layer located on the device structure, where the metal interconnect layer includes a top metal layer 201.
In this embodiment, the substrate further includes a base, and the device structure is located on the base; the metal interconnect layer is electrically interconnected with the device structure. The device structure includes one or a combination of more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure. The metal interconnect layer may include several metal layers, and the top metal layer 201 is located at the top of the metal interconnect layer.
In this embodiment, the substrate is made of silicon. In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
The material of the top metal layer 201 includes metal. In this embodiment, the top metal layer 201 is made of copper.
Referring to fig. 4 to 6, fig. 4 is a top view, fig. 5 is a schematic cross-sectional structure along the direction X1X2 in fig. 4, fig. 6 is a schematic cross-sectional structure along the direction X3X4 in fig. 4, a dielectric layer 202 and an opening located in the dielectric layer 202 and exposing a portion of the top metal layer 201 are formed on the surface of the substrate 200, the periphery of the opening is zigzag, and the opening includes a main opening 203 and a plurality of branch openings 204 located around the main opening 203 and communicated with the main opening 203.
The method for forming the dielectric layer 202, the main opening 203 and the branch openings 204 comprises the following steps: forming a dielectric material layer (not shown) on the surface of the substrate 200; forming a first patterned layer (not shown) on the surface of the dielectric material layer, wherein the first patterned layer exposes a portion of the dielectric material layer; and etching the dielectric material layer by taking the first patterning layer as a mask until part of the top metal layer 201 is exposed, and forming the dielectric layer 202, the main opening 203 and the branch openings 204.
The opening is used for forming a welding pad layer subsequently, the welding pad layer is electrically connected with the top metal layer, and the welding pad layer is used for being electrically connected with an external circuit.
The dimension M of the horizontal plane projection of the branch opening 204 in the circumferential direction along the horizontal plane projection of the main opening 203 is larger than 1.8 micrometers.
The distance N of the horizontal plane projection of the adjacent branch openings 204 in the circumferential direction along the horizontal plane projection of the main opening 203 is larger than 1.8 micrometers.
Subsequently, the main opening 203 is used to form a main body of the pad layer, and the branch openings 204 are used to form a saw-tooth structure for facilitating the position fixing of the pad layer. The saw-toothed structure can increase the area of the welding pad layer by a small amount, and the size of the support opening 204 can be adjusted according to actual requirements, so that the firmness of the welding pad layer can be increased, and the performance of the welding pad layer main body can be ensured.
The material of the dielectric layer 202 includes silicon oxide. In this embodiment, the dielectric layer is made of silicon oxide. In other embodiments, the material of the dielectric layer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Referring to fig. 7 to 9, fig. 8 is a schematic cross-sectional view taken along the direction X1X2 in fig. 7, and fig. 9 is a schematic cross-sectional view taken along the direction X3X4 in fig. 7, wherein a pad layer 205 is formed in the opening.
The method for forming the pad layer 205 includes: forming a pad material layer (not shown) in the opening and on the surface of the dielectric layer 202; forming a second patterned layer (not shown) on the surface of the pad material layer; and etching the pad material layer by using the second patterned layer as a mask until part or all of the surface of the dielectric layer 202 is exposed to form the pad layer 205.
In this embodiment, the pad layer 205 is further located on the dielectric layer 202, and the sidewall of the pad layer 205 is flush with the sidewall of the top metal layer 201. Since no surface planarization is performed after the formation of the pad material layer, the surface of the middle region of the pad layer 205 located in the main opening 203 and the branch opening 204 is flush with the dielectric layer 202, and the edge region of the pad layer 205 located on the dielectric layer 202 protrudes relative to the middle region.
The material of the pad layer 205 includes metal. In this embodiment, the pad layer 205 is made of aluminum.
Due to the shape of the opening, the formed periphery of the bonding pad layer 205 is provided with a saw-toothed structure, due to the fixing and pulling strengthening effect of the periphery of the bonding pad layer 205, when a shearing force in a direction parallel to the surface of the substrate 200 is applied subsequently, the bonding pad layer 205 is not easy to deviate from a target position, the probability of contact between the bonding pad layers 205 is reduced, the probability of abnormal short circuit of a device is further reduced, and the reliability of a semiconductor structure is improved.
Referring to fig. 10 to 12, fig. 11 is a schematic cross-sectional view taken along a direction X1X2 in fig. 10, and fig. 12 is a schematic cross-sectional view taken along a direction X3X4 in fig. 10, wherein a passivation layer 206 is formed on the surface of the dielectric layer 202.
The formation process of the passivation layer 206 includes: forming a passivation layer (not shown) on the surfaces of the dielectric layer 202 and the pad layer 205; forming a third patterned layer (not shown) on the surface of the passivation material layer, wherein the third patterned layer exposes a portion of the passivation material layer; and etching the passivation material layer by using the third patterned layer as a mask until part or all of the pad layer is exposed to form the passivation layer 206 and a slot 207 in the passivation layer 206.
In this embodiment, the opening 207 exposes a portion of the pad layer 205, and the sidewall of the opening 207 is flush with the sidewall of the main opening 203. Because the edge region of the pad layer 205 is located between the passivation layer 206 and the dielectric layer 202, the position of the edge region is not easy to deviate from the target position, so that the adhesion between the pad layer 205 and the passivation layer 206 and between the pad layer 205 and the dielectric layer 202 are increased, the pad layer 205 is not easy to peel off, and the reliability of the semiconductor structure is improved.
Accordingly, the present invention further provides an embodiment of a semiconductor structure formed by the above-mentioned forming method, with reference to fig. 10 to 12, including: a substrate 200, wherein the substrate 200 includes a device structure (not shown) and a metal interconnection layer located on the device structure, and the metal interconnection layer includes a top metal layer 201; an opening located in the dielectric layer 202 and the dielectric layer 202 on the surface of the substrate 200 and exposing a portion of the top metal layer, wherein the periphery of the opening is zigzag, and the opening includes a main opening 203 (shown in fig. 4) and a plurality of branch openings 204 (shown in fig. 4) located around the main opening and communicating with the main opening 203; a pad layer 205 located within the opening; a passivation layer 206 on the surface of the dielectric layer 202.
The size of the horizontal plane projection of the branch opening 204 in the circumferential direction along the horizontal plane projection of the main opening 203 is larger than 1.8 micrometers.
The distance between the horizontal plane projection of the adjacent branch openings 204 in the circumferential direction along the horizontal plane projection of the main opening 203 is greater than 1.8 micrometers.
The material of the top metal layer 201 includes metal. In this embodiment, the top metal layer 201 is made of copper.
The material of the dielectric layer 202 includes silicon oxide. In this embodiment, the dielectric layer 202 is made of a material. In other embodiments, the material of the dielectric layer 202 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
The material of the pad layer 205 includes metal. In this embodiment, the pad layer 205 is made of aluminum.
The pad layer 205 is also located on the dielectric layer 202, and the sidewall of the pad layer 205 is flush with the sidewall of the top metal layer 201.
The passivation layer 206 is also located on the surface of the pad layer 205, and the passivation layer 206 has a slot 207 therein, and the side wall of the slot 207 is flush with the side wall of the main opening 203.
The material of the passivation layer 206 comprises silicon nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A semiconductor structure, comprising:
a substrate comprising a device structure and a metal interconnect layer located on the device structure, the metal interconnect layer comprising a top metal layer;
the openings are positioned in the dielectric layer and the dielectric layer on the surface of the substrate and expose part of the top metal layer, the peripheral edges of the openings are in a sawtooth shape, and the openings comprise main openings and a plurality of branch openings which are positioned on the periphery of the main openings and are communicated with the main openings;
a pad layer located within the opening;
and the passivation layer is positioned on the surface of the dielectric layer.
2. The semiconductor structure of claim 1, wherein a horizontal projection of the branch aperture has a dimension in a perimeter direction along a horizontal projection of the main aperture that is greater than 1.8 microns.
3. The semiconductor structure of claim 1, wherein a distance of a horizontal plane projection of adjacent ones of the branch openings in a perimeter direction along a horizontal plane projection of the main opening is greater than 1.8 microns.
4. The semiconductor structure of claim 1, in which a material of the top metal layer comprises a metal.
5. The semiconductor structure of claim 1, wherein a material of the dielectric layer comprises silicon oxide.
6. The semiconductor structure of claim 1, wherein a material of the pad layer comprises a metal.
7. The semiconductor structure of claim 1, wherein the pad layer is further on the dielectric layer and the pad layer sidewalls are flush with the top metal layer sidewalls.
8. The semiconductor structure of claim 1, wherein the passivation layer is further on the pad layer surface and has a trench therein, the trench sidewall being flush with the main opening sidewall.
9. The semiconductor structure of claim 1, wherein a material of the passivation layer comprises silicon nitride.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a device structure and a metal interconnection layer positioned on the device structure, and the metal interconnection layer comprises a top metal layer;
forming a dielectric layer and an opening which is positioned in the dielectric layer and exposes part of the top metal layer on the surface of the substrate, wherein the peripheral edge of the opening is in a sawtooth shape, and the opening comprises a main opening and a plurality of branch openings which are positioned on the periphery of the main opening and are communicated with the main opening;
forming a welding pad layer in the opening;
and forming a passivation layer on the surface of the dielectric layer.
11. The method of forming a semiconductor structure of claim 10, wherein the method of forming the dielectric layer, the main opening, and the branch openings comprises: forming a dielectric material layer on the surface of the substrate; forming a first patterning layer on the surface of the dielectric material layer, wherein the first patterning layer exposes a part of the dielectric material layer; and etching the dielectric material layer by taking the first patterning layer as a mask until part of the top metal layer is exposed to form the dielectric layer, the main opening and the branch openings.
12. The method of forming a semiconductor structure of claim 10, wherein the method of forming the pad layer comprises: forming a welding pad material layer in the opening and on the surface of the dielectric layer; forming a second patterned layer on the surface of the welding pad material layer; and etching the welding pad material layer by taking the second patterning layer as a mask until the part or the whole surface of the dielectric layer is exposed to form the welding pad layer.
13. The method of claim 10, wherein the passivation layer is formed by a process comprising: forming a passivation material layer on the surfaces of the dielectric layer and the welding pad layer; forming a third patterned layer on the surface of the passivation material layer, wherein the third patterned layer exposes a part of the passivation material layer; and etching the passivation material layer by taking the third patterning layer as a mask until part or all of the welding pad layer is exposed to form the passivation layer and a groove in the passivation layer.
14. The method of forming a semiconductor structure of claim 13, wherein said trench exposes a portion of said pad layer, said trench sidewalls being flush with said main opening sidewalls.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020078217A (en) * | 2001-04-06 | 2002-10-18 | 신코 덴키 코교 가부시키가이샤 | Surface mounting substrate having bonding pads in staggered arrangement |
| JP2003338585A (en) * | 2002-05-22 | 2003-11-28 | Kyocera Corp | Wiring board |
| US20060240660A1 (en) * | 2005-04-20 | 2006-10-26 | Jin-Sheng Yang | Semiconductor stucture and method of manufacturing the same |
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| US20170330827A1 (en) * | 2016-05-12 | 2017-11-16 | Digi International Inc. | Hybrid embedded surface mount module form factor with same signal source subset mapping |
| CN108630657A (en) * | 2017-03-24 | 2018-10-09 | 联华电子股份有限公司 | Semiconductor structure and preparation method thereof |
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| KR20020078217A (en) * | 2001-04-06 | 2002-10-18 | 신코 덴키 코교 가부시키가이샤 | Surface mounting substrate having bonding pads in staggered arrangement |
| JP2003338585A (en) * | 2002-05-22 | 2003-11-28 | Kyocera Corp | Wiring board |
| US20060240660A1 (en) * | 2005-04-20 | 2006-10-26 | Jin-Sheng Yang | Semiconductor stucture and method of manufacturing the same |
| US20070115606A1 (en) * | 2005-11-21 | 2007-05-24 | Devries Kenneth L | Method and structure for charge dissipation in integrated circuits |
| CN102543921A (en) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Welding pad structure and manufacturing method thereof |
| US20170330827A1 (en) * | 2016-05-12 | 2017-11-16 | Digi International Inc. | Hybrid embedded surface mount module form factor with same signal source subset mapping |
| CN108630657A (en) * | 2017-03-24 | 2018-10-09 | 联华电子股份有限公司 | Semiconductor structure and preparation method thereof |
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