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CN118231357A - Chip packaging method and packaging structure - Google Patents

Chip packaging method and packaging structure Download PDF

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Publication number
CN118231357A
CN118231357A CN202211641578.6A CN202211641578A CN118231357A CN 118231357 A CN118231357 A CN 118231357A CN 202211641578 A CN202211641578 A CN 202211641578A CN 118231357 A CN118231357 A CN 118231357A
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CN
China
Prior art keywords
layer
opening
chip
substrate
area
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Pending
Application number
CN202211641578.6A
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Chinese (zh)
Inventor
朱雅莉
王亚平
费春潮
黄婷婷
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202211641578.6A priority Critical patent/CN118231357A/en
Publication of CN118231357A publication Critical patent/CN118231357A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60225—Arrangement of bump connectors prior to mounting
    • H01L2021/60232—Arrangement of bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor chip

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A chip packaging method and a packaging structure, wherein the chip packaging method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of leading-out areas, and each leading-out area comprises a first area and a second area surrounding the first area; forming a first passivation layer on the substrate, the first passivation layer having a first opening located on the first region; forming a first welding pad layer on the surface of the first passivation layer on the lead-out area and in the first opening; forming a second passivation layer on the surfaces of the first passivation layer and the first bonding pad layer, wherein a second opening is formed in the second passivation layer, and the second opening exposes the first bonding pad layer on the first region and part of the second region; forming a buffer layer on the surface of the second passivation layer and the side wall of the second opening, wherein the buffer layer exposes the surface of the first welding pad layer on the first area; forming a conductive layer on the surface of part of the buffer layer and the first pad layer exposed by the buffer layer; and forming solder bumps on the conductive layer, so as to reduce layering of the first welding pad layer and the conductive layer.

Description

Chip packaging method and packaging structure
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a chip packaging method and a packaging structure.
Background
At present, three technologies for interconnecting integrated circuits are mainly used: wire Bonding (Wire Bonding), tape automated Bonding (Tape Automated Bonding), flip chip (Flip chip). In the flip chip technology, a chip functional area is downwards and reversely connected with a substrate through solder bumps (referred to as bumps) in a back-off way, and the placing direction of the chip is upwards opposite to that of a traditional packaging functional area, so that the flip chip is called. Flip-chip packaging has greatly increased the integration of electronic devices, and flip-chips have been known in recent years as a method of interconnecting high performance packages, and their use has been developed relatively widely and rapidly.
However, during packaging and subsequent reliability testing, thermal stresses can affect the solder under-bump Fang Yifa that connects the chip to the package substrate, affecting device performance and even causing failure.
Therefore, the existing chip packaging method needs to be further improved.
Disclosure of Invention
The invention solves the technical problem of providing a chip packaging method and a chip packaging structure so as to improve the reliability of packaging interconnection.
In order to solve the above technical problems, the present invention provides a chip packaging structure, including: the chip is provided with a functional surface and comprises a plurality of lead-out areas, wherein each lead-out area comprises a first area and a second area surrounding the first area; a first passivation layer on the functional side of the chip, the first passivation layer having a first opening therein on the first region; a first passivation layer surface on the lead-out region and a first pad layer within the first opening; a second passivation layer on the first passivation layer and the first pad layer, wherein a second opening is formed in the second passivation layer, and the second opening exposes the first pad layer on the first region and part of the second region; a buffer layer on the surface of the second passivation layer and the side wall of the second opening, wherein the buffer layer exposes the surface of the first pad layer on the first region; the conductive layer is positioned on part of the surface of the buffer layer and the first pad layer exposed by the buffer layer; and solder bumps on the conductive layer.
Optionally, the projection of the first opening on the surface of the chip is annular; the width of the area where the ring is positioned ranges from 3 mu m to 5 mu m; the first opening edge is in a size range of 5 μm to 10 μm from the second opening edge.
Optionally, the method further comprises: the substrate is provided with a second welding cushion layer on the surface; the chip is mutually fixed with the second welding pad layer through the solder bump.
Optionally, the solder bump includes a stud, an adhesion layer on the stud, and a solder layer on the adhesion layer.
Correspondingly, the technical scheme of the invention also provides a chip packaging method, which comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of lead-out areas, and each lead-out area comprises a first area and a second area surrounding the first area; forming a first passivation layer on the substrate, the first passivation layer having a first opening located on the first region; forming a first welding cushion layer on the surface of the first passivation layer on the lead-out area and in the first opening; forming a second passivation layer on the surfaces of the first passivation layer and the first bonding pad layer, wherein a second opening is formed in the second passivation layer, and the second opening exposes the first bonding pad layer on the first region and part of the second region; forming a buffer layer on the surface of the second passivation layer and the side wall of the second opening, wherein the buffer layer exposes the surface of the first welding pad layer on the first area; forming a conductive layer on a part of the surface of the buffer layer and the first pad layer exposed by the buffer layer; and forming a solder bump on the conductive layer.
Optionally, the projection of the first opening on the surface of the substrate is annular; the width of the area where the ring is positioned ranges from 3 mu m to 5 mu m; the first opening edge is in a size range of 5 μm to 10 μm from the second opening edge.
Optionally, the method further comprises: providing a substrate, wherein the surface of the substrate is provided with a second welding pad layer; dicing the substrate to form chips; and welding the solder bump of the chip towards the second welding pad layer, wherein the solder bump and the second welding pad layer are bonded to form a welding point.
Optionally, the solder bump includes a stud, an adhesion layer on the stud, and a solder layer on the adhesion layer.
Optionally, the projection of the second opening on the surface of the substrate is circular, elliptical or octagonal.
Optionally, the material of the first pad layer includes aluminum; the material of the buffer layer comprises epoxy resin.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the chip packaging method provided by the technical scheme of the invention, the first passivation layer surface on the lead-out area and the first opening are internally provided with the first welding cushion layer, so that the first welding cushion layer surface is not on the same horizontal plane, the contact interface between the first welding cushion layer and the conducting layer is increased, the combination capability of the first welding cushion layer and the conducting layer is further improved, and the layering phenomenon of the first welding cushion layer and the conducting layer is reduced.
Further, the projection of the first opening on the surface of the substrate is annular, the first opening enables the first pad layer to have an annular protrusion facing the surface of the substrate, the annular protrusion is arranged between a main contact interface of the first pad layer and the conductive layer and an initial layering interface (namely, a contact interface of the buffer layer and the first pad layer), layering problems are reduced, the layering problems are further extended from the initial layering interface to the main contact interface, and layering phenomena of the first pad layer and the conductive layer are further reduced.
In the chip packaging structure provided by the technical scheme of the invention, the surface of the first passivation layer positioned on the lead-out area and the first welding cushion layer positioned in the first opening are not positioned on the same horizontal plane, so that the contact interface between the first welding cushion layer and the conducting layer is increased, the combination capability of the first welding cushion layer and the conducting layer is further improved, and the layering phenomenon of the first welding cushion layer and the conducting layer is reduced.
Drawings
FIGS. 1 and 2 are schematic diagrams of a chip package structure;
Fig. 3 to 14 are schematic structural diagrams of steps in a chip packaging method according to an embodiment of the invention.
Detailed Description
As described in the background, with the existing chip package structure, performance needs to be improved. Analysis will now be described in connection with a chip package structure.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 and 2 are schematic diagrams of a chip package structure.
Referring to fig. 1 and 2, fig. 1 is a schematic cross-sectional structure, and fig. 2 is a schematic cross-sectional structure along the direction EE1 in fig. 1, the chip package structure includes: a chip, the chip includes a substrate 100, a pad layer 101 located on a part of the surface of the substrate 100, and a passivation layer 102 located on the surface of the substrate 100 and the pad layer 101, the passivation layer 102 has an opening (not shown in the figure) therein, and the opening exposes the surface of the pad layer 101; a buffer layer 103 located on the surface of the passivation layer 102, the side wall of the opening, and part of the surface of the pad layer 102; an under bump metallization layer 104 located at the bottom of the opening and on a portion of the surface of the buffer layer 103; a solder bump on the under bump metallization layer 104, the solder bump comprising a stud 105, an adhesion layer 106 on the stud 105, and a solder layer 107 on the adhesion layer 106.
In the flip chip packaging process, a packaging substrate is also provided, and the solder bumps of the chip packaging structure face the substrate to complete packaging. However, the above structure is affected by thermal stress during the packaging process and during the subsequent reliability test, resulting in a delamination phenomenon of the solder under bump Fang Yifa connecting the chip and the package substrate, specifically, being generated between the under bump metal layer 104 and the pad layer 101. When the delamination penetrates the entire interface between the under bump metallurgy layer 104 and the pad layer 101, electrical disconnection may be caused, resulting in device performance failure.
The layering phenomenon occurs because: the material of the buffer layer is epoxy resin, which is used for playing a buffering role between the solder pad layer 101 and the solder bump. However, in the process of forming the chip package structure, the buffer layer 103 may undergo a liquid-to-solid process during the forming process, and due to the difference of the thermal expansion coefficients of the buffer layer 103 and the pad layer 101, an initial delamination is generated at the interface a between the pad layer 101 and the buffer layer 103, and in the subsequent thermal process, the initial delamination may extend to the junction between the under bump metal layer 104 and the pad layer 101, and then extend toward the center of the pad layer 101 until penetrating through the interface between the whole under bump metal layer 104 and the pad layer 101.
In order to solve the above problems, in the chip packaging method and the packaging structure provided by the invention, a first pad layer is formed on the surface of the first passivation layer on the lead-out area and in the first opening, so that the surface of the first pad layer is not on the same horizontal plane, the contact interface between the first pad layer and the conductive layer is increased, the bonding capability between the first pad layer and the conductive layer is further improved, and the layering phenomenon of the first pad layer and the conductive layer is reduced.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 14 are schematic structural diagrams of steps in a chip packaging method according to an embodiment of the invention.
Referring to fig. 3, fig. 3 is a schematic top view of a structure, a substrate 200 is provided, the substrate 200 includes a plurality of lead-out regions, each of the lead-out regions includes a first region I and a second region II surrounding the first region I.
The first area I is used to define the position of the subsequent first opening.
In this embodiment, the substrate 200 is a wafer, and the chips are formed by dicing the wafer.
In this embodiment, the substrate 200 has a device structure therein, where the device structure includes one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure.
In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-V element comprises a multi-component semiconductor material comprising InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Referring to fig. 4 and 5, fig. 4 is a schematic top view, and fig. 5 is a schematic cross-sectional view along the DD1 direction in fig. 4, wherein a first passivation layer 201 is formed on the substrate 200, and the first passivation layer 201 has a first opening 202 therein located on the first region I.
A first pad layer 203 is formed on the surface of the first passivation layer 201 on the lead-out area and in the first opening 202, the surface of the first pad layer 203 is not on the same horizontal plane by the first opening 202, the contact interface between the first pad layer 203 and a conductive layer formed subsequently is increased, the bonding capability of the first pad layer 203 and the conductive layer is further improved, and the layering phenomenon of the first pad layer 203 and the conductive layer is reduced.
In this embodiment, the projection of the first opening 202 on the surface of the substrate 200 is annular. In other embodiments, the topography of the first opening may not be limited.
In this embodiment, the width d of the area where the ring is located is in the range of 3 μm to 5 μm.
The method for forming the first passivation layer 201 includes: forming a first passivation material layer (not shown) on the surface of the substrate 200; forming a first mask layer (not shown) on the first passivation material layer, the first mask layer exposing a portion of the first passivation material layer; and etching the first passivation material layer by taking the first mask layer as a mask.
Referring to fig. 6 and 7, fig. 6 is a schematic top view, and fig. 7 is a schematic cross-sectional view along the DD1 direction in fig. 6, wherein a first pad layer 203 is formed on the surface of the first passivation layer 201 and in the first opening 202 on the lead-out area.
In this embodiment, the material of the first pad layer 203 includes aluminum.
The forming method of the first pad layer 203 includes: forming a bonding pad material layer (not shown) on the surface of the first passivation layer 201 and in the first opening 202; forming a second mask layer (not shown) on the surface of the bonding pad material layer, wherein the second mask layer exposes part of the bonding pad material layer; and etching the bonding pad material layer by taking the second mask layer as a mask until the surface of the first passivation layer 201 is exposed.
In this embodiment, the projection of the first pad layer 203 on the surface of the substrate 200 is circular. In other embodiments, the projection of the first pad layer on the surface of the substrate may be circular, elliptical, or octagonal.
Referring to fig. 8 and 9, fig. 8 is a schematic top view, and fig. 9 is a schematic cross-sectional view along the DD1 direction in fig. 8, wherein a second passivation layer 204 is formed on the surfaces of the first passivation layer 201 and the first pad layer 203, and a second opening 205 is formed in the second passivation layer 204, and the second opening 205 exposes the first pad layer 203 on the first region I and a portion of the second region II.
The forming method of the second passivation layer 204 includes: forming a second passivation material layer (not shown) on the surfaces of the first passivation layer 201 and the first pad layer 203; forming a third mask layer (not shown) on the surface of the second passivation material layer, wherein the third mask layer exposes a part of the second passivation material layer; and etching the second passivation material layer until the first pad layer 203 is exposed by using the third mask layer as a mask.
In this embodiment, the dimension m of the edge of the first opening 202 from the edge of the second opening 205 ranges from 5 μm to 10 μm.
The projection of the second opening 205 on the surface of the substrate 200 is circular, elliptical or octagonal. In this embodiment, the projection of the second opening 205 on the surface of the substrate 200 is circular.
Referring to fig. 10 and 11, fig. 10 is a schematic top view, fig. 11 is a schematic cross-sectional view along the DD1 direction in fig. 10, a buffer layer 206 is formed on the surface of the second passivation layer 204 and the sidewalls of the second opening 205, and the buffer layer 206 exposes the surface of the first pad layer 203 on the first region I.
In this embodiment, the material of the buffer layer 206 includes epoxy. The buffer layer 206 is used for playing a role of buffering between the first pad layer 203 and the solder bump, and an initial delamination phenomenon is easy to occur at a contact interface between the buffer layer 206 and the surface of the first pad layer 203.
Referring to fig. 12 and 13, fig. 12 is a schematic top view, and fig. 13 is a schematic cross-sectional view along the DD1 direction in fig. 12, wherein a conductive layer 207 is formed on a portion of the surface of the buffer layer 206 and the first pad layer 203 exposed by the buffer layer 206.
In this embodiment, the projection of the first opening 202 on the surface of the substrate 200 is annular, so that the first pad layer 203 has an annular protrusion T facing the surface of the substrate 200, and the annular protrusion T is disposed between the primary contact interface Z1 of the first pad layer 203 and the conductive layer 207 and the initial delamination interface Z2 (i.e. the contact interface between the buffer layer 206 and the first pad layer 203), which is beneficial to reducing delamination problems from the initial delamination interface to the primary contact interface, thereby reducing delamination phenomena of the first pad layer 203 and the conductive layer 207.
In this embodiment, the projection of the first opening 202 on the surface of the substrate 200 is annular, so that the first pad layer has an annular protrusion facing the surface of the substrate 200, and the occurrence of delamination between the first pad layer 203 and the conductive layer can be reduced from the periphery, which is a more optimal solution. In other embodiments, the morphology of the first opening is not limited, so that the contact interface between the first pad layer and the conductive layer can be increased, the bonding capability of the first pad layer and the conductive layer is improved, and the layering phenomenon of the first pad layer and the conductive layer is reduced.
The conductive layer 207 is used as a metal layer under the solder bump, and is used as a bonding layer between the solder bump and the first pad layer 203, and is the basis for low-resistance electrical, mechanical and thermal connection between the chip and the substrate.
The material of the conductive layer 207 is metal.
With continued reference to fig. 14 on the basis of fig. 13, solder bumps are formed on the conductive layer 207.
In this embodiment, the solder bump includes a bump 208, an adhesion layer 209 on the bump 208, and a solder layer 210 on the adhesion layer 209.
In this embodiment, the material of the stud 208 is copper; the adhesion layer 209 is made of nickel; the material of the solder layer 210 is tin.
Subsequently, further comprising: providing a substrate (not shown) with a second pad layer (not shown) on the surface of the substrate; dicing the substrate 200 to form chips (not shown); and welding the solder bump of the chip towards the second welding pad layer, wherein the solder bump and the second welding pad layer are bonded to form a welding point (not shown in the figure).
Correspondingly, the embodiment of the invention also provides a chip packaging structure formed by adopting the method, please continue to refer to fig. 14, which comprises the following steps: a chip (not shown in the figure) having a functional surface, the chip comprising a plurality of extraction areas, each of the extraction areas comprising a first area I and a second area II surrounding the first area I; a first passivation layer 201 on the functional surface of the chip, wherein the first passivation layer 201 has a first opening 202 (as shown in fig. 5) located on the first region I; a first passivation layer 201 surface on the lead-out region and a first pad layer 203 within the first opening 202; a second passivation layer 204 located on the surface of the first passivation layer 201 and the first pad layer 203, where the second passivation layer 204 has a second opening 205 (as shown in fig. 9), and the second opening 205 exposes the first pad layer 203 on the first region I and a part of the second region II; a buffer layer 206 located on the surface of the second passivation layer 204 and on the side wall of the second opening 205, wherein the buffer layer 206 exposes the surface of the first pad layer 203 on the first region I; a conductive layer 207 on a portion of the surface of the buffer layer 206 and on the first pad layer 203 exposed by the buffer layer 206; solder bumps on the conductive layer 207.
The surface of the first passivation layer 201 on the lead-out area and the first pad layer 203 in the first opening 202 are not on the same horizontal plane, so that the contact interface between the first pad layer 203 and a conductive layer formed subsequently is increased, the bonding capability of the first pad layer 203 and the conductive layer is further improved, and the layering phenomenon of the first pad layer 203 and the conductive layer is reduced.
In this embodiment, the projection of the first opening 202 on the surface of the chip is annular. As shown in fig. 12 and 13, the projection of the first opening 202 on the surface of the substrate 200 is annular, so that the first pad layer 203 has an annular protrusion T facing the surface of the substrate 200, and the annular protrusion T is disposed between the primary contact interface Z1 of the first pad layer 203 and the conductive layer 207 and the initial delamination interface Z2 (i.e., the contact interface between the buffer layer 206 and the first pad layer 203), so as to facilitate reducing delamination problems from the initial delamination interface to the primary contact interface, thereby reducing occurrence of delamination phenomena of the first pad layer 203 and the conductive layer 207.
In this embodiment, the width d of the area where the ring is located is in the range of 3 μm to 5 μm.
In this embodiment, the dimension m of the edge of the first opening 202 from the edge of the second opening 205 ranges from 5 μm to 10 μm.
In this embodiment, the method further includes: a substrate (not shown) having a second pad layer (not shown) on a surface thereof; the chip is mutually fixed with the second welding pad layer through the solder bump.
In this embodiment, the solder bump includes a bump 208, an adhesion layer 209 on the bump 208, and a solder layer 210 on the adhesion layer 209.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A chip package structure, comprising:
the chip is provided with a functional surface and comprises a plurality of lead-out areas, wherein each lead-out area comprises a first area and a second area surrounding the first area;
A first passivation layer on the functional side of the chip, the first passivation layer having a first opening therein on the first region;
A first passivation layer surface on the lead-out region and a first pad layer within the first opening;
a second passivation layer on the first passivation layer and the first pad layer, wherein a second opening is formed in the second passivation layer, and the second opening exposes the first pad layer on the first region and part of the second region;
A buffer layer on the surface of the second passivation layer and the side wall of the second opening, wherein the buffer layer exposes the surface of the first pad layer on the first region;
The conductive layer is positioned on part of the surface of the buffer layer and the first pad layer exposed by the buffer layer;
and solder bumps on the conductive layer.
2. The chip package structure of claim 1, wherein a projection of the first opening on the chip surface is annular; the width of the area where the ring is positioned ranges from 3 mu m to 5 mu m; the first opening edge is in a size range of 5 μm to 10 μm from the second opening edge.
3. The chip package structure of claim 1, further comprising: the substrate is provided with a second welding cushion layer on the surface; the chip is mutually fixed with the second welding pad layer through the solder bump.
4. The chip package structure of claim 1, wherein the solder bump comprises a stud, an adhesion layer on the stud, and a solder layer on the adhesion layer.
5. A method of packaging a chip, comprising:
providing a substrate, wherein the substrate comprises a plurality of lead-out areas, and each lead-out area comprises a first area and a second area surrounding the first area;
forming a first passivation layer on the substrate, the first passivation layer having a first opening located on the first region;
Forming a first welding cushion layer on the surface of the first passivation layer on the lead-out area and in the first opening;
Forming a second passivation layer on the surfaces of the first passivation layer and the first bonding pad layer, wherein a second opening is formed in the second passivation layer, and the second opening exposes the first bonding pad layer on the first region and part of the second region;
Forming a buffer layer on the surface of the second passivation layer and the side wall of the second opening, wherein the buffer layer exposes the surface of the first welding pad layer on the first area;
forming a conductive layer on a part of the surface of the buffer layer and the first pad layer exposed by the buffer layer;
And forming a solder bump on the conductive layer.
6. The chip packaging method according to claim 5, wherein a projection of the first opening on the substrate surface is annular; the width of the area where the ring is positioned ranges from 3 mu m to 5 mu m; the first opening edge is in a size range of 5 μm to 10 μm from the second opening edge.
7. The chip packaging method according to claim 5, further comprising: providing a substrate, wherein the surface of the substrate is provided with a second welding pad layer; dicing the substrate to form chips; and welding the solder bump of the chip towards the second welding pad layer, wherein the solder bump and the second welding pad layer are bonded to form a welding point.
8. The chip packaging method of claim 5, wherein the solder bump comprises a stud, an adhesion layer on the stud, and a solder layer on the adhesion layer.
9. The chip packaging method according to claim 5, wherein a projection of the second opening on the surface of the substrate is circular, elliptical or octagonal.
10. The chip packaging method of claim 5, wherein the material of the first pad layer comprises aluminum; the material of the buffer layer comprises epoxy resin.
CN202211641578.6A 2022-12-20 2022-12-20 Chip packaging method and packaging structure Pending CN118231357A (en)

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