CN114983425A - Neural signal detection circuit for outputting time difference data or neural data - Google Patents

Abstract

A neural signal detection circuit capable of outputting time difference data or neural data comprises a first time circuit and a second time circuit. The first time circuit is used for storing the detection voltage energy in a first period and a second period as the time difference data. The second time circuit is used for storing the detected voltage energy in the second period as the neural data. The neural signal detection circuit is used for outputting the time difference data or the neural data under different operation modes.

Description

Neural signal detection circuit for outputting time difference data or neural data

Technical Field

The present invention relates to a detection circuit, and more particularly, to a neural signal detection circuit that can selectively output a pulse width signal corresponding to time difference data and/or neural data.

Background

With the development of neuroscience, cognitive psychology, and artificial intelligence research, electroencephalogram (EEG) signals are increasingly being applied to the fields of medical diagnosis and neurobiology.

Generally, electrodes may be used to acquire voltage signals as the electroencephalogram signals.

Electrodes that can be used to collect voltage signals include dry electrodes and wet electrodes. Since no conductive medium is required for detection using dry electrodes, the complexity of preparation for detection is significantly reduced and the preparation time can be shortened, compared to detection using wet electrodes.

Since electroencephalogram signals are in the millivolt range, how to accurately and quickly acquire clean electroencephalogram signals is a problem. Furthermore, analyzing and processing the acquired voltage signal is another problem.

Disclosure of Invention

The invention provides a neural signal detection circuit capable of outputting time difference data and/or neural data.

The invention provides a neural signal detection circuit comprising an electrode, a first time circuit, a second time circuit, a first comparator and a second comparator. The electrodes are used to generate a detection voltage. The first time circuit includes a first capacitor having a first end coupled to the electrode. The second time circuit includes a second capacitor having a first end coupled to the electrode. The first comparator includes a first input transistor and a second input transistor. The first input transistor is configured in the first time circuit and connected to the second end of the first capacitor. The second input transistor is configured outside the first time circuit and is shared with other neural signal detection circuits. The second comparator includes a third input transistor and a fourth input transistor. The third input transistor is configured in the second time circuit and connected to the second end of the second capacitor. The fourth input transistor is configured outside the second time circuit and is shared with the other neural signal detection circuits.

The invention also provides a neural signal detection circuit comprising the electrode, the first time circuit and the second time circuit. The electrodes are used to generate a detection voltage. The first time circuit includes a first capacitor having a first end coupled to the electrode. The second time circuit includes a second capacitor having a first end coupled to the electrode. The second end of the first capacitor is coupled to the inverting input terminal of a first comparator, and the first comparator is configured outside the neural signal detection circuit and shared by the first time circuit and other neural signal detection circuits. The second end of the second capacitor is coupled to the inverting input terminal of a second comparator, and the second comparator is configured outside the neural signal detection circuit and shared by the second time circuit and the other neural signal detection circuits.

The invention also provides a neural signal detection circuit comprising the source follower, the first time circuit and the second time circuit. The first time circuit comprises a first capacitor having a first end coupled to the source follower. The second time circuit comprises a second capacitor having a first end coupled to the source follower. The second end of the first capacitor is coupled to the inverting input terminal of a first comparator, and the first comparator is configured outside the neural signal detection circuit and shared by the first time circuit and other neural signal detection circuits. The second end of the second capacitor is coupled to the inverting input terminal of a second comparator, and the second comparator is configured outside the neural signal detection circuit and shared by the second time circuit and the other neural signal detection circuits.

In the present invention, the electrode is selected from the group consisting of a dry electrode and a wet electrode. In one embodiment, the detection voltage generated by the electrodes is first amplified and filtered and then transferred to the time circuit.

In order that the manner in which the above recited and other objects, features and advantages of the present invention are obtained will become more apparent, a more particular description of the invention briefly described below will be rendered by reference to the appended drawings. In the description of the present invention, the same components are denoted by the same reference numerals, and the description thereof is made herein.

Drawings

FIG. 1 is a block diagram of a circuit architecture of a neural signal detection circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a neural signal detection circuit of an embodiment of the present invention;

FIG. 3 is a circuit diagram of a timing circuit of the neural signal detecting circuit of the embodiment of the present invention;

FIG. 4A is a timing diagram of the operation of the timing circuit of FIG. 3;

FIG. 4B is a timing diagram illustrating the operation of the neural signal detection circuit of FIG. 2;

FIG. 5 is a circuit diagram of a subtraction circuit of the neural signal detection circuit of an embodiment of the present invention;

FIG. 6 is a circuit diagram of an addition circuit of the neural signal detecting circuit of the embodiment of the present invention;

FIG. 7 is a circuit diagram of an absolute difference circuit of the neural signal detecting circuit of the embodiment of the present invention;

FIG. 8 is a circuit diagram of a recursive operation circuit of the neural signal detecting circuit of the embodiment of the present invention;

FIG. 9 is a run-time sequence diagram of the recursive computation circuit of FIG. 8;

FIG. 10 is a schematic diagram of one application of a neural signal detection circuit of an embodiment of the present invention;

11A-11C are flow diagrams of different modes that can be performed using neural signal detection circuitry according to embodiments of the present invention;

FIG. 12 is a schematic diagram of a neural signal detection circuit outputting time differential data or neural data using an embodiment of the present invention;

FIG. 13 is a signal timing diagram of the neural signal detection circuit of FIG. 12;

FIG. 14 is a schematic diagram of a time differential detection using a detection array of the neural signal detection circuit of an embodiment of the present invention;

FIG. 15 is a circuit diagram of a modification I of the neural signal detecting circuit of the present invention;

FIG. 16 is a signal timing diagram of the neural signal detection circuit of FIG. 15;

fig. 17 is a circuit diagram of a modification II of the neural signal detecting circuit of the present invention;

fig. 18 is a circuit diagram of a modification III of the neural signal detecting circuit of the present invention; and

fig. 19 is a circuit diagram of a modification IV of the neural signal detecting circuit of the present invention.

Description of the reference numerals

10. 200 neural signal detection circuit

12 arithmetic circuit

14 judging circuit

2a first time circuit

2b second time circuit

SWrst reset transistor

SWt transfer transistor

A first detection signal

B second detection signal

Pulse widths of T1 and T2

Detailed Description

The present invention relates to a neural signal detection circuit for performing analog operation on a neural signal. Each detection circuit outputs a detection signal having a pulse width corresponding to the detection voltage. The operation circuit performs an analog operation on a pulse width signal (pulse width signal). The voltage value after the analog operation can be converted into a pulse width signal through a voltage-time conversion circuit, and then the next analog operation is carried out by the same or other operation circuits. Therefore, all data operations can be completed in the analog stage without first converting into digital data.

Fig. 1 is a block diagram of a circuit architecture of a neural signal detecting circuit (sometimes referred to as a detecting circuit) according to an embodiment of the present invention. The circuit architecture includes a neural signal detection circuit 10 and an arithmetic circuit 12. The neural signal detecting circuit 10 is used for outputting detection signals of different periods, for example, the detection signals of different periods are represented by signal a and signal B in fig. 1. In the present invention, the detection signals a and B respectively represent the magnitude of the voltage energy detected by the neural signal detecting circuit 10 by the pulse widths T1 and T2, wherein the larger the detected voltage energy is, the wider the pulse width of the corresponding detection signal a or B is.

The operation circuit 12 includes any circuit for performing an operation between signals, such as the subtraction circuit of fig. 5, the addition circuit of fig. 6, and the absolute difference circuit of fig. 7, but not limited thereto. In a detection array including a plurality of detection circuits, the arithmetic circuit 12 may be disposed in each of the detection circuits to process data in the detection circuits or disposed between the detection circuits to process data between the detection circuits.

In some embodiments, the circuit architecture may further include a determination circuit 14, and the determination circuit 14 includes, for example, a comparator for comparing the output result of the operation circuit 12 with a predetermined threshold value to determine the operation state of the device applying the circuit architecture of the present invention. For example, the determination circuit 14 may be used to determine whether the electrode is picked up. The output result of the arithmetic circuit 12 represents the voltage energy change, and when the judgment circuit 14 judges that the voltage energy change is larger than or smaller than the threshold value, the electrode is judged to be picked up. The determining circuit 14 then outputs a control signal to perform corresponding control, such as outputting a voltage signal, but not limited thereto.

Fig. 2 is a circuit diagram of a neural signal detecting circuit 200 according to an embodiment of the present invention. The neural signal detecting circuit 200 is used to output a pulse width signal A, B, i.e., a detection signal. The neural signal detecting circuit 200 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first time circuit 2a and a second time circuit 2b connected to a node V _FD 。

The electrode ED is used to generate a detection voltage. The detection voltage is passed through a transfer transistor SWt to be stored in the first time circuit 2a and the second time circuit 2b at different periods (e.g., controlled by a control signal TX), respectively. In the present invention, the first time circuit 2a and the second time circuit 2B are used to store the voltage energy detected in different periods, and also convert the stored voltage energy into the detection signals a and B with corresponding pulse widths (e.g. T1 and T2) respectively for the analog operation of the operation circuit 12. The first time circuit 2a and the second time circuit 2b have the same circuit configuration and differ only in operation period.

The first time circuit 2a is in the firstTime period (e.g., see T shown in FIG. 4B) _SA ) The first detection voltage (e.g. V shown in FIG. 4B) generated by the storage electrode ED _SIG1 ) And during operation (e.g., see T shown in FIG. 4B) _O1 ) According to the first detection voltage V _SIG1 The first detection signal a having the first pulse width T1 is output.

The second time circuit 2B is in the second period (for example, refer to T shown in FIG. 4B _SB ) The second detection voltage (e.g. V shown in FIG. 4B) generated by the storage electrode ED _SIG2 ) And during the operation period T _O1 According to the second detection voltage V _SIG2 The second detection signal B having the second pulse width T2 is output. It should be understood that the lengths of T1 and T2 are only exemplary and not intended to limit the present invention.

The reset transistor SWrst is coupled to a voltage source V _DD And node V _FD For a first period T _SA Resetting the first time circuit 2a and during a second period T _SB The second time circuit 2b is reset.

A transfer transistor SWt coupled between the electrode ED and the node V _FD For a first period T _SA The first detection voltage V _SIG1 Transferred to the first time circuit 2a for storage, and during a second period T _SB The second detection voltage V _SIG2 Transferred to the second time circuit 2b for storage. Therefore, the neural signal detecting circuit 200 can be used to store the detected voltage energy in different periods to represent the change of the detected neural signal with time.

In some embodiments, the first timing circuit 2a further includes a first inverter INV1 coupled between the output terminal of the first timing circuit 2a and the operation circuit 12 for inverting the first detection signal a; the second time circuit 2B further includes a second inverter INV2 coupled between the output terminal of the second time circuit 2B and the operation circuit 12 for inverting the second detection signal B. In other embodiments, the first inverter INV1 and the second inverter INV2 are disposed in the operation circuit 12, but not in the first time circuit 2a and the second time circuit 2 b.

Referring to fig. 3 and fig. 4A, fig. 3 is a circuit diagram of a timing circuit (e.g., 2a and 2b) of the neural signal detecting circuit according to the embodiment of the present invention; fig. 4A is a run-time sequence diagram of the time circuit 2a/2b of fig. 3. It should be noted that although fig. 2 shows that a single neural signal detection circuit includes two time circuits, the invention is not limited thereto. In other embodiments, each neural signal detection circuit comprises a single time circuit as in fig. 3 to output a pulse width signal a or B.

In the present invention, the operation of the timing circuits 2a and 2b of fig. 2 is described with reference to fig. 3 and 4A.

The time circuits 2a and 2b respectively include a storage capacitor C, a first transistor SW1, a second transistor SW2, and a third transistor SW 3. The storage capacitor and the first to third transistors are respectively denoted by different reference numerals in fig. 2 to separate the associated time circuits.

A first terminal of a storage capacitor C (shown as a first capacitor C1 in the first time circuit 2a and a second capacitor C2 in the second time circuit 2b) is connected to the reset transistor SWrst, and the storage capacitor C is used for storing voltage energy generated by the electrode ED, such as a first detection voltage V _SIG1 Or a second detection voltage V _SIG2 。

The first transistor SW1 (shown as SWa1 in the first time circuit 2a and SWb1 in the second time circuit 2b) is coupled to the voltage source V _DD And node V _X Which is controlled by a control signal BIAS (shown as BIAS1 in the first time circuit 2a and BIAS2 in the second time circuit 2B) to convert the stored voltage energy into a detection signal, such as a first detection signal a or a second detection signal B.

The second transistor SW2 (shown as SWa2 in the first time circuit 2a and SWb2 in the second time circuit 2b) is coupled between the storage capacitor C and the first transistor SW1 and is controlled by a control signal AZ (shown as AZ1 in the first time circuit 2a and AZ2 in the second time circuit 2 b). During a first period T _SA The second transistor SWb2 is turned off to avoid changing the stored energy in the second capacitor C2. During a second period T _SB In this case, the second transistor SWa2 is turned off to avoid changing the energy stored in the first capacitor C1.

The third transistor SW3 (shown as SWa3 in the first time circuit 2a and SWb3 in the second time circuit 2b) is coupled between the second terminal of the storage capacitor C and the ground voltage.

Referring again to FIG. 4A, the operation of the timing circuits 2a/2b is shown to include a reset period, an energy transfer period, an energy storage period, and a transfer pulse period. During the RESET period, the control signals BIAS, RESET and AZ are high level to RESET the potential on the storage capacitor C, such as the node V _FD Is reset to V _RESET (e.g. equal to V) _DD ) And node V _G Is reset to V _AZ . During the energy transfer, the control signal RESET changes to the low level, and when the control signal TX changes to the high level, the voltage energy V detected by the electrode ED _SIG Transferred to node V through transfer transistor SWt _FD So that the potential on it is increased to V _RESET +V _SIG In which V is _SIG Representing the detected voltage energy. During the energy storage period, the control signal RESET changes to the high level again and the control signals BIAS and AZ change to the low level to change the voltage energy V _SIG Store to node V _G To reduce the potential thereon to V _AZ -V _SIG . At this time, if the control signal AZ is maintained at the low level to turn off the second transistor SW2, the potential of the storage capacitor C is substantially maintained.

In fig. 4A, the reset period, the energy transfer period, and the energy storage period are collectively used as the energy storage period T of the first time circuit 2a _SA Or as an energy storage period T of the second time circuit 2b _SB . Before the operation of the operation circuit 12 is started, the first time circuit 2a and the second time circuit 2b sequentially store the voltage energy detected by the electrode ED. As shown in FIG. 4A, the first detection voltage V in the first time circuit 2a enters the pulse transition period after the operation is started _SIG1 Is converted into the first detection signal a and the second detection voltage V in the second time circuit 2b _SIG2 Is converted into a second detection signal B.

During the pulse transition period, the control signal BIAS uses a ramp signal (ramp signal) whose voltage level decreases with time. When the BIAS signal begins to change to the high level (e.g. V) _{BIAS_AZ} ) While flowing through the firstThe current I1 of the transistor SW1 is smaller than the current I3 flowing through the third transistor SW3, so that the output voltage V is increased _X Is at the low level. As the voltage level of the control signal BIAS gradually decreases, the current I1 gradually increases until the current I1 is substantially equal to the current I3, and the output voltage V is then increased _X Changes to high level to form negative pulse width signal. When the output voltage V is _X After passing through the inverter INV, a positive pulse width signal can be generated as shown in FIG. 4A, wherein the pulse width Δ T and the voltage energy V _SIG And are in positive correlation. Thus, the time circuits 2a and 2b of the embodiment of the present invention convert the voltage energy detected by the electrode ED into a time signal for the operation circuit 12 to perform the operation.

Fig. 4B is a timing diagram illustrating the operation of the neural signal detecting circuit 200 shown in fig. 2. The first time circuit 2a is in a first period (e.g. energy storage period T) _SA ) Storing the first detection voltage V according to the operation mode of FIG. 4A _SIG1 To the first capacitor C1. The second time circuit 2b is in a second period (e.g. energy storage period T) _SB ) Storing the second detection voltage V according to the operation mode of FIG. 4A _SIG2 To the second capacitor C2. Then, during the first operation period T _O1 The first time circuit 2a uses a ramp signal with a decreasing voltage level with time as the control signal BIAS1 to detect the first detection voltage V _SIG1 Converts into the first detection signal A, and the second time circuit 2b uses the ramp signal whose voltage level decreases with time as the control signal BIAS2 to output the second detection voltage V _SIG2 Converted into a second detection signal B. Preferably, the ramp signals BIAS1 and BIAS2 are substantially in-phase (in-phase) to generate the detection signals a and B substantially simultaneously, but are not limited thereto. The detection signals A and B can be sequentially generated according to the operation performed by the operation circuit 12. The operation circuit 12 is in the first operation period T _O1 The first detection signal a and the second detection signal B are subjected to numerical calculation, such as addition, subtraction, and absolute difference operations as exemplified in the present invention, but the present invention is not limited to these operations.

As shown in FIG. 4B, during the first operation period T _O1 Stores the first detection voltage V _SIG1 First period T of _SA Prior to storing the second detection voltage V _SIG2 Second period T of _SB 。

In one embodiment, during the first operation period T _O1 After the end, the second time circuit 2b continues to store the second detection voltage V _SIG2 First time circuit 2a during the next energy storage period T _SA ' the next first test voltage V is stored in the operating mode likewise in accordance with FIG. 4A _SIG1 ' to the first capacitor C1. Then, during a second operation period T _O2 The first time circuit 2a uses a ramp signal with a decreasing voltage level with time as the control signal BIAS1 to detect the first detection voltage V _SIG1 'convert to the first detection signal A', while the second time circuit 2b uses the ramp signal with the voltage level decreasing with time as the control signal BIAS2 to detect the second detection voltage V _SIG2 Is converted into a second detection signal B which is approximately the same as the first operation period T _O1 The generated signal. The operation circuit 12 is in the second operation period T _O2 The first detection signal a' and the second detection signal B are numerically calculated. During the second operation T _O2 In the first step, the first detection voltage V is stored _SIG1 ' first period T _SA Later than storing the second detection voltage V _SIG2 Second period T of _SB 。

During the next energy storage period, the first detection voltage V of the first time circuit 2a is maintained _SIG1 And updates the second detection voltage of the second time circuit 2b to V _SIG2 '. As shown in fig. 4B, the voltage energies stored in the first time circuit 2a and the second time circuit 2B are repeatedly updated, so that the numerical calculation can be performed for signals at different times.

Fig. 5 is a circuit diagram of a subtracting circuit 500 according to an embodiment of the invention, which has two input terminals respectively coupled to a first timing circuit 2a and a second timing circuit 2B for respectively receiving a first detecting signal a having a first pulse width T1 and a second detecting signal B having a second pulse width T2. The subtraction circuit 500 includes an operation capacitor Co and a first operation transistor SWA and a second operation transistor SWB connected in series, wherein the operation capacitor Co is connected between the first operation transistor SWA and the second operation transistor SWB. The first operation transistor SWA is used as a switch to control the charging time of the first current Ic to the operation capacitor Co according to the first pulse width T1; the second operation transistor SWB is used as a switch to control the discharge time of the second current Id to the operation capacitor Co according to the second pulse width T2, wherein the first current Ic is substantially equal to the second current Id. Thus, the subtraction circuit 500 can perform the numerical calculation of A-B. It can be appreciated that when the subtraction circuit 500 is used to perform the numerical calculation of B-a, the input signals received by the gates of the first and second operation transistors SWA and SWB are opposite, which can be realized by a switching element or a multiplexer, for example.

Fig. 6 is a circuit diagram of an adder circuit 600 according to an embodiment of the invention, which has two input terminals respectively coupled to a first timing circuit 2a and a second timing circuit 2B for respectively receiving a first detection signal a having a first pulse width T1 and a second detection signal B having a second pulse width T2. The adder circuit 600 includes an operational capacitor Co connected between a first operational transistor SWA and a second operational transistor SWB, and the first operational transistor SWA and the second operational transistor SWB connected in parallel. The first operational transistor SWA is used as a switch to control a first charging time of the first current Ic1 to the operational capacitor Co according to the first pulse width T1; the second operation transistor SWB is used as a switch to control the second charging time of the second current Ic2 to the operation capacitor Co according to the second pulse width T2, wherein the first current Ic1 is substantially equal to the second current Ic 2. Thus, the adder circuit 600 can perform the numerical calculation of a + B.

Referring to fig. 7, a circuit diagram of an absolute differential circuit 700 according to an embodiment of the invention is shown, which has two sets of input terminals respectively coupled to the first time circuit 2a and the second time circuit 2b for receiving a first detection signal A, Abar with a first pulse width T1 and a second detection signal B, Bbar with a second pulse width T2, wherein Abar and Bbar can be generated from A, B or vice versa using an inverter, respectively. When the first pulse width T1 is greater than the second pulse width T2, the pulse width signals a and Bbar are received by the first set of input terminals (including the operation transistors SWA and SWBbar) to control the first charging time of the operation capacitor Co by the first current Ic 1. When the first pulse width T1 is smaller than the second pulse width T2, the pulse width signals B and Abar are received by the second set of input terminals (including the operation transistors SWB and SWAbar) to control the second charging time of the second current Ic2 to the operation capacitor Co. Thus, the absolute difference circuit 700 can perform numerical calculation of | A-B |.

Although the current sources of fig. 5-7 are shown as being implemented with a control signal PBIAS control transistor, the invention is not so limited. Other current sources may also be used.

Referring to fig. 8, which is a circuit diagram of a recursive operation circuit 800 of the detection circuit according to the embodiment of the present invention, the recursive operation circuit 800 is connected to the operation circuit 12 for controlling the operation timing of the operation circuit 12 and converting the operation result (i.e. the potential stored in the operation capacitor Co) into a pulse width signal again for the next operation, for example, the pulse width output of the recursive operation circuit 800 is connected to one signal input terminal of the operation circuit 12 as the signal a or B in fig. 5 to 7.

The recursive operation circuit 800 includes a first recursive transistor SWr1, a second recursive transistor SWr2, and a third recursive transistor SWr3, which are connected in the same manner as the first transistor SW1, the second transistor SW2, and the third transistor SW3 of fig. 3.

In fig. 8, the circuit within the dashed line box 81 can be referred to as a voltage-time conversion circuit, for example, for converting the voltage of the operation capacitor Co into the pulse width signals as a and B, wherein the operation capacitor Co in fig. 8 is the operation capacitor Co in fig. 5 to 7.

Referring to fig. 9, a timing diagram of the operation of the recursive operation circuit 800 of fig. 8 is shown. Before the first and second detection signals a and B output by the first and second timing circuits 2a and 2B are numerically calculated by using the operation capacitor Co, the operation capacitor Co is reset. During the operation reset period, the control signals AZr and BIASr change to high level for resetting the potential of the operation capacitor Co to V _AZ . In the present embodiment, the second recursion transistor SWr2 functions as an operation reset transistor to reset the potential of the operation capacitor Co during the operation reset period. During the period of numerical calculation (for example, the hatched portion), the control signal AZr changes to the low levelThe bit, the operation result of the operation circuit 12 is stored in the operation capacitor Co to cause the potential thereof to change, wherein the magnitude of the potential change is correlated with the operation result. Then, during the energy storage period, the operation capacitor Co keeps holding the operated potential until the next operation is started, and the voltage-time conversion circuit 81 converts the operated potential into a pulse width signal for the operation circuit 12 to operate. The operation of the recursive operation circuit 800 during the energy storage period and the pulse transition period is the same as the operation of the energy storage period and the pulse transition period in fig. 4A, for example, a ramp signal is used to generate the pulse width signal, and therefore, the description thereof is omitted.

In one embodiment, the recursive operation circuit 800 may further include an inverter INV for inverting the output pulse width signal. However, when the operation circuit 12 includes an inverter, the recursive operation circuit 800 does not include the inverter INV.

In the present invention, the transition pulse period of fig. 4A, the operation reset period of fig. 9 and the numerical calculation period may be collectively referred To as an operation period To, wherein the operation of the operation reset period of fig. 9 may be performed simultaneously with or may be performed subsequently To the operation of the transition pulse period of fig. 4A.

It is understood that if the recursive computation circuit 800 does not need to perform the next operation thereafter, the recursive computation circuit 800 may directly provide (e.g., control through a switch element) the calculated potential of the computation capacitor Co to the judgment circuit 14 for judgment, for example, compare with the reference potential through a comparator.

The circuit of fig. 8 is referred to as a recursive operation circuit in the present invention because the operation result of the operation circuit 12 can be stored and converted into a pulse width signal through the recursive operation circuit 800 for multiple times of recursive operations. That is, the arithmetic circuit 12 can calculate not only the detection result of the electrode ED but also the arithmetic result of itself and the arithmetic result of another detection circuit again.

Thus, by using the neural signal detection circuit 200 of fig. 2 in combination with the recursive computation circuit 800 of fig. 8, various operations can be directly performed on neural data at an analog level to perform various applications, and the determination circuit 14 performs various determinations, for example, a determination of lifting of an electrode, a multi-layer neural network operation, and the like, directly on the basis of the final computation result of the neural signal detection circuit 200 in combination with the recursive computation circuit 800, thereby realizing a circuit architecture for in-circuit computation.

For example, referring to fig. 10, a schematic diagram of the neural signal detecting circuit of the present invention applied to array detection is shown. The detection array includes a plurality of detection circuits arranged in an array, and the judgment circuit 14 performs detection including a circuit 0 to a circuit 8, for example, based on 9 detection circuits adjacent to each other, where the circuit 0 is an intermediate detection circuit of the circuits 1 to 8. In the present embodiment, the circuits 0 to 8 include the neural signal detection circuit 200 and/or the at least one arithmetic circuit 12 of fig. 2, respectively.

As described above, the circuits 0 to 8 generate the first detection signals A0 to A8 and the second detection signals B0 to B8, respectively. The first detection signals a 0-A8 and the second detection signals B0-B8 of the circuits 0-8 are numerically calculated by a subtraction circuit 500 (for example, but not limited to, included in the neural signal detection circuits of the circuits 0-8), and the subtraction results of Y0-Y8 can be obtained respectively and stored in a corresponding operation capacitor Co (for example, Co in fig. 8), wherein Y0-Y8 represents that each circuit 0-8 can perform time difference operation of detection signals in different detection periods to represent the voltage energy change detected by each detection circuit.

Then, after Y0 to Y8 are converted into pulse width signals by the recursive computation circuit 800, Y01 to Y08 are obtained by performing numerical computation of absolute differences for Y0 and Y1, Y0 and Y2, …, and Y0 and Y8, respectively, by the absolute difference circuit 700, where Y01 to Y08 indicate that the detection arrays perform spatial difference computation between different detection circuits, and Y01 to Y08 include computation results of temporal and spatial differences.

Finally, Y01 to Y08 are summed up by the adder circuit 600. Similarly, Y01 to Y08 are stored in the corresponding operation capacitors Co, and then converted into pulse width signals by the voltage-time conversion circuit 81 for addition by the addition circuit 600.

In one embodiment, the adder circuit 600 comprises two signal inputs as shown in FIG. 6, for performing the storage and voltage-to-time conversion after each addition of two of Y01-Y08, and then performing the addition with the remaining next one of Y01-Y08 until all additions are completed.

In another embodiment, the summing circuit comprises 8 inputs and uses the pulse width associated with Y01-Y08 to control the charging time of the respective current source to the computing capacitor to sum Y01-Y08.

The judgment circuit 14 receives the addition result of the addition circuit 600, and compares the sum with a predetermined threshold value (for example, using a comparator). When the sum of Y01-Y08 is greater than or equal to a predetermined threshold, it indicates that a electroencephalogram change is detected.

In another embodiment, the determination circuit 14 receives the sum of the time differences Y0 to Y8 (e.g., Y0 to Y8 output directly from circuit 0 to circuit 8 to the addition circuit 600), and when the sum is greater than or less than the threshold, it indicates that the electrode is picked up.

It can be understood that fig. 10 is a diagram illustrating the detection of the brain electrogram or the picking-up detection by the temporal and spatial brightness changes detected by the 9 adjacent detection circuits, but the invention is not limited thereto. The judgment circuit 14 can detect the voltage variation in time and space according to the appropriate number of detection circuits, and it can be set according to the detection environment and the size of the detection array.

The neural signal detecting circuit 200 in fig. 2 can operate in different modes according to different control signals, including outputting neural data as shown in fig. 11A, outputting differential data as shown in fig. 11B, and determining whether to output neural data as shown in fig. 11C, wherein mode III can be regarded as a combination of mode I and mode II.

In fig. 12, the first time circuit 2a is shown in an output period (e.g., period T in fig. 4B) _O1 ) Output differential data D _diff And the second time display circuit 2b outputs the neural data D during the output _nueral . During the next output period (e.g., period T of FIG. 4B) _O2 ) The first time circuit 2a outputs the neural data D _nueral And the second time circuit 2b outputs the differential data D _diff The exchange is repeated in this way.

That is, in FIGS. 11A to 11CThe circuit interchange shown refers to recording and outputting differential data D _diff And neural data D _nueral Is exchanged during each output, wherein the output period is the period during which data or signals are read from the time circuit.

The neural signal detection circuit 1200 of fig. 12 is the same as fig. 2, except that the control signal is changed to obtain different output signals from the two time circuits. In addition, in order to indicate different time circuits, in fig. 12, the components and signals in the first time circuit 2a are indicated by _ R and the components and signals in the second time circuit 2b are indicated by _ N.

Fig. 13 is a signal timing diagram of the neural signal detecting circuit 1200 of fig. 12, which includes a first period and a second period for recording voltage energy, and three signal output periods including a differential data reading period, a differential checking period, and a neural data reading period.

In the reset detection period of the first period, the electrode ED operates and the node V is connected by the configuration of the control signals BIAS _ R, RESET and AZ _ R shown in fig. 13 _FD Is reset to V _RESET And node V _{G_R} Is reset to V _AZ 。

In the energy transfer period of the first period, the voltage energy V is supplied by the arrangement of the control signals BIAS _ R, RESET and AZ _ R shown in fig. 13 _REF Transferred to node V through transfer transistor SWt _FD So that the potential thereon changes into V _RESET +V _REF 。

During the reset detection period of the second period, the electrode ED is re-operated and the node V is reset _FD Is reset to V again _RESET . At this time, since the storage capacitor C1 is floating (AZ _ R goes low), the corresponding node V _FD Voltage V of _REF Change that has occurred, node V _{G_R} While lowering V _REF To be V _AZ -V _REF 。

In the energy transfer period of the second period, the voltage energy V is transferred _NEW Transferred to node V through transfer transistor SWt _FD So that the potential thereon changes into V _RESET +V _NEW Wherein V is _REF Has the similar meaning as V of FIG. 4B _SIG1 And V _NEW Has the similar meaning as V of FIG. 4B _SIG2 Only here V _REF And V _NEW Are all transferred to node V _FD . At this time, since the storage capacitor C1 is still floating, the node V _{G_R} Is simultaneously changed to V _AZ +(V _NEW -V _REF ). That is, node V _{G_R} The voltage energy change (V) detected by the electrode ED during the first period and the second period is recorded _NEW -V _REF )。

Then, by selecting the control signal BIAS _ R or BIAS _ N, different modes in fig. 11A to 11C can be selected.

In the mode I of FIG. 11A, the detected voltage energy V of the second timing circuit 2b is read _NEW . Due to the detected voltage energy V _NEW The voltage energy is not differentiated from the voltage energy detected in the other period, and therefore, it can be considered as the neural data detected by the neural signal detecting circuit 1200 in the second period.

Referring to FIG. 13 again, in the energy transfer period of the second period, the node V _FD Is formed as a voltage of V _NEW -V _RESET . During reading of the neural data, the storage capacitor C2 is floating (AZ _ N goes low). When node V _FD Is reset to V _RESET While, the corresponding node V _FD Voltage variation V of _REF Node V _{G_N} While lowering V _NEW To form V _AZ -V _NEW . Using the same method as that of FIG. 4A, the ramp signal is inputted as the control signal BIAS _ N into the first transistor SW1_ N to output the pulse width signal Tneural with a length corresponding to the voltage energy V _NEW The sizes of the components are not described herein because they are described above. The pulse width signal Tneural may be used for analog operation by other arithmetic circuits or other applications by a back-end processor, as described above.

In the next period, when the electrode ED is operated, new neural data is recorded in the first time circuit 2a and new differential data is recorded in the second time circuit 2 b. Using the same method as that of fig. 4A, the ramp signal is input to the first transistor SW1_ R as the control signal BIAS _ R to output the time signal (i.e., pulse width signal) Tneural as the neural data output by the neural signal detecting circuit 1200.

In mode II of FIG. 11B, the voltage energy difference (V) of the first time circuit 2a is read _NEW -V _REF )。

Referring to FIG. 13, during the energy transfer period of the second period, the node V _{G_R} Is changed into V _AZ +(V _NEW -V _REF ). During reading of differential data, using a similar method as that of fig. 4A, a ramp signal is input to the first transistor SW1_ R as a control signal BIAS _ R to output a time signal Tdiff having a length corresponding to a voltage energy difference (V) _NEW -V _REF ) The sizes of the components are not described herein because they are described above.

It should be noted that, during differential data reading, the voltage energy difference (V) is determined according to the voltage energy detected by the electrode ED in different periods _NEW -V _REF ) May be positive or negative, in order to be able to be at (V) _NEW -V _REF ) When the pulse width is negative, the corresponding pulse width signal can still be output (the pulse width has no negative value), so that the start of the ramp signal is not from V _AZP Initially, a voltage offset value Voff is added. Although it is shown in FIG. 13 that the pulse width signal Tdiff is proportional to Voff + (V) _NEW -V _REF ) When Voff is constant, the pulse width signal Tdiff is substantially only equal to (V) _NEW -V _REF ) And (4) correlating.

It should be noted that although fig. 13 shows that the ramp control signals BIAS _ R and BIAS _ N start after the voltage valley (voltage valley) which is used to create the starting point of the ramp signal.

In the next period, when the electrode ED is operated, new differential data D _diff The new neural data D recorded in the second time circuit 2b _nueral It is recorded in the first time circuit 2 a. Using the same method as that of fig. 4A, the ramp signal is input to the first transistor SW1_ N as the control signal BIAS _ N to output the time signal Tdiff as differential data output by the neural signal detecting circuit 1200.

In the pattern III of fig. 11C, the differential signal (V) recorded in accordance with the first time circuit 2a _NEW -V _REF ) It is determined whether or not to read the neural data of the second time circuit 2b of the neural signal detecting circuit 1200.

Referring to FIG. 13, during the differential checking period, the voltage V of the control signal BIAS _ R is controlled _AZP Plus and minus a voltage threshold Vth to V _AZ +(V _NEW -V _REF ) And (6) comparing. When (V) _NEW -V _REF ) When the variation of (D) is greater than Vth, the differential signal D _diff A transition, such as a change from 1 to 0 or a change from 0 to 1, may occur, indicating that the neural signal detection circuit 1200 detects a change in voltage energy between the first period and the second period. Therefore, the processor at the back end reads the second time circuit 2b of the neural signal detecting circuit 1200 recorded at the node V during the period of reading the neural data _{G_N} The neural data of (a).

If (V) _NEW -V _REF ) Is not greater than Vth, node V is not read _{G_N} And continues to detect voltage energy in the next period, as shown in fig. 11C.

Similarly, during the next period, the storage positions of the differential data and the neural data are exchanged when the electrode ED operates. The back-end processor determines whether the voltage energy variation is greater than or equal to a threshold Vth according to the differential signal Ddiff of the second time circuit 2b, so as to determine whether to read the neural data Dnueral from the first time circuit 2 a.

It should be noted that the differential data reading period, the differential checking period and the neural data reading period in fig. 13 are not necessarily all performed, and at least one of the periods may be performed according to different applications.

For example, as shown in fig. 14, when the detection array includes a plurality of neural signal detection circuits 1200 (or 1500, 1700, 1800, 1900 described later), the difference check shown in fig. 13 can confirm whether or not each neural signal detection circuit 1200 detects a voltage energy change between the first frame and the second frame, i.e., the determination signal D _diff Otherwise, the state is transferred.

In one embodiment, the back-end processor (e.g., the above-mentioned determining circuit or the back-end host) performs the neural signal detecting circuit 1200 for detecting the sufficient voltage energy changeTag (tag), for example, FIG. 14 shows that five (the arrow symbols indicate) detection circuits in the detection array detect the voltage energy change, i.e., the differential signal D _diff A transition occurs.

In another embodiment, the processor at the back end only reads the neural data (i.e. pulse width signal) of the neural signal detection circuit 1200 that detects the voltage energy change for updating the neural data stored in the corresponding frame buffer at the back end. The neural data of the neural signal detecting circuit 1200 that does not detect the voltage energy change is not read by the processor in the back end.

It should be noted that the usage of the neural signal detection circuit 1200 and its neural data by the back-end processor to detect sufficient voltage energy changes may depend on different applications.

In summary, the neural signal detecting circuit 1200 of the present invention includes two time circuits, and after performing reset detection and energy transfer in two different periods, the time difference data (or signal) and the neural data can be recorded respectively, and according to the selection of different control signals BIAS _ R and BIAS _ N (for example, using a switch or a multiplexer), different modes of operations such as fig. 11A to 11C can be performed.

Fig. 15 shows a modification 1500 of the neural signal detecting circuit according to the embodiment of the present invention, which can perform operations in different modes as shown in fig. 11A to 11C according to different control signals BIAS _ R and BIAS _ N.

The difference between the neural signal detecting circuit 1500 of fig. 15 and the neural signal detecting circuit 1200 of fig. 12 is that the first transistor SW1_ R, SW1_ N and the third transistor SW3_ R, SW3_ N of fig. 12 are replaced by a comparator. The upper right circuit of fig. 15 shows the structure of the two comparators and their input signals. An inverting input terminal of the comparator CMP1 is connected to the second terminal of the first capacitor C1 and the second transistor SW2_ R, and a non-inverting input terminal of the comparator CMP1 receives the control signal BIAS _ R. An inverting input terminal of the comparator CMP2 is connected to the second terminal of the second capacitor C2 and the second transistor SW2_ N, and a non-inverting input terminal of the comparator CMP2 receives the control signal BIAS _ N. Compared with fig. 12, the present embodiment can reduce the influence of current and noise.

Fig. 16 is a signal timing diagram of the neural signal detecting circuit 1500 of fig. 15.

Similarly, during the first period, electrode ED operates and forms voltage VRESET + VREF at node VFD by the configuration of control signals BIAS _ R, RESET and AZ _ R shown in fig. 16. In the second period, the electrode ED is operated again and forms a voltage VAZ + (VNEW-VREF) on the node VG _ R by the arrangement of the control signals BIAS _ R, RESET and AZ _ R shown in FIG. 16.

During reading of the neural data, the storage capacitor C2 is floating (AZ _ N goes low), and when the voltage of the node VFD is reset to VRESET, the voltage of the node VG _ N decreases VNEW to form VAZ-VNEW in response to the voltage change VREF of the node VFD. The ramp signal is input as a control signal BIAS _ N to the comparator CMP2 to cause the comparator CMP2 to output a time signal Tneural.

During reading of the differential data, the ramp signal is input as the control signal BIAS _ R to the comparator CMP1 to cause the comparator CMP1 to output the time signal Tdiff.

During the differential check, voltage VAZ is added and subtracted by voltage threshold Vth as control signal BIAS _ R to compare with VAZ + (VNEW-VREF). When the variation of (VNEW-VREF) is larger than Vth, the transition of the differential signal Ddiff occurs.

Reading differential data, differentially examining and reading neural data is similar to fig. 13, with the main difference being that control signals BIAS _ R and BIAS _ N are different.

In fig. 15, all the transistors of the comparators CMP1 and CMP2 are disposed in the neural signal detecting circuit 1500, and thus the area of the neural signal detecting circuit 1500 is increased.

Fig. 17 shows a modification 1700 of the neural signal detecting circuit according to the embodiment of the present invention, in which the first input transistor SWc1 and the third input transistor SWc3 of the comparator of fig. 15 are respectively disposed in the neural signal detecting circuit 1700, and the other transistors of the comparator are disposed outside the neural signal detecting circuit 1700 and shared with the other neural signal detecting circuits. The other neural signal detection circuit is a plurality of neural signal detection circuits located in the same column (e.g., the same column of the detection array of fig. 14) as the neural signal detection circuit 1700.

The timing diagram of the signals of the neural signal detecting circuit 1700 is also shown in FIG. 16.

In the present modification, the neural signal detection circuit 1700 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first time circuit 172a, and a second time circuit 172 b.

The first timing circuit 172a includes a first capacitor (or storage capacitor) C1 and a second transistor SW2_ R, which have functions similar to those of the elements C1 and SWa2 of fig. 2, respectively, and therefore are not described herein again. The first capacitor C1 has a first terminal (e.g., the left terminal shown in fig. 17) coupled to the electrode ED.

The first time circuit 172a further includes a first input transistor SWc1 serving as an inverting input terminal of the first comparator and connected to the second terminal (e.g., the right terminal shown in fig. 17) of the first capacitor C1. The first comparator further includes a second input transistor SWc2 and transistors T1, T2 disposed outside the neural signal detecting circuit 1700 and shared by the first time circuit 172a and other neural signal detecting circuits. The second input transistor SWc2 serves as a non-inverting input terminal of the first comparator.

The second timing circuit 172b includes a second capacitor (or storage capacitor) C2 and a second transistor SW2_ N, which have the same functions as the elements C2 and SWb2 of fig. 2, and therefore, the description thereof is omitted. The second capacitor C2 has a first terminal (e.g., the left terminal shown in fig. 17) coupled to the electrode ED.

The second timing circuit 172b further includes a third input transistor SWc3 serving as an inverting input terminal of the second comparator and connected to the second terminal of the second capacitor C2 (e.g., the right terminal thereof is shown in fig. 17). The second comparator further includes a fourth input transistor SWc4 and transistors T3 and T4 disposed outside the neural signal detecting circuit 1700 and shared by the second timing circuit 172b and the other neural signal detecting circuits. A fourth input transistor SWc4 serves as a non-inverting input of the second comparator.

Electrode ED is used to generate a sensing voltage, including VREF and VNEW as shown in FIG. 16.

The transfer transistor SWt is connected between the electrode ED and the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2. As shown in fig. 16, the transfer transistor SWt is used to transfer the detection voltage (including VREF and VNEW) to the first time circuit 172a (VRESET + VREF and VRESET + VNEW, respectively, shown on the node VFD) during the first period and the second period and to transfer the detection voltage (including VNEW) to the second time circuit 172b (VRESET + VNEW, shown on the node VFD) during the second period.

The reset transistor SWrst is connected between the transfer transistor SWt and the first end of the first capacitor C1 and the first end of the second capacitor C2. The function of the reset transistor SWt is described above, and therefore, the description thereof is omitted.

The second transistor SW2_ R is connected between the first capacitor C1 and the first input transistor SWc1, wherein the second transistor SW2_ R of the first time circuit 172a is turned off during the second period, and the control signal AZ _ R shown in fig. 16 is at a low level during the second period. The second transistor SW2_ N is connected between the second capacitor C2 and the third input transistor SWc3, wherein the second transistor SW2_ N of the second timing circuit 172b is not turned on during the first period, and the control signal AZ _ N shown in fig. 16 is at a low level during the first period.

In this embodiment, the first time circuit 172a is used for recording the voltage energy variation of the voltage energy detected by the electrode ED between the first period and the second period, as shown in fig. 16, when the transfer transistor SWt is turned on during the second period, the voltage at the node VG _ R is converted into VAZ + (VNEW-VREF), where VAZ is the voltage at the node VG _ R during the reset period. The second time circuit 172b is used to record the detected voltage of the electrode ED during the second period, and when the node VFD is reset to the voltage VRESET during reading of the neural data as shown in fig. 16, the voltage of the node VG _ N is changed to VAZ-VNEW.

The neural signal detecting circuit 1700 can operate in different modes according to the input signal of the second input transistor SWc2, as shown in fig. 11B and 11C. When the second input transistor SWc2 receives the ramp signal (as shown in the differential data reading period of fig. 16), the first time circuit 172a outputs the pulse width signal Tdiff corresponding to the voltage energy variation (VNEW — VREF). As previously described, since (VNEW-VREF) may be negative, the starting point of the ramp signal is added with an offset Voff.

When the second input transistor SWc2 receives the lower threshold voltage VAZ-Vth and the upper threshold voltage VAZ + Vth in sequence (as shown in the read check differential period of FIG. 16), it can be confirmed whether the voltage energy change (VNEW-VREF) exceeds the voltage threshold Vth. When VAZ + (VNEW-VREF) does not exceed the range of the upper threshold voltage VAZ + Vth and the lower threshold voltage VAZ-Vth, the output signal Ddiff does not transition, which indicates that the neural signal detection circuit 1700 does not detect enough energy change; when VAZ + (VNEW-VREF) exceeds the range of the upper threshold voltage VAZ + Vth or the lower threshold voltage VAZ-Vth, the output signal Diff will go into a transition state, which indicates that the neural signal detection circuit 1700 detects the energy change, and the back-end processor can perform corresponding operation accordingly.

The neural signal detecting circuit 1700 may operate in another mode according to the input signal of the fourth input transistor SWc4, as shown in fig. 11A. When the fourth input transistor SWc4 receives the ramp signal (as shown in the period of reading nerve data of fig. 16), the second time circuit 172b outputs the pulse width signal Tneural corresponding to the detection voltage energy VNEW. Since the detected voltage energy VNEW does not undergo a difference operation and does not have a negative value, the offset voltage Voff is not added.

In one embodiment, the first timing circuit 172a further includes two row select transistors SWrs _ R (two are shown) connected between the first timing circuit 172a and the first comparator, the row select transistors SWrs _ R being configured to connect the first timing circuit 172a and the first comparator according to the row select signal RS. The second timing circuit 172b further includes a row select transistor SWrs _ N (two are shown) connected between the second timing circuit 172b and the second comparator, the row select transistor SWrs _ N for connecting the second timing circuit 172b and the second comparator according to the row select signal RS.

Operations not described with respect to the neural signal detection circuit 1700 can be described with reference to fig. 16.

Fig. 18 shows a modification 1800 of the neural signal detecting circuit according to the embodiment of the present invention, in which all of the first comparator and the second comparator shown in fig. 17 are disposed outside the neural signal detecting circuit 1800 and shared with other neural signal detecting circuits. The other neural signal detection circuits are a plurality of neural signal detection circuits located in the same column (e.g., the same column of the detection array of fig. 14) as the neural signal detection circuit 1800.

The timing diagram of the neural signal detection circuit 1800 is also shown in FIG. 16.

The neural signal detecting circuit 1800 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first time circuit 182a, and a second time circuit 182 b.

The first timing circuit 182a includes a first capacitor C1 and a second transistor SW2_ R, which function similarly to the elements C1 and SWa2 of fig. 2, respectively, and therefore are not described herein again. The first capacitor C1 has a first terminal (e.g., the left terminal shown in fig. 18) coupled to the electrode ED.

A second terminal (e.g., the right terminal of fig. 18) of the first capacitor C1 of the first time circuit 182a is coupled to the inverting input terminal of the first comparator CMP 1. The first comparator CMP1 is disposed outside the neural signal detecting circuit 1800 and shared by the first time circuit 182a and the other neural signal detecting circuits.

The second timing circuit 182b includes a second capacitor C2 and a second transistor SW2_ N, which function similarly to the elements C2 and SWb2 of fig. 2, respectively, and therefore are not described herein again. The second capacitor C2 has a first terminal (e.g., the left terminal shown in fig. 18) coupled to the electrode ED.

A second terminal (e.g., the right terminal shown in fig. 18) of the second capacitor C2 of the second timing circuit 182b is coupled to the inverting input terminal of the second comparator CMP 2. The second comparator CMP2 is disposed outside the neural signal detecting circuit 1800 and shared by the second timing circuit 182b and the other neural signal detecting circuits.

Electrode ED is used to generate a sensing voltage, including VREF and VNEW as shown in FIG. 16.

The transfer transistor SWt is connected between the electrode ED and the first end of the first capacitor C1 and the first end of the second capacitor C2. As shown in fig. 16, transfer transistor SWt is used to transfer voltage energy (including VREF and VNEW) to first time circuit 182a (VRESET + VREF and VRESET + VNEW, respectively, shown on node VFD) during a first period and to transfer voltage energy (including VNEW) to second time circuit 182b (VRESET + VNEW, shown on node VFD) during a second period.

The reset transistor SWrst is connected between the transfer transistor SWt and the first terminal of the first capacitor C1 and the first terminal of the second capacitor C2. The function of the reset transistor SWt is described above, and therefore, the description thereof is omitted.

The second transistor SW2_ R is connected between the first capacitor C1 and the first comparator CMP1, wherein the second transistor SW2_ R of the first time circuit 182a is not turned on during the second period, and the control signal AZ _ R is at a low level during the second period as shown in fig. 16. The second transistor SW2_ N is connected between the second capacitor C2 and the second comparator CMP2, wherein the second transistor SW2_ N of the second time circuit 182b is not turned on during the first period, and the control signal AZ _ N shown in fig. 16 is at a low level during the first period.

In this embodiment, the first time circuit 182a is used to record the voltage energy change of the voltage energy detected by the electrode ED between the first period and the second period, as shown in fig. 16, when the transfer transistor SWt is turned on during the second period, the voltage at the node VG _ R is transformed into VAZ + (VNEW-VREF), where VAZ is the voltage at the node VG _ R during the reset period. The second time circuit 182b is used to record the detected voltage of electrode ED during the second period, as shown in fig. 16, when node VFD is reset to voltage VRESET during reading of the neural data, the voltage of node VG _ N transitions to VAZ-VNEW.

The neural signal detecting circuit 1800 may operate in different modes according to the input signal of the non-inverting input terminal of the first comparator CMP1, as shown in fig. 11B to 11C. For example, when the non-inverting input terminal of the first comparator CMP1 receives the ramp signal (as shown in the differential data reading period of fig. 16), the first time circuit 182a outputs the pulse width signal Tdiff corresponding to the voltage energy variation (VNEW — VREF). As previously mentioned, (VNEW-VREF) may be negative, with an offset Voff added to the start of the ramp signal.

When the non-inverting input of the first comparator CMP1 receives the lower threshold voltage VAZ-Vth and the upper threshold voltage VAZ + Vth in sequence (as shown in the read check differential period of FIG. 16), it can be confirmed whether the voltage energy variation (VNEW-VREF) exceeds the voltage threshold Vth. When VAZ + (VNEW-VREF) does not exceed the range of the upper threshold voltage VAZ + Vth and the lower threshold voltage VAZ-Vth, the output signal Ddiff does not transition, indicating that the neural signal detecting circuit 1800 does not detect enough energy change; when VAZ + (VNEW-VREF) exceeds the range of the upper threshold voltage VAZ + Vth or the lower threshold voltage VAZ-Vth, the output signal Ddiff will transition to indicate that the neural signal detection circuit 1800 detects the energy change, and the back-end processor can perform corresponding operation accordingly.

It should be noted that the input sequence of the upper threshold voltage and the lower threshold voltage is not limited in particular.

The neural signal detecting circuit 1800 may operate in another mode according to the input signal of the non-inverting input terminal of the second comparator CMP2, as shown in fig. 11A. When the non-inverting input terminal of the second comparator CMP2 receives the ramp signal (as shown in the period of reading the neural data of fig. 16), the second time circuit 182b outputs the pulse width signal Tneural corresponding to the detected voltage energy VNEW. Since the detected voltage energy VNEW does not undergo a difference operation and does not have a negative value, the offset voltage Voff is not added.

In order to allow the voltage on the first capacitor C1 to be buffered to the capacitor C3 without loss for storage, the first time circuit 182a further includes a first source follower SF _ R connected between the first capacitor C1 and the second transistor SW2_ R and the first comparator CMP 1. In order to buffer the voltage on the second capacitor C2 to the capacitor C4 for storage without loss, the second time circuit 182b further includes a second source follower SF _ N connected between the second capacitor C2 and the second transistor SW2_ N and the second comparator CMP 2.

In one embodiment, the first time circuit 182a further includes a row select transistor SWrs _ R connected between the first source follower SF _ R and the first comparator CMP1, the row select transistor SWrs _ R being configured to turn on the first source follower SF _ R and the first comparator CMP1 according to the row select signal RS. The second timing circuit 182b further includes a row select transistor SWrs _ N connected between the second source follower SF _ N and the second comparator CMP2, the row select transistor SWrs _ N for turning on the second source follower SF _ N and the second comparator CMP2 according to the row select signal RS.

Operations not described with respect to the neural signal detection circuit 1800 can be seen with reference to fig. 16.

In the modification of fig. 18, the first comparator CMP1 and the second comparator CMP2 are disposed outside the neural signal detection circuit 1800 and are shared with other neural signal detection circuits. Therefore, in the operation of fig. 16, the operations of the first period and the second period are performed in the neural signal detecting circuit 1800, and the differential data reading, the differential checking and the neural data reading in the output stage (i.e., turning on the row selecting transistor SWrs _ R or SWrs _ N) are mainly performed outside the neural signal detecting circuit 1800.

The plurality of neural signal detection circuits 1800 of one detection circuit column sequentially output a time signal or a differential check signal using the comparators CMP1 or CMP2 according to the row selection signal RS.

Referring to fig. 19, a modified example 1900 of the neural signal detecting circuit according to the embodiment of the present invention is mainly disclosed, in which a source follower SF is additionally disposed between the transfer transistor SWt and the first capacitor C1 of the first time circuit 192a and the second capacitor C2 of the second time circuit 192b in the neural signal detecting circuit 1800 of fig. 18, so as to buffer the voltage at the node VFD to the first capacitor C1 and the second capacitor C2 without loss, thereby improving the sensitivity and the conversion gain of the neural signal detecting circuit.

The rest of fig. 19 is the same as fig. 18 and the operation thereof can be referred to fig. 16, so that the description thereof is omitted.

In the modification shown in fig. 19, the second terminal of the first capacitor C1 is coupled to the inverting input terminal of the first comparator CMP1, and the first comparator CMP1 is disposed outside the neural signal detecting circuit 1900 and shared by the first time circuit 192a and other neural signal detecting circuits. The second end of the second capacitor C2 is coupled to the inverting input terminal of the second comparator CMP2, and the second comparator CMP2 is disposed outside the neural signal detecting circuit 1900 and shared by the second timing circuit 192b and other neural signal detecting circuits. The other neural signal detection circuits are a plurality of neural signal detection circuits located in the same column (e.g., the same column of the detection array of fig. 14) as the neural signal detection circuit 1900.

It should be noted that the operations of the neural signal detection circuits 1500, 1700, 1800, and 1900 can be applied to each detection circuit of the detection array of fig. 14, for example.

It should be noted that since the storage locations of the time difference data and the neural data are interchanged, it is also possible that the first time circuit records the neural data and the second time circuit records the time difference data at the first cycle.

It should be noted that in the present description, the term "element" is in the neural signal detection circuit means that each detection circuit of the detection array includes one element, and the term "element" is outside the neural signal detection circuit means that a column of detection circuits of the detection array shares the element.

The invention is also applicable to retinal chips, as long as the sensing elements (i.e. electrodes) are replaced by light sensing elements, such as photodiodes as mentioned in the parent application, and the details thereof have been explained in the parent application and are therefore not described in detail herein.

In summary, processing and analyzing electroencephalographic signals is an important task. Therefore, the present invention also provides a neural signal detection circuit (fig. 2 and 5 to 7, 12 and 15 to 19) that can output a pulse width signal and perform analog operation of a neural signal.

Although the present invention has been disclosed by way of examples, it is not intended to be limited thereto, and various changes and modifications can be made by one of ordinary skill in the art without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the scope defined by the appended claims.

Claims (20)

1. A neural signal detection circuit, comprising:

an electrode for generating a detection voltage;

a first time circuit, the first time circuit comprising:

a first capacitor having a first end coupled to the electrode;

a second time circuit, the second time circuit comprising:

a second capacitor having a first end coupled to the electrode;

a first comparator, the first comparator comprising:

a first input transistor configured in the first time circuit and connected to a second end of the first capacitor; and

a second input transistor configured outside the first time circuit and shared with other neural signal detection circuits; and

a second comparator, the second comparator comprising:

a third input transistor configured in the second time circuit and connected to the second end of the second capacitor; and

a fourth input transistor configured outside the second time circuit and shared with the other neural signal detection circuits.

2. The neural signal detecting circuit of claim 1,

the other neural signal detection circuits are a plurality of neural signal detection circuits located in the same column of the detection array as the neural signal detection circuit,

the first input transistor serves as an inverting input terminal of the first comparator,

the second input transistor serves as a non-inverting input of the first comparator,

the third input transistor serves as an inverting input terminal of the second comparator, an

The fourth input transistor serves as a non-inverting input terminal of the second comparator.

3. The neural signal detection circuit of claim 1, further comprising:

a transfer transistor connected between the electrode and the first end of the first capacitor and the first end of the second capacitor for transferring the detection voltage to the first time circuit during a first period and a second period and transferring the detection voltage to the second time circuit during the second period; and

a reset transistor connected between the transfer transistor and the first end of the first capacitor and the first end of the second capacitor.

4. The neural signal detecting circuit of claim 3,

the first time circuit further comprises a second transistor connected between the first capacitor and the first input transistor,

the second time circuit further comprises a second transistor connected between the second capacitor and the third input transistor, an

The second transistor of the first time circuit is non-conductive during the second period, and the second transistor of the second time circuit is non-conductive during the first period.

5. The neural signal detecting circuit of claim 3,

the first time circuit is used for recording the voltage energy change of the electrode between the first period and the second period, an

The second time circuit is used for recording the detection voltage of the electrode in the second period.

6. The neural signal detecting circuit of claim 5, wherein the second input transistor is configured to be used

Receiving a ramp signal to make the first time circuit output a pulse width signal corresponding to the voltage energy change, or

An upper threshold voltage and a lower threshold voltage are sequentially received to determine whether the voltage energy change exceeds the upper threshold voltage or the lower threshold voltage.

7. The neural signal detecting circuit of claim 5, wherein the fourth input transistor is for

And receiving a ramp signal to enable the second time circuit to output a pulse width signal corresponding to the detection voltage.

8. The neural signal detection circuit of claim 1, further comprising a plurality of row select transistors connected between the first time circuit and the first comparator and between the second time circuit and the second comparator.

9. A neural signal detection circuit, comprising:

an electrode for generating a detection voltage;

a first time circuit, the first time circuit comprising:

a first capacitor having a first end coupled to the electrode; and

a second time circuit, the second time circuit comprising:

a second capacitor having a first end coupled to the electrode, wherein,

a second end of the first capacitor is coupled to an inverting input terminal of a first comparator, the first comparator is disposed outside the neural signal detection circuit and shared by the first time circuit and other neural signal detection circuits, an

The second end of the second capacitor is coupled to the inverting input terminal of a second comparator, and the second comparator is configured outside the neural signal detection circuit and shared by the second time circuit and the other neural signal detection circuits.

10. The neural signal detection circuit of claim 9, wherein the other neural signal detection circuits are a plurality of neural signal detection circuits located in the same column of a detection array as the neural signal detection circuit.

11. The neural signal detection circuit of claim 9, further comprising:

a transfer transistor connected between the electrode and the first end of the first capacitor and the first end of the second capacitor for transferring the detection voltage to the first time circuit during a first period and a second period and transferring the detection voltage to the second time circuit during the second period; and

a reset transistor connected between the transfer transistor and the first end of the first capacitor and the first end of the second capacitor.

12. The neural signal detecting circuit of claim 11,

the first time circuit further comprises a second transistor connected between the first capacitor and the first comparator,

the second time circuit further comprises a second transistor connected between the second capacitor and the second comparator, an

The second transistor of the first time circuit is non-conductive during the second period, and the second transistor of the second time circuit is non-conductive during the first period.

13. The neural signal detecting circuit of claim 11,

the first time circuit is used for recording the voltage energy change of the electrode between the first period and the second period, an

The second time circuit is used for recording the detection voltage of the electrode in the second period.

14. The neural signal detection circuit of claim 13, wherein the non-inverting input of the first comparator is used to

Receiving a ramp signal to make the first comparator output a pulse width signal corresponding to the voltage energy variation, or

An upper threshold voltage and a lower threshold voltage are sequentially received to determine whether the voltage energy change exceeds the upper threshold voltage or the lower threshold voltage.

15. The neural signal detection circuit of claim 13, wherein the non-inverting input of the second comparator is used to

Receiving a ramp signal to cause the second comparator to output a pulse width signal corresponding to the detection voltage.

16. The neural signal detection circuit of claim 12, further comprising:

a first source follower connected to the first capacitor and the second transistor of the first time circuit;

a first row select transistor connected between the first source follower and the first comparator;

a second source follower connected to the second capacitor and the second transistor of the second time circuit; and

a second row select transistor connected between the second source follower and the second comparator.

17. A neural signal detection circuit, comprising:

a source follower;

a first time circuit, the first time circuit comprising:

a first capacitor having a first end coupled to the source follower; and a second time circuit, the second time circuit comprising:

a second capacitor having a first end coupled to the source follower, wherein a second end of the first capacitor is coupled to an inverting input of a first comparator disposed outside the neural signal detection circuit and shared by the first time circuit and other neural signal detection circuits, an

The second end of the second capacitor is coupled to the inverting input terminal of a second comparator, and the second comparator is configured outside the neural signal detection circuit and shared by the second time circuit and the other neural signal detection circuits.

18. The neural signal detection circuit of claim 17, further comprising:

a first source follower connected to the second end of the first capacitor;

a first row select transistor connected between the first source follower and the first comparator;

a second source follower connected to the second end of the second capacitor; and

and the second row selection transistor is connected between the second source follower and the second comparator.

19. The neural signal detection circuit of claim 15, further comprising:

an electrode for generating a detection voltage;

a transfer transistor connected between the electrode and the source follower, for transferring the detection voltage to the first time circuit through the source follower during a first period and a second period, and transferring the detection voltage to the second time circuit through the source follower during the second period; and

a reset transistor connected between the transfer transistor and the source follower.

20. The neural signal detecting circuit of claim 19,

the first time circuit is used for recording the voltage energy change of the electrode between the first period and the second period, an

The second time circuit is used for recording the detection voltage of the electrode in the second period.

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