CN112422129B - Direct X-ray detector CMOS reading circuit and control method - Google Patents
Direct X-ray detector CMOS reading circuit and control method Download PDFInfo
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- CN112422129B CN112422129B CN202011160805.4A CN202011160805A CN112422129B CN 112422129 B CN112422129 B CN 112422129B CN 202011160805 A CN202011160805 A CN 202011160805A CN 112422129 B CN112422129 B CN 112422129B
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Abstract
The invention discloses a CMOS reading circuit of a direct X-ray detector, which is used for reading an induced current signal in the direct X-ray detector and comprises a pixel circuit, a double sampling and amplifying circuit and a detection circuit; the pixel circuit is connected with an X-ray sensitive element in the detector and used for integrating the induced current output by the sensitive element in an integration stage and converting the induced current into an integration voltage and outputting a reset voltage in a reset stage; the double sampling and amplifying circuit is used for sampling and amplifying the integral voltage and the reset voltage output by the pixel circuit, so that the reading of the induced current is realized; the input end of the detection circuit is connected to the output end of the double sampling and amplifying circuit, and the output end of the detection circuit is connected to the input end of the pixel circuit and used for detecting whether the X-ray sensitive element is damaged or not and grounding the output end of the damaged X-ray sensitive element.
Description
Technical Field
The invention belongs to the field of CMOS (complementary metal oxide semiconductor) reading circuits of detectors, and particularly relates to a CMOS reading circuit of a direct X-ray detector and a control method thereof.
Background
Generally, a perovskite direct type X-ray detector is divided into two major parts, namely a perovskite direct type X-ray sensitive element and a CMOS readout circuit. The CMOS readout circuit is used for reading out the output signal of the X-ray sensitive element, so the design of the CMOS readout circuit is inseparable from the condition of the output signal of the sensitive element. Therefore, according to relevant parameters of the perovskite direct X-ray sensitive element, designing a CMOS reading circuit is very important for designing the whole direct X-ray detector chip.
The read-out circuitry of the detector typically comprises a pixel circuit and a double sampling and amplifying circuit. The pixel circuit is connected with the sensitive element and used for integrating the induced current output by the sensitive element in an integration stage and converting the induced current into voltage. The double sampling and amplifying circuit is used for sampling and amplifying the output signal of the pixel circuit after the integration stage is finished, so that the reading of the induced current is realized.
The existing reading circuit is not provided with a corresponding detection and protection circuit module, so when the consistency of the sensitive elements is poor and the defective points exist, the response of the defective points of the sensitive elements to external stimulation is too high, the input current of the corresponding pixel circuit is too large, and finally the pixel circuit cannot bear large current and is damaged. In addition, in the detector chip, the damage of some pixels may cause a chain effect, so that the surrounding pixel circuits and even the entire pixel circuit array are completely damaged, and the output signals of the sensitive elements cannot be read normally.
Disclosure of Invention
Aiming at the defects and the improvement requirements of the prior art, the invention provides a high-reliability CMOS reading circuit of a direct X-ray detector and a control method thereof, and aims to perform a round of detection process before a chip of the direct X-ray detector normally works. In the detection process, dead spots in the perovskite X-ray sensitive element can be detected, input signals of the dead spots are grounded, and overlarge output current does not enter a pixel circuit, so that a CMOS reading circuit is protected, and stable and reliable signal reading is realized.
In order to achieve the purpose, the invention designs a high-reliability CMOS reading circuit of a direct X-ray detector, which comprises a pixel circuit and a double sampling and amplifying circuit detection circuit; the pixel circuit is connected with an X-ray sensitive element in the detector and used for integrating the induced current output by the sensitive element in an integration stage and converting the induced current into an integration voltage and outputting a reset voltage in a reset stage; the double sampling and amplifying circuit is used for sampling and amplifying the integral voltage and the reset voltage output by the pixel circuit, so that the reading of the induced current is realized; the input end of the detection circuit is connected to the output end of the double sampling and amplifying circuit, and the output end of the detection circuit is connected to the input end of the pixel circuit and used for detecting whether the X-ray sensitive element is damaged or not and grounding the output end of the damaged X-ray sensitive element.
In one embodiment of the invention, in order to facilitate circuit testing and verification, a signal generating circuit is further provided for simulating the current generated by the perovskite X-ray sensitive element under an external stimulus, and the output end of the signal generating circuit is connected with the input end of the pixel circuit to input the current into the pixel circuit for processing.
In an embodiment of the present invention, the CMOS readout circuit further includes an ADC circuit, a first input terminal of the ADC circuit is connected to the non-inverting output terminal of the dual sampling and amplifying circuit, and a second input terminal of the ADC circuit is connected to the inverting output terminal of the dual sampling and amplifying circuit; the ADC circuit is used for carrying out analog-to-digital conversion on the output of the double sampling and amplifying circuit.
According to another aspect of the present application, there is also provided a control method of the CMOS readout circuit of the direct X-ray detector described above, including the steps of:
before the reading circuit works normally, a detection mode is firstly entered, and the following stages of processing are executed in the detection mode:
a reset stage: resetting, by the reset circuit, the integrating capacitor;
an integration stage: the integrating capacitor receives an induced current signal input by an X-ray sensitive element in the detector;
and (3) a reading stage: reading out the reset voltage signal and the integral voltage signal through the double sampling and amplifying circuit, and sending the signals to a detection circuit for detection;
an assignment stage: the detection circuit grounds the output end of the X-ray sensitive element with the overhigh input induced current signal according to the detection result;
the readout circuit then enters a normal operating mode in which the duration of the integration phase in the detection mode is no more than 20% of the duration of the integration phase in the normal operating mode.
According to one aspect of the present application, there is also provided a direct type X-ray detector comprising the CMOS readout circuitry described above.
In general, the above technical solution of the present invention can achieve the following advantages:
the high-reliability CMOS reading circuit and the control method of the direct X-ray detector can detect the pixel dead pixel of the perovskite X-ray sensitive element with overlarge response, and carry out grounding processing on the pixel point at the corresponding position, can prevent the pixel circuit of the pixel from being damaged due to overlarge input current, and avoid the damage of circuits at other positions due to the dead pixel, thereby achieving the purpose of protecting the circuit.
Drawings
FIG. 1 is a schematic diagram of a CMOS readout circuit of a direct X-ray detector according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a pixel circuit of the CMOS readout circuit;
FIG. 3 is a timing diagram of a CMOS readout circuit of the direct X-ray detector according to an embodiment of the present invention;
FIG. 4 is a diagram showing the result of the CMOS readout circuit of the direct X-ray detector in the detection mode according to the embodiment of the present invention;
fig. 5 is a diagram illustrating a result of a CMOS readout circuit of a direct X-ray detector according to an embodiment of the present invention in a normal operation mode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In order to detect the pixel point with overlarge response of the perovskite sensitive element and perform grounding processing on the pixel point at the corresponding position to prevent the pixel circuit from being damaged due to overlarge input current, the invention provides a high-reliability CMOS (complementary metal oxide semiconductor) reading circuit of a direct X-ray detector, which comprises a pixel circuit 2, a double sampling and amplifying circuit 3 and a detection circuit 4, as shown in figure 1. The pixel circuit 2 is connected with an X-ray sensitive element (not shown) in the detector, and is used for integrating the induced current output by the sensitive element in an integration phase and converting the induced current into an integration voltage, and outputting a reset voltage in a reset phase. The double sampling and amplifying circuit 3 is used for sampling and amplifying the integral voltage and the reset voltage output by the pixel circuit 2, so that the reading of the induced current is realized; the input end of the detection circuit 4 is connected to the output end of the double sampling and amplifying circuit 3, and the output end of the detection circuit is connected to the input end of the pixel circuit 2, so as to detect whether the X-ray sensitive element is damaged or not and connect the damaged output end of the X-ray sensitive element to the ground.
Specifically, in order to facilitate the test and verification of the readout circuit, the embodiment of the present invention further provides a signal generating circuit 1. The signal generating circuit is used for simulating the current generated by the perovskite X-ray sensitive element under the external stimulation, the output end of the signal generating circuit is connected with the input end of the pixel circuit 2, and the current is input into the pixel circuit 2 for processing.
Further, as shown in fig. 1, the detection circuit 4 is used for detecting the position of the pixel circuit with too high input in the detection mode, and performing grounding processing on the pixel circuit, so as to protect the pixel circuit and the whole CMOS readout circuit from being damaged, and realize stable and reliable readout of signals. The detection circuit 4 includes: a comparator 41, a digital processing block 42 and a ground control block 43. The input end of the comparator 41 is connected to the output end of the double sampling and amplifying circuit 3, and is configured to compare the output voltage of the double sampling and amplifying circuit 3 with a reference voltage, and send a comparison result to the digital processing module 42; the digital processing module 42 is configured to control the grounding control module 43 to turn on and off according to the comparison result of the comparator 41; the grounding control module 43 is connected to the output terminal of the X-ray sensitive element, that is, the input terminal of the pixel circuit 2, and is used for grounding or connecting the output current of the X-ray sensitive element to the pixel circuit 2 under the control of the digital processing module.
Specifically, as shown in fig. 1, a first input terminal of the comparator 41 is connected to the non-inverting output terminal of the double sampling and amplifying circuit, a second input terminal of the detection circuit is connected to the inverting output terminal of the double sampling and amplifying circuit, a third input terminal of the detection circuit is connected to the reference level VREFN, and a fourth input terminal of the detection circuit is connected to the reference level VREFP. After the double sampling and amplifying circuit 3 completes the amplification of the difference between the integration voltage and the reset voltage, the comparator compares this amplified difference with the difference between VREFP and VREFN, and inputs the comparison result to the digital processing module 42.
The digital processing module 42 can store the detection result of each pixel circuit and control the input of the pixel circuit to be grounded or normally operate according to the detection result.
As shown in fig. 1, the ground control module 43 includes a MOS transistor M5, the drain of the MOS transistor M5 is connected to the output terminal of the X-ray sensitive element (replaced by the signal generating circuit 1 in the figure), the source of the MOS transistor M5 is grounded, and the gate of the MOS transistor M5 is connected to the power supply voltage or ground through a switch. When the gate of the MOS transistor M5 is grounded, the current of the signal generating circuit 1 is input to the pixel circuit 2; when the gate of the MOS transistor M5 is connected to the power supply voltage VCC, the MOS transistor M5 is turned on, and the current of the signal generating circuit 1 flows directly to the ground through the MOS transistor M5.
Further, as shown in fig. 2, the pixel circuit 2 includes: an integrating capacitor C1, a signal transmission circuit 22, a reset circuit 23, and a gate readout circuit 24.
One end of the integrating capacitor C1 is connected to an X-ray sensitive element (replaced by a signal generating circuit 1 in the figure) in the detector, and the other end of the integrating capacitor C1 is grounded and used for receiving an input induced current signal and converting the induced current signal into a voltage signal.
A first input terminal of the signal transmission circuit 22 is connected to the integrating capacitor C1, that is, an output terminal of the signal generation circuit 1, a second input terminal of the signal transmission circuit 22 is connected to a first timing control signal TX, and output terminals of the signal transmission circuit 22 are connected to an output terminal of the reset circuit 23 and a first input terminal of the gate readout circuit 24, respectively, to form a floating diffusion node FD; the signal transmission circuit 22 is used for realizing the reset of the integrating capacitor in cooperation with the reset circuit 23 in a reset stage, and opening a signal readout path in a signal readout stage to realize the readout of the voltage of the integrating capacitor C1.
A first input terminal of the reset circuit 23 is connected to the second timing control signal RST, and a second input terminal of the reset circuit 23 is connected to the reset voltage VRST(ii) a The reset circuit 23 is configured to control the reset of the floating diffusion node FD according to the level of the second timing control signal RST, and at the same time, cooperate with the signal transmission circuit 22 in the reset phase to realize the reset of the integrating capacitor C1.
A second input terminal of the gate readout circuit 24 is connected to a third timing control signal SEL; the gate readout circuit 24 is configured to read out the reset voltage and the integrated voltage of the floating diffusion node FD to the output terminal Vout of the gate readout circuit 24 in the signal readout phase.
Specifically, as shown in fig. 2, the signal transmission circuit 22 includes a first NMOS transistor M1, a drain of the first NMOS transistor M1 is used as a first input terminal of the signal transmission circuit, a gate of the first NMOS transistor M1 is used as a second input terminal of the signal transmission circuit, and a drain of the first NMOS transistor M1 is used as an output terminal of the signal transmission circuit 22.
The reset circuit 23 includes a second NMOS transistor M2, a gate of the second NMOS transistor M2 is used as an input terminal of the reset circuit, a drain of the second NMOS transistor M2 is used as an output terminal of the reset circuit 23, and a source of the second NMOS transistor M2 is connected to the reset voltage.
The gated readout circuit 24 comprises a third NMOS transistor M3 and a fourth NMOS transistor M4; the gate of the third NMOS transistor M3 is used as the first input terminal of the gate readout circuit, the drain of the third NMOS transistor M3 is connected to the power supply voltage, the source of the third NMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4, the gate of the fourth NMOS transistor M4 is used as the second input terminal of the gate readout circuit, and the source of the fourth NMOS transistor M4 is used as the output terminal Vout of the gate readout circuit 24.
In one embodiment of the present application, as shown in fig. 1, the number of the pixel circuits 2 is multiple, and the ground control module 43 corresponds to the pixel circuits 2 one to one.
In one embodiment of the present application, as shown in fig. 1, a first input terminal of the dual sampling and amplifying circuit 3 is connected to an output terminal of the pixel circuit, a second input terminal of the dual sampling and amplifying circuit 3 is connected to the timing control signal S/S, a third input terminal of the dual sampling and amplifying circuit 3 is connected to the timing control signal S/R, a fourth input terminal of the dual sampling and amplifying circuit 3 is connected to the timing control signal RO, and a fifth input terminal of the dual sampling and amplifying circuit 3 is connected to the timing control signal SWRThe sixth input end of the double sampling and amplifying circuit 3 is connected to the time sequence control signal Vb; the double sampling and amplifying circuit 3 performs correlated double sampling on the output signal of the pixel circuit, and amplifies the sampling result to realize matching with the input range of the ADC.
In one embodiment of the present application, the CMOS readout circuit further comprises an ADC circuit 5, as shown in fig. 1. The first input end of the ADC circuit 5 is connected with the in-phase output end of the double sampling and amplifying circuit 3, and the second input end of the ADC circuit 5 is connected with the anti-phase output end of the double sampling and amplifying circuit 3; the ADC circuit 5 is configured to perform analog-to-digital conversion on the output of the double sampling and amplifying circuit 3.
Based on the CMOS readout circuit of the direct X-ray detector, the present invention also provides a control method, including:
as shown in fig. 3, before the CMOS readout circuit works normally, the CMOS readout circuit enters a detection mode, which includes four stages of reset, integration, readout, and assignment. In the detection mode, the CMOS readout circuit first enters a reset state, and the integrating capacitor C1 is reset; then, the integration phase is entered, and the integrating capacitor C1 receives the induced current signal inputted by the X-ray sensitive element in the detector, and the voltage rises. The duration of the integration phase of the detection mode is much less than the duration of the integration phase of the normal operation mode, typically less than 20% of the duration of the normal mode section phase. The integration time in the normal operation mode is 10ms in this example, and the integration time in the detection mode is only 100 mus. Then, a reading stage is carried out, signal reading comprises two stages of reset voltage reading and integral voltage reading, a reset voltage signal and an integral voltage signal are read out through the double sampling and amplifying circuit 3 and sent to the detection circuit 4 for detection. And finally, entering an assignment stage, grounding the pixel circuit with the overhigh input signal, namely grounding the output end of the X-ray sensitive element, and ending the detection mode. And entering a normal working mode after the detection mode is finished, wherein the normal working mode comprises three stages of resetting, integrating and reading. Firstly, entering a reset phase, the integrating capacitor C1 is reset; then, the integration phase is started, the integration capacitor C1 receives an induction current signal, and the voltage rises; then, a readout phase is entered, and signal readout comprises two phases of reset voltage readout and integration voltage readout.
As shown in fig. 3, the operation timing of the readout circuit in the detection mode is as follows:
the time period t 0-t 1 is a reset phase, the control signals TX and RST are set to high level, the MOS transistors M1 and M2 are turned on, and the voltages of the integrating capacitor C1 and the FD node are reset to GND.
the time period from t1 to t3 is an integration stage, the control signals TX and RST are set to be low level, the MOS transistors M1 and M2 are closed, the current signal of the sensitive element enters the pixel circuit, and the voltage of the upper electrode plate of the integration capacitor C1 continuously rises.
the period from t2 to t5 is the readout phase. The reading circuit adopts a relevant double sampling working mode, so that the reading phase is divided into the reading of reset voltage and the reading of integral voltage. In the time period from t2 to t3, the control signal TX is set to be high level again, the MOS transistor M1 is turned on, and integration is carried outThe voltage signal of the capacitor C1 is stored to the FD node, the time period from t3 to t4, the control signal SEL and the S/S are set to be high level, the MOS tube M1 is closed, and the voltage signal of the FD node is read out to the capacitor C through M4Sig(ii) a In the time period from t4 to t5, the control signal RST is set to high level again, the MOS transistor M2 is turned on, the FD node is reset again, in the time period from t5 to t6, the control signals SEL and S/R are set to high level, and the reset voltage of the FD node is read out to the capacitor CRST。
the time period t 6-t 7 is the processing assignment phase. The system pair is stored in a capacitor CSigAnd CRSTThe voltage signals are differentiated, and then the actual output voltage value of the pixel circuit is obtained after passing through the switched capacitor amplifier, and then whether the current output of the pixel circuit is greater than the comparison threshold is obtained after passing through the comparator 41, and then the high level or the low level is fed back to the grounding control module 43 on the left side of the detection circuit 4 after passing through the digital processing module 42.
The digital processing module 42 mainly samples and stores the output signal of the comparator 41, and after the readout process of all pixel signals is completed, the signal stored in the digital processing module 42 is output again and fed back to each pixel circuit 2.
Specifically, in one embodiment of the present application, the first column switch SW is used for feeding back whether the pixel circuit in the first column of each row is dead or not1On, switches of other columns are closed, and the output signal of the digital processing module 42 controls the switch SWVCC1And SWGND1After the first row is finished, the second row switch SW2On, switches of other columns are closed, and the output signal of the digital processing module 42 controls the switch SWVCC2And SWGND2Switches SW for all columns are completed in sequenceVCCAnd SWGNDAnd (4) controlling. In this embodiment, for an n × m pixel circuit matrix, n dual sampling and amplifying circuits 3 and m ground control modules 42 need to be configured. For m columns of pixel circuits 2 in the same row, values are assigned in turn by m column switches SW. The design can reduce the circuit arrangement and save the chip area.
If the sensitive element corresponding to a certain pixel circuit is a dead pixel, the output result of the sampling and amplifying circuit is greater than the threshold value of the comparatorThen let the switch SW of the corresponding pixel circuitVCCOpen and close the switch SWGNDWhen the circuit is closed, the input current of the sensing element is grounded through the MOS transistor M5 in the grounding control module 43 corresponding to the pixel circuit and does not enter the pixel circuit, thereby achieving the effect of protecting the circuit.
As shown in fig. 3, after the CMOS readout circuit performs grounding processing on the pixel circuit with too high input through the detection mode, it enters the normal operation mode, and the operation timing sequence is as follows:
the time period t 7-t 8 is a reset phase, the control signals TX and RST are set to high level, the MOS transistors M1 and M2 are turned on, and the voltages of the integrating capacitor C1 and the FD node are reset to GND.
the time period t 8-t 10 is an integration stage, the control signals TX and RST are set to low level, the MOS transistors M1 and M2 are turned off, the current signal of the sensitive element enters the pixel circuit 2, and the voltage of the upper electrode plate of the integrating capacitor C1 continuously rises.
the time period from t9 to t13 is a reading phase, and the reading circuit adopts a related double sampling working mode, so that the reading phase is divided into reading of a reset voltage and reading of an integral voltage. In the time period from t9 to t10, the control signal TX is set to be high level again, the MOS tube M1 is opened, the voltage signal of the integrating capacitor C1 is stored to the FD node, in the time period from t10 to t11, the control signals SEL and S/S are set to be high level, the MOS tube M1 is closed, and the voltage signal of the FD node is read out to the capacitor C4 through the MOS tube M4Sig(ii) a In the time period from t11 to t12, the control signal RST is set to high level again, the MOS transistor M2 is turned on, the FD node is reset again, in the time period from t12 to t13, the control signals SEL and S/R are set to high level, and the reset voltage of the FD node is read out to the capacitor CRST。
the time period from t13 to t14 is the treatment period. The sampling and amplifying circuit 3 is used for storing the data in the capacitor CSigAnd CRSTAnd the voltage signals are subjected to difference, and then the actual output voltage value of the pixel circuit is obtained and output after passing through the switched capacitor amplifier.
Starting at time t14, the readout circuit repeats the above-described normal operation mode stages, and proceeds to the next frame processing.
The invention designs a high-reliability CMOS reading circuit of a direct X-ray detector and a control method, in the embodiment, the integration time in a detection mode is set to be 100 mu s, the input current of a dead pixel is set to be 100pA, the input current of a normal pixel point is set to be 1pA, and the dead pixel current is 100 times of the normal pixel point current. Fig. 4 is a simulation diagram of the circuit in the detection mode, and the simulation result shows that the output voltage value of the dead pixel circuit is much larger than that of the normal pixel point in the detection mode. Fig. 5 shows that in the normal operation mode, the integration time is 10ms, after the dead pixel circuit is grounded, in the normal operation mode, the outputs of the pixel circuits are all-490 mV, and are identified as dead pixels in the subsequent processing, and the other circuits normally output voltage values which are linearly increased according to different input current values.
In an embodiment of the present application, there is also provided a direct type X-ray detector employing the CMOS readout circuit described in the above embodiments.
In summary, the direct type X-ray detector CMOS readout circuit provided by the present invention is a readout circuit with high reliability, and can detect a pixel point with an excessive response of the perovskite X-ray sensitive element and perform grounding processing, so as to prevent the pixel circuit from being damaged due to an excessive input current of the pixel and potentially prevent circuits at other positions from being damaged due to the pixel damage, thereby achieving the purpose of protecting the circuit.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A CMOS reading circuit of a direct X-ray detector is used for reading an induced current signal in the direct X-ray detector and is characterized by comprising a pixel circuit, a double sampling and amplifying circuit and a detection circuit;
the pixel circuit is connected with an X-ray sensitive element in the detector and used for integrating the induced current output by the sensitive element in an integration stage and converting the induced current into an integration voltage and outputting a reset voltage in a reset stage;
the double sampling and amplifying circuit is used for sampling and amplifying the integral voltage and the reset voltage output by the pixel circuit, so that the reading of the induced current is realized;
the input end of the detection circuit is connected to the output end of the double sampling and amplifying circuit, and the output end of the detection circuit is connected to the input end of the pixel circuit and used for detecting whether the X-ray sensitive element is damaged or not and grounding the output end of the damaged X-ray sensitive element.
2. The CMOS readout circuit of claim 1, wherein the detection circuit comprises: the device comprises a comparator, a digital processing module and a grounding control module; the input end of the comparator is connected with the output end of the double sampling and amplifying circuit and is used for comparing the output voltage of the double sampling and amplifying circuit with a reference voltage and sending a comparison result to the digital processing module; the digital processing module is used for controlling the on and off of the grounding control module according to the comparison result of the comparator; the grounding control module is connected to the output end of the X-ray sensitive element and is used for grounding or connecting the output current of the X-ray sensitive element into the pixel circuit under the control of the digital processing module.
3. The CMOS readout circuit of claim 2, wherein said ground control module comprises a MOS transistor, a drain of said MOS transistor is connected to an output terminal of said X-ray sensitive element, a source of said MOS transistor is grounded, and a gate of said MOS transistor is connected to a power supply voltage or ground through a switch.
4. The CMOS readout circuit of claim 1, wherein the pixel circuit comprises: the circuit comprises an integrating capacitor, a signal transmission circuit, a reset circuit and a gating reading circuit;
one end of the integrating capacitor is connected with an X-ray sensitive element in the detector, and the other end of the integrating capacitor is grounded and used for receiving an input induced current signal and converting the induced current signal into a voltage signal;
a first input end of the signal transmission circuit is connected to the integrating capacitor, a second input end of the signal transmission circuit is connected to a first timing control signal TX, and output ends of the signal transmission circuit are respectively connected to an output end of the reset circuit and a first input end of the gating readout circuit to form a floating diffusion node; the signal transmission circuit is used for realizing the reset of the integration capacitor in a reset stage in cooperation with the reset circuit, and opening a signal read-out passage in a signal read-out stage to realize the read-out of the integration voltage;
the first input end of the reset circuit is connected to a second timing control signal RST, and the second input end of the reset circuit is connected to a reset voltage; the reset circuit is used for controlling the reset of the floating diffusion node according to the level of the second time sequence control signal RST and is matched with the signal transmission circuit in the reset stage to realize the reset of the integrating capacitor;
the second input end of the gating readout circuit is connected to a third timing control signal SEL; the gate readout circuit is used for respectively reading out the reset voltage and the integral voltage of the floating diffusion node to the output end Vout of the gate readout circuit in a signal readout stage.
5. The CMOS readout circuit of claim 4 wherein said signal transmission circuit comprises a first NMOS transistor M1, a drain of said first NMOS transistor M1 being a first input of said signal transmission circuit, a gate of said first NMOS transistor M1 being a second input of said signal transmission circuit, and a drain of said first NMOS transistor M1 being an output of said signal transmission circuit.
6. The CMOS readout circuit of claim 4, wherein said reset circuit comprises a second NMOS transistor M2, a gate of said second NMOS transistor M2 is used as an input terminal of said reset circuit, a drain of said second NMOS transistor M2 is used as an output terminal of said reset circuit, and a source of said second NMOS transistor M2 is connected to said reset voltage.
7. The CMOS readout circuit of claim 4 wherein said gated readout circuit comprises a third NMOS transistor M3 and a fourth NMOS transistor M4; the gate of the third NMOS transistor M3 is used as the first input terminal of the gate readout circuit, the drain of the third NMOS transistor M3 is connected to the power supply voltage, the source of the third NMOS transistor M3 is connected to the drain of the fourth NMOS transistor M4, the gate of the fourth NMOS transistor M4 is used as the second input terminal of the gate readout circuit, and the source of the fourth NMOS transistor M4 is used as the output terminal Vout of the gate readout circuit.
8. The CMOS readout circuit according to claim 2, wherein the number of the pixel circuits is plural, and the ground control blocks correspond to the pixel circuits one to one.
9. A method of controlling a CMOS readout circuit according to any one of claims 1 to 8, comprising the steps of:
before the reading circuit works normally, a detection mode is firstly entered, and the following stages of processing are executed in the detection mode:
a reset stage: resetting the integrating capacitor through a reset circuit;
an integration stage: the integrating capacitor receives an induced current signal input by an X-ray sensitive element in the detector;
and (3) a reading stage: reading out the reset voltage signal and the integral voltage signal through the double sampling and amplifying circuit, and sending the signals to a detection circuit for detection;
an assignment stage: the detection circuit grounds the output end of the X-ray sensitive element with the overhigh input induced current signal according to the detection result;
the readout circuit then enters a normal operating mode in which the duration of the integration phase in the detection mode is no more than 20% of the duration of the integration phase in the normal operating mode.
10. A direct X-ray detector comprising a CMOS readout circuit according to any one of claims 1 to 8.
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| CN202011160805.4A CN112422129B (en) | 2020-10-27 | 2020-10-27 | Direct X-ray detector CMOS reading circuit and control method |
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| A Mixed-Signal Spectroscopic-Grade and High-Functionality CMOS Readout Cell for Semiconductor X-γ Ray Pixel Detectors;Stefano Caccia等;《IEEE Transactions on Nuclear Science ( Volume: 55, Issue: 5, Oct. 2008)》;20081208;第2721-2726页 * |
| 全局快门CMOS图像传感器研究进展;刘昌举等;《半导体光电》;20160615(第03期);第4-9页 * |
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