CN114883301B

CN114883301B - Chiplet-based microsystem reconfigurable network topology structure and implementation method

Info

Publication number: CN114883301B
Application number: CN202210474339.XA
Authority: CN
Inventors: 单光宝; 郑彦文; 李国良; 杨银堂; 朱樟明
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2023-03-21
Anticipated expiration: 2042-04-29
Also published as: CN114883301A

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a reconfigurable network topology structure and an implementation method thereof, which mainly solve the problems of the existing micro-system based on a large SoC that the functions are solidified, the expansibility is poor, the design period is long, and the cost is high. The reconfigurable network topology control circuit comprises a reconfigurable network topology control unit (1), a bonding pad (2), a conical through silicon hole (3), a rewiring layer (4), a micro bump (5), a chip (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit and the switch matrix are integrated on a first layer of wafer, and the chipset is integrated on a second layer of wafer; the pad, the conical silicon through hole, the rewiring layer and the micro bump are used for achieving electrical interconnection of the microsystem, and the reconfigurable control unit is used for flexibly configuring the chip and achieving that one set of hardware can rapidly build one or more microsystems with multiple functions. The invention has high function reconstruction capability and expansion capability and can be used for micro-system design.

Description

Chiplet-based microsystem reconfigurable network topology structure and implementation method

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a reconfigurable network topology structure and an implementation method, which can be used for a semiconductor micro-integration system.

Background

A conventional SoC-based microsystem integrates a large number of transistors using a monolithic integration process to construct a system having a specific function.

The problems of function solidification, incompatible process, large design difficulty and high cost exist, and the multitask concurrent requirement of the system cannot be met gradually. The Chiplet is a generalized small-scale hardmac IP with specific functions, can form a flexibly configured microsystem through the flexible combination of the Chiplet, solves the design problem and the cost problem based on the large SoC, and has wide application prospect in the fields of high-performance calculation and radio frequency. Patent document CN202111237938.1 discloses "an arbitrary routing rf switch matrix", which realizes routing of an arbitrary input port rf signal to an arbitrary output port through an N-port rf switch matrix, but cannot realize system-level function reconfiguration. Patent document No. cn202111291800.X discloses "a three-dimensional multi-die interconnection network structure", which mainly realizes the functions of reducing the number of routing hops, shortening the transmission path, and reducing the network delay by reducing the network structure of the on-chip multi-die, and the network also cannot realize the dynamic reconfiguration of the system function.

At present, due to the lack of network topology for realizing the function reconstruction of the Chiplet microsystem, the key points that the Chiplet multiplexing rate is low and the advantages of universality and modularization cannot be fully exerted are solved, the universality and expansibility of an electronic system are influenced, and the development of the reconfigurable, extensible, multifunctional and low-cost microsystem is restricted.

Disclosure of Invention

The invention aims to provide a reconfigurable network topological structure of a microsystem based on a Chiplet and an implementation method thereof to reduce the cost, shorten the research and development period, improve the universality of the microsystem, meet the diversified application requirements,

in order to achieve the purpose, the technical scheme of the invention comprises the following steps:

1. a microsystem reconfigurable network topology structure based on a chip is characterized by comprising a reconfigurable network topology control unit (1), a bonding pad (2), a conical through silicon hole (3), a rewiring layer (4), a micro bump (5), a chip (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit (1) and the switch matrix (7) are integrated on a first layer of wafer, the chip (6) is integrated on a second layer of wafer, and the two layers of wafers are integrated in a three-dimensional mode; the bonding pad (2), the conical silicon through hole (3), the rewiring layer (4) and the micro bump (5) are used for achieving electrical interconnection of the micro system; the reconfigurable control unit (1) is used for flexibly configuring a Chiplet (6) and realizing that one set of hardware quickly constructs one or more microsystems with multiple functions.

Further, the reconfigurable network topology control unit (1) comprises a coding-decoding circuit and a switch matrix state storage circuit, wherein the coding-decoding circuit is used for generating a coding sequence and an enabling signal, the coding sequence is decoded by the decoding circuit to generate a control signal, the control signal is transmitted to the switch matrix storage circuit and stored, and when the switch control signal jumps, the control signal after jumping is transmitted to the switch matrix (7).

Further, the switch matrix (7) comprises: the switch tube driving circuit is used for enhancing the driving capability of a control signal of the switch tube and transmitting an output signal to the switch tube; the switch tube is used for controlling the on-off of a circuit of the reconfigurable network topology, transmitting an enabling signal generated by the coding-decoding circuit after the switch tube is conducted, and transmitting the enabling signal to the signal filtering circuit; the signal filtering circuit is used for filtering noise in the enabling signal, and the filtered enabling signal is transmitted to the signal conditioning circuit; the signal conditioning circuit is used for modulating the waveform of the enabling signal, and transmitting the modulated enabling signal to the signal holding circuit; the signal holding circuit is used for storing the enable signal of each chip and transmitting the enable signal to the corresponding chip when the enable signal jumps.

Further, the chip (6) is a functional chip prepared by selecting Si or GaAs or GaN material and utilizing CMOS or BiCMOS or Bipolar technology, and is connected with the reconfigurable network topology control unit (1) to form a microsystem;

2. a realization method of a microsystem reconfigurable network topology structure based on a chip is characterized by comprising the following steps:

1) Preparing a conical through silicon via on the wafer 1:

etching a through hole on the first layer of silicon wafer by adopting a laser drilling technology, filling a polymer in the through hole, and then ablating the polymer in the hole by using laser to form the through hole with an insulating inner wall;

preparing a TiN barrier layer in the through hole by adopting Physical Vapor Deposition (PVD), preparing a seed layer on the TiN barrier layer by adopting a Physical Vapor Deposition (PVD) process, and filling Cu in the through hole after the seed layer deposition is finished to form a conical silicon through hole;

2) Thinning the first silicon wafer with the conical silicon through hole, namely polishing the front surface of the first silicon wafer by adopting a chemical mechanical polishing process (CMP), and then grinding the back surface of the first silicon wafer by adopting a back grinding process to enable two ends of the conical silicon through hole to be exposed;

3) Sequentially integrating a switch matrix and a reconfigurable network control unit on a first layer of silicon wafer by adopting a CMOS (complementary metal oxide semiconductor) process, and preparing a rewiring layer on the first layer of silicon wafer by adopting a Damascus process to realize the electrical interconnection of the switch matrix and the conical silicon through hole so as to transmit an enabling signal;

4) Manufacturing a first alignment mark after preparing a tapered silicon through hole, a reconfigurable network control unit, a switch matrix and a rewiring layer on a first layer of wafer;

5) Preparing a cavity on the surface of the second layer of wafer by adopting a dry etching process for integrating a chip; reuse of SiO ₂ Passivating the bottom of the chamber and manufacturing a second alignment mark on the surface of the wafer for accurately positioning the placing position of the chip;

6) Placing a chip in the chamber according to the second alignment marker;

7) Preparing an electrical interconnection structure on the second layer of wafer, namely preparing a rewiring layer by adopting a Damascus process, and leading out an enabling end of a chip to the surface of the second layer of wafer by utilizing the rewiring layer; preparing salient points above the rewiring layer by adopting a ball planting process so as to realize electrical interconnection with the conical silicon through holes and bonding the wafer;

8) Filling the cavity with epoxy resin to fix the Chiplet;

9) Thinning the back of the second layer of wafer by adopting a back grinding process, and manufacturing a third alignment marker;

10 Bonding the first layer wafer and the second layer wafer at 300 ℃ by adopting a bump bonding process according to the positions of the first alignment mark and the third alignment mark, and scribing the first layer wafer and the second layer wafer by adopting a laser cutting process;

11 And) carrying out integrated packaging on the scribed modules to obtain a function reconfigurable microsystem based on Chiplet.

Compared with the prior art, the invention has the following advantages:

firstly, the invention effectively overcomes the defects of the prior micro-system based on SoC that the functions are solidified and the utilization rate of hardware resources is low because of dynamically calling the chip through the reconfigurable network topology, not only effectively improves the reuse rate of the chip, but also improves the design efficiency and the robustness of the system, reduces the research and development cost of the micro-system and obtains the micro-system with higher function reconfigurability and higher reliability.

Secondly, the invention effectively overcomes the defect of poor expansibility of the existing microsystem and effectively improves the expansion flexibility of the microsystem because the microsystem is expanded by utilizing the reconfigurable network topology which can be randomly cascaded.

Thirdly, the invention effectively overcomes the defects of incompatible process and large performance optimization difficulty of the existing micro system based on SoC due to the Chiplet construction system prepared by different materials, not only effectively improves the heterogeneous characteristics of the micro system, but also reduces the design cost and obtains a more flexible performance optimization way.

Fourthly, the invention integrates a plurality of wafers through the three-dimensional wafer level integration technology, effectively overcomes the defects of poor product performance uniformity and low preparation efficiency of the existing chip level integration technology, and effectively improves the performance consistency and efficiency during the batch preparation of the micro system.

Drawings

FIG. 1 is a three-dimensional structure diagram of a basic network topology unit with reconfigurable and expandable features;

FIG. 2 is a diagram of a basic network topology unit with reconfigurable and extensible features according to the present invention;

FIG. 3 is a diagram of a network topology unit according to a first embodiment of the present invention after the structure of FIG. 1 is expanded;

FIG. 4 is a diagram of a network topology unit according to a second embodiment of the present invention after expanding the structure of FIG. 1;

FIG. 5 is a diagram of a network topology unit according to a third embodiment of the present invention after expanding the structure of FIG. 1;

FIG. 6 is a schematic of the three-dimensional structure of FIG. 4;

FIG. 7 is a flow diagram of a microsystem implementation of the present invention constructed with a network topology that is an extended three-dimensional structure.

The concrete scheme is as follows

Embodiments of the present invention are further described below with reference to the accompanying drawings.

Referring to fig. 1, the basic network topology unit of the present invention includes a reconfigurable network topology control unit 1, a pad 2, a tapered through silicon via 3, a redistribution layer 4, a micro bump 5, a chip 6, a switch matrix 7, and a plurality of wafers 8; this example employs, but is not limited to, two wafers. The reconfigurable network topology control unit 1 and the switch matrix 7 are integrated on a first layer of wafer, the chip 6 is integrated on a second layer of wafer, and the two layers of wafers are integrated in a three-dimensional mode; the bonding pad 2, the conical silicon through hole 3, the rewiring layer 4 and the micro-bump 5 are used for achieving electrical interconnection of a micro-system. Specifically, after the control unit generates the control signal, the signal is transmitted to the pad 2 first, and then transmitted to the redistribution layer on the first layer of wafer, so as to realize redistribution of the signal; and then, the signal enters a signal path formed by switch matrix reconstruction after flowing through the conical silicon through hole in the first layer of wafer, and finally the signal is enabled to flow through the vertical silicon through hole and the micro-convex point in the second layer of wafer to enter the functional chip. The reconfigurable control unit 1 is used for flexibly configuring a chipset 6, specifically, when application requirements change, the reconfigurable network topology control unit generates a coding sequence and an enabling signal, the coding sequence is decoded to generate a switch tube control signal for controlling a switch matrix, and a signal path is formed; after entering the signal path, the enabling signal is filtered, modulated, stored and the like and then reaches the functional chipset, so that the chipset is dynamically and flexibly configured, and a microsystem with reconfigurable functions is quickly constructed by using a reconfigurable network topology control unit, a bonding pad, a conical silicon through hole, a rewiring layer, a micro-bump, the chipset, a switch matrix and two wafers.

In order to more clearly illustrate the working principle of the reconfigurable and expandable network topology, the invention takes the simplified schematic diagram shown in fig. 2 as an example to illustrate the working principle of basic network topology units, wherein C1 and C2 represent two chiplets with different functions, and S11 to S16 represent 6 switching tubes in a switching matrix. When the application requirement changes, the reconfigurable network topology control unit 1 dynamically configures 6 switch tubes in the switch matrix to generate different enabling signal circulation paths, so as to flexibly call the functions of a chip and a dynamic reconfiguration micro-system. Specifically, when the microsystem only needs to call a first function chip C1, under the configuration of the reconfigurable network topology control unit 1, the first 3 switches S11, S12 and S13 are closed, and the last three switches S14, S15 and S16 are opened; when the microsystem only needs to call a second function chip C2, under the configuration of the reconfigurable network topology control unit 1, the fourteenth switch S14 and the sixteenth switch S16 are closed, and the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13 and the fifteenth switch S15 are opened; when the microsystem needs to call the first function chip C1 and the second function C2, under the adjustment of the reconfigurable network topology control unit, the eleventh switch S11, the fifteenth switch S15, and the sixteenth switch S16 are closed, and the twelfth switch S12, the thirteenth switch S13, and the fourteenth switch S14 are opened. When the microsystem does not need to call the first function chip C1 and the second function chip C2, the thirteenth switch S13 is closed, and the eleventh switch S11, the twelfth switch S12, the fourteenth switch S14, the fifteenth switch S15, and the sixteenth switch S16 are opened.

Taking the structure of fig. 1 as an example, by flexibly configuring a switch matrix in a reconfigurable network topology, a plurality of working modes can be reconfigured. This example gives, but is not limited to, the following three:

first, the expansion of the microsystem can be realized by cascading at an expansion point by using a basic network topology unit, that is, the chip in fig. 1 is expanded to 4, as shown in fig. 3. Different functional reconstructions of the microsystem can be realized through different combinations of the 4 Chiplets:

when the microsystem only calls one function chip, namely only calls a first function chip C1, a second function chip C2, a third function chip C3 or a fourth function chip C4, four system functions can be reconstructed;

when the micro system calls two functions, namely a first function, namely a Chiplet C1, a second function, namely a Chiplet C2, a first function, namely a Chiplet C1, a third function, namely a Chiplet C3, a first function, namely a Chiplet C1, a fourth function, namely a Chiplet C4, a second function, namely a Chiplet C2, a third function, namely a Chiplet C3, a second function, namely a Chiplet C2, a fourth function, namely a Chiplet C4, a third function, namely a Chiplet C3, and a fourth function, namely a Chiplet C4, the micro system can be reconfigured into six system functions;

when the microsystem calls three functions, namely a first function chip C1, a second function chip C2, a third function chip C3, a first function chip C1, a second function chip C2, a fourth function chip C4, a second function chip C2, a third function chip C3 and a fourth function chip C4 are respectively called, and system functions in 3 can be reconstructed;

when the microsystem calls four functions, namely a first function chip C1, a second function chip C2, a third function chip C3 and a fourth function chip C4, one system function can be reconstructed.

Secondly, the basic network topology unit in fig. 1 is extended to a network topology with 3 chiplets, and the structure is shown in fig. 4. Through different combinations of the 3 Chiplets, different functional reconstructions of the microsystem can be realized:

when the microsystem only calls one function, namely only calls a first function, namely, a chip C1, a second function, namely, a chip C2, or a third function, namely, a chip C3, three system functions can be reconstructed;

when the microsystem calls two functions, namely a first function chip C1 and a second function chip C2, a first function chip C1 and a third function chip C3, a second function chip C2 and a third function chip C3 are respectively called, and three system functions can be reconstructed;

when the microsystem calls three functions, namely a first function chip C1, a second function chip C2 and a third function chip C3, one system function may be reconfigured.

Thirdly, taking a reconfigurable network integrating four basic network topology units shown in fig. 1 as an example, the reconfiguration working principle is explained. As shown in FIG. 5, where EN represents the enable signal into the switch matrix, C1-C8 represent chips with different functions, S11-S16, S21-S26, S31-S36, S41-S46 represent the switch tubes in the switch matrix:

when the microsystem needs to call the first, third, fifth and seventh functions, namely, chip C1, C3, C5 and C7, the reconfigurable network topology control unit generates a coding sequence and an enable signal EN. The coding sequence is decoded by a decoding circuit to generate a control signal, the control signal is transmitted to a switch matrix storage circuit and stored, when the switch control signal jumps, the control signal after jumping is transmitted to a switch matrix, the control signal is transmitted to a switch driving circuit after filtering and conditioning to drive a zeroth switch S01, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a zeroth switch S02, a twenty-first switch S21, a twenty-second switch S22, a twenty-second switch S23, a zeroth switch S03, a thirty-first switch S31, a thirty-second switch S32, a thirty-third switch S33, a zeroth fourth switch S4, a forty-first switch S41, a forty-second switch S42 and a forty-third switch S43 to be closed, the rest switches are opened, and an enable signal EN is guided to pass through a conical silicon through hole in a first layer wafer and transmitted to a first, third, fifth, seventh, third and third functions Chiplec 1, C3, C5 and C7 in a second layer wafer to construct a microsystem with a function;

when the microsystem needs to call the second, fourth, sixth and eighth functions, chip C2, C4, C6 and C8, the reconfigurable network topology control unit generates a coding sequence and an enabling signal EN. The coded sequence generates a control signal after being decoded by a decoding circuit, the control signal is transmitted to a switch matrix storage circuit and stored, when the switch control signal jumps, the jump control signal is transmitted to a switch matrix, the control signal is transmitted to a switch driving circuit after being filtered and conditioned, the control signal drives a first switch S01, a fourteenth switch S14, a fifteenth switch S15, a second switch S2, a twenty-fourth switch S24, a twenty-fifth switch S25, a third switch S3, a thirty-fourth switch S34, a thirty-fifth switch S35, a fourth switch S04, a fourth switch S44 and a forty-fifth switch S45 to be closed, the rest switches are disconnected, an enable signal EN is guided to pass through a conical silicon through hole in a first layer of wafer and transmitted to enable ends of a second, a fourth, a sixth and an eighth function chip C2, a C4, a C6 and a C8 in a second layer of wafer, and a micro-system with a function B is constructed;

when the microsystem needs to call the functions of chips C1-C8, the reconfigurable network topology control unit generates a coding sequence and an enabling signal EN. The coded sequence generates a control signal after being decoded by a decoding circuit, the control signal is transmitted to a switch matrix storage circuit and stored, when the switch control signal jumps, the jump control signal is transmitted to a switch matrix, the control signal is transmitted to a switch driving circuit after being filtered and conditioned, the switch driving circuit drives a zeroth switch S01, an eleventh switch S11, a fifteenth switch S15, a sixteenth switch S16, a zeroth second switch S02, a twenty-first switch S21, a twenty-fifth switch S25, a twenty-sixth switch S26, a zeroth switch S03, a thirty-first switch S31, a thirty-first switch S35, a thirty-sixth switch S36, a zeroth fourth switch S04, a forty-first switch S41, a forty-fifth switch S45 and a forty-sixth switch S46 to be closed, the rest switches are opened, and an enable signal EN is guided to pass through a conical silicon through hole in a first layer wafer and transmitted to an enable end of functions Chiplet C1-C8 in a second layer wafer, so as to construct a microsystem with a C function;

similarly, when the micro-system needs to reconstruct other functions, the reconfigurable network topology control unit generates a coding sequence and an enable signal EN, the control signal controls the switch matrix to form a signal path, the enable signal is processed and then reaches a functional chipset through the signal path, the function of dynamically configuring the functional chipset is achieved, and the dynamic reconfiguration of the functions of the micro-system is achieved. The reconfigurable network topology shown in fig. 4 has symmetry, so that the enable signal EN is transmitted to different key chiplets for the same time, and the response symmetry of the chiplets is improved.

Compared with the existing method for turning off the enabling signal, when the system function is reconstructed, the enabling signal can be respectively configured for each function chip in the network, that is, when the microsystem does not need to call any function chip in the network, the calling of other functions chips is not affected, and the reconstruction flexibility is higher.

Referring to fig. 6, the expanded network topology unit structure of fig. 4 is integrated in the vertical direction to obtain a three-dimensional structure, that is, 4 switch matrices, 1 control unit, 8 functional chips, 4 redistribution layers, 32 micro-bumps, and 24 tapered through-silicon vias are integrated on two wafers, respectively, where:

integrating 24 conical silicon through holes, 16 micro bumps and 2 rewiring layers on a first layer of wafer; according to the cross structure, a first switch matrix, a second switch matrix, a third switch matrix and a fourth switch matrix are integrated; integrating a control unit above the switch matrix;

according to the cross structure, 2 functional chips are respectively integrated in the four directions of the second layer of wafer; integrating 2 layers of rewiring layers and 16 micro-bumps;

and bonding the first layer of wafer and the second layer of wafer to obtain the microsystem with the three-dimensional structure.

When the micro-system needs to work, the signal generated by the control unit controls the switch matrix to form a signal path, the enable signal EN is guided to flow through the conical silicon through hole on the first layer of wafer, then through the micro-convex point and then through the rewiring layer on the surface of the second layer of wafer, finally, the corresponding function chip enable end in the second layer of wafer is reached, and different function reconstruction of the micro-system is realized through combination of different chips.

Referring to fig. 7, the method for making a reconfigurable network topology three-dimensional structure of the present invention provides the following three embodiments

Embodiment 1, manufacturing N reconfigurable microsystems which integrate 1 basic network topology unit structure and have 2 function chips;

step 1, preparing a conical through silicon hole on a first layer of silicon wafer.

Because the enable signal in the reconfigurable network topology needs to be transmitted through the tapered silicon through hole, the tapered silicon through hole which meets the signal transmission has the characteristics of small density and small quantity, and therefore the tapered silicon through hole is etched on the first layer of silicon wafer by adopting the laser drilling technology with higher cost performance, and the method is specifically realized as follows:

1.1 Using laser with frequency of 30KHz, wavelength of 355nm, pulse width of 50ns, pulse energy of 300 muj and spot diameter of 15 μm to etch 6 conical silicon through holes on a silicon wafer with thickness of 155 μm;

1.2 Filling polymers in the through holes, and ablating the polymers in the 6 through holes by using laser with the power of 1KW to form the through holes with insulating inner walls;

1.3 Physical Vapor Deposition (PVD) is adopted to prepare a TiN barrier layer by sputtering under the process conditions that the inert gas is argon, the sputtering target material is TiN, the frequency of the radio frequency source is 13.56MHz, the pre-sputtering power is 40W, the sputtering power is 20W and the sputtering time is 10 min;

1.4 Preparing a tapered silicon through hole seed layer on the barrier layer by adopting a Physical Vapor Deposition (PVD) process, and selecting CuSO with the concentration of 0.5mol/L ₄ And filling the through hole on the seed layer as electroplating solution to finally obtain the conical through silicon hole.

And 2, thinning the first layer of wafer with the conical through silicon holes.

In order to realize enabling signal transmission, two ends of the conical silicon through hole are required to be completely exposed, so that the front surface of the first layer of wafer is polished by adopting a chemical mechanical polishing process CMP to realize the thickness reduction, and the method is specifically realized as follows:

2.1 Placing the first layer of wafer on a silicon wafer holder, selecting an acidic chemical solution with pH of 3.5 and SiO with diameter of 100 μm ₂ Polishing the wafer 1 by using polishing liquid consisting of particles to enable two ends of the conical silicon through hole to be exposed;

2.2 Adopting an electroplating ball-planting process to prepare the cylindrical micro-bump at the lower side port of the conical through-silicon-via by adopting an electroplating material of Cu and at an electroplating speed of 0.2 mu m/min.

And 3, integrating a control unit on the thinned first layer of wafer.

Under the condition that the annealing temperature is 1000 ℃, a switch matrix is prepared on the front surface of a first wafer by photoetching, exposing, developing, depositing and etching by adopting a CMOS (complementary metal oxide semiconductor) process, and then a control unit is prepared on the switch matrix by carrying out secondary photoetching, exposing, developing, depositing and etching;

and 4, preparing a rewiring layer on the first layer of wafer after the control unit is integrated.

4.1 Adopting damascene process to prepare rewiring layer, i.e. firstly adopting silicon nitride to deposit diffusion barrier layer on the surface of first layer wafer, then depositing SiO ₂ A dielectric layer;

4.2 In SiO ₂ Patterning the surface of the dielectric layer, and etching the patterned redundant dielectric layer;

4.3 Depositing a diffusion barrier layer and a seed layer on the surface of the etched patterned dielectric layer, and performing electroplating and chemical mechanical polishing again to obtain a rewiring layer.

And 5, preparing a first alignment mark on the surface of the first layer of wafer after the rewiring layer is prepared.

And preparing a first cross-shaped alignment mark in the passive area on the surface of the first layer of wafer by adopting an anodic mark process, wherein the line length is 140 microns, and the line width is 30 microns.

And 6, preparing a cavity on the second layer of wafer.

6.1 Preparing a cavity on the surface of the two-layer wafer by adopting a dry etching process;

6.2 Using SiO ₂ And the bottom of the cavity is passivated by using an insulating medium to realize the electrical insulation between the chip and the wafer.

And 7, preparing a second alignment mark at the bottom of the second layer of wafer chamber.

And preparing a second cross-shaped alignment mark at the central position of the bottom of the second layer of wafer chamber by adopting a positive standard process, wherein the length of the cross-shaped alignment mark is 140 mu m, and the line width of the cross-shaped alignment mark is 30 mu m.

And 8, placing 2N chips in the second-layer wafer chamber.

And placing the 2N functional Chiplets on an alignment machine, and placing the 2N functional Chiplets in the chamber according to the positions of the cross alignment markers in the second layer wafer chamber.

And 9, preparing an interconnection structure on the surface of the second layer of wafer on which the chip is placed.

9.1 Damascene process for making rewiring layerFirstly, silicon nitride is adopted to deposit a diffusion barrier layer on the surface of a second layer of wafer, and then SiO is deposited ₂ A dielectric layer;

9.2 Patterning the surface of the dielectric layer, and etching the patterned redundant dielectric layer;

9.3 Depositing a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer, and then electroplating;

9.4 Polishing the electroplated layer by adopting a chemical mechanical polishing process to finally obtain the rewiring layer.

9.5 Using Cu material on the second wafer layer by ball-planting process, and electroplating to form cylindrical micro-bumps at an electroplating rate of 0.3 μm/min.

And step 10, filling the second layer wafer cavity with the micro bumps.

Filling the filling cavity by using epoxy resin as a material, and removing the epoxy resin higher than the surface of the second layer of wafer by adopting a chemical mechanical polishing process;

and 11, thinning the back of the second layer of wafer.

And grinding the back surface of the second layer of wafer by adopting a coarse grinding mode, performing fine grinding when the thickness of the second layer of wafer is 100 mu m, and polishing the back surface of the second layer of wafer by adopting a chemical mechanical polishing process when the thickness of the wafer is 40 mu m.

And step 12, preparing a third bit mark on the back of the thinned second layer of wafer.

And preparing a third cross-shaped alignment mark on the back surface of the second layer of wafer by adopting a positive standard process, wherein the length of the cross-shaped alignment mark is 140 micrometers, and the line width is 30 micrometers.

And step 13, bonding the wafer.

And bonding the two wafers by adopting a hot-pressing bonding process under the conditions that the bonding pressure is 200KPa, the bonding temperature is 300 ℃ and the temperature rise rate is 6 ℃/min.

And step 14, dicing and packaging the bonded wafer.

And cutting the bonded wafer by adopting laser with the power of 1KW to obtain N three-dimensional circuit modules, integrating the N three-dimensional modules obtained by scribing on a packaging substrate and packaging a shell to obtain N functional reconfigurable microsystems with 2 chips.

In embodiment 2, N reconfigurable microsystems are manufactured and integrated with 2 basic network topology units and 4 chiplets.

Step one, preparing a conical through silicon hole on a first layer of silicon wafer.

Etching 12 conical silicon through holes on a silicon wafer with the thickness of 100 mu m by using a laser instrument under the conditions that the laser frequency is 30KHz, the wavelength is 355nm, the pulse width is 50ns, the pulse energy is 300 mu j and the spot diameter is 15 mu m, filling polymers in the through holes, and ablating the polymers in the 12 through holes by using laser with the power of 1KW to form the through hole with an insulating inner wall;

setting the technological conditions that the inert gas is argon, the sputtering target material is TiN, the frequency of a radio frequency source is 13.56MHz, the pre-sputtering power is 50W, the sputtering power is 30W and the sputtering time is 5min, and preparing a TiN barrier layer sputtered on the insulating surface of the through hole by adopting Physical Vapor Deposition (PVD); preparing a conical silicon through hole seed layer on the barrier layer by adopting a Physical Vapor Deposition (PVD) process, and selecting CuSO with the concentration of 1mol/L ₄ And filling the through hole on the seed layer as electroplating liquid to finally obtain the conical silicon through hole.

And step two, thinning the first layer of wafer with the prepared tapered through silicon holes.

The specific implementation of this step is the same as step 2 of example 1.

And step three, integrating a control unit on the thinned first layer of wafer.

The specific implementation of this step is the same as step 3 of example 1.

And fourthly, preparing a rewiring layer on the first layer of wafer after the control unit is integrated.

The specific implementation of this step is the same as step 4 of example 1.

And step five, preparing a first alignment mark on the surface of the first layer of wafer after the rewiring layer is prepared.

The specific implementation of this step is the same as step 5 of example 1.

And step six, preparing a cavity on the second layer of wafer.

The specific implementation of this step is the same as step 6 of example 1.

And step seven, preparing a second alignment mark at the bottom of the second layer of wafer chamber.

The specific implementation of this step is the same as step 7 of example 1.

And step eight, placing a chip in the second layer of wafer chamber.

And placing the 4N functional Chiplets on an alignment machine, and placing the 4N functional Chiplets in the chamber according to the positions of the cross alignment markers in the second layer wafer chamber.

And step nine, preparing an interconnection structure on the surface of the second layer of wafer on which the chip is placed.

9a) Adopting a Damascus process to prepare a rewiring layer, namely firstly adopting Si ₃ N ₄ Depositing a diffusion barrier layer on the surface of the second layer of wafer, and then depositing SiO ₂ A dielectric layer;

9b) Patterning the surface of the dielectric layer, and etching the patterned redundant dielectric layer;

9c) And depositing a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer, electroplating, and polishing the electroplated layer by adopting a chemical mechanical polishing process to finally obtain a rewiring layer.

9d) And electroplating a cylindrical micro-bump on the second layer of wafer by adopting a ball-planting process and adopting a Cu material at an electroplating speed of 0.4 mu m/min.

Step ten, filling the second layer wafer cavity with the micro-bumps.

The specific implementation of this step is the same as step 10 of example 1.

And step eleven, thinning the back of the second layer of wafer.

And grinding the back surface of the second layer of wafer by adopting a coarse grinding mode, performing fine grinding when the thickness of the second layer of wafer is 80 microns, and polishing the back surface of the second layer of wafer by adopting a chemical mechanical polishing process when the thickness of the wafer is 30 microns.

And step twelve, preparing a third bit mark on the back of the thinned second layer of wafer.

The specific implementation of this step is the same as step 12 of example 1.

And step thirteen, bonding the wafer.

And bonding the two wafers by adopting a hot-press bonding process under the conditions that the bonding pressure is 200KPa, the bonding temperature is 200 ℃, and the temperature rise rate is 5 ℃/min.

And fourteenth, scribing and packaging the bonded wafer.

And cutting the bonded wafer by adopting a laser instrument with the power of 1KW to obtain N three-dimensional circuit modules, integrating N modules containing 4 functional chips by scribing, integrating the N modules on a packaging substrate, and packaging a shell to obtain N functional reconfigurable microsystems integrating the 4 chips.

In embodiment 3, N reconfigurable microsystems each having 1 basic network topology unit and 3 function chiplets are manufactured.

And step A, preparing a conical through silicon hole on the first layer of silicon wafer.

The method is characterized in that a laser drilling technology is adopted to etch a conical silicon through hole on a first layer of silicon wafer, and the method is specifically realized as follows:

a1 Using laser with frequency of 30KHz, wavelength of 300nm, pulse width of 50ns, pulse energy of 300 muj and spot diameter of 10 μm to etch 24 conical through-silicon vias on a silicon wafer with thickness of 100 μm;

a2 Filling polymer in the through holes, and ablating the polymer in the 24 through holes by using laser with the power of 1KW to form the through holes with insulating inner walls;

a3 Adopting Physical Vapor Deposition (PVD) to prepare a TiN barrier layer by sputtering under the process conditions that the inert gas is argon, the sputtering target material is TiN, the frequency of the radio frequency source is 13.56MHz, the pre-sputtering power is 60W, the sputtering power is 40W and the sputtering time is 5 min;

a4 Preparing a tapered silicon through hole seed layer on the barrier layer by adopting a Physical Vapor Deposition (PVD) process, and selecting CuSO with the concentration of 1.5mol/L ₄ And filling the through hole on the seed layer as electroplating solution to finally obtain the conical through silicon hole.

And step B, thinning the first layer of wafer with the tapered through silicon holes.

b1 Placing the first layer of wafer on a silicon wafer holder, selecting an acidic chemical solution with pH of 4 and SiO with a diameter of 800 μm ₂ Polishing both sides of the first layer of wafer by using polishing liquid consisting of particles to enable both ends of the conical silicon through hole to be exposed;

b2 Adopting an electroplating ball-planting process to prepare the cylindrical micro-bump at the lower side port of the conical through-silicon-via by adopting an electroplating material of Cu-Pb at an electroplating speed of 0.2 mu m/min.

And step C, integrating a control unit on the thinned first layer of wafer.

The specific implementation of this step is the same as step 3 of example 1.

And D, preparing a rewiring layer on the first layer of wafer after the control unit is integrated.

The specific implementation of this step is the same as step 4 of example 1.

And E, preparing a first alignment mark on the surface of the first layer of wafer after the rewiring layer is prepared.

The specific implementation of this step is the same as step 5 of example 1.

And step F, preparing a chamber on the second layer of wafer.

The specific implementation of this step is the same as step 6 of example 1.

And G, preparing a second alignment mark at the bottom of the second layer of wafer chamber.

The specific implementation of this step is the same as step 7 of example 1.

And H, placing a chip in the second-layer wafer chamber.

And placing the 3N functional chips on an alignment machine, and placing the 3N functional chips in the chamber according to the positions of the cross alignment markers in the second layer wafer chamber.

And step I, preparing an interconnection structure on the surface of the second layer of wafer on which the chip is placed.

I1 Adopting damascene process to prepare rewiring layer, i.e. firstly adopting silicon nitride to deposit diffusion barrier layer on the surface of second layer wafer, then depositing SiO ₂ A dielectric layer; patterning the surface of the dielectric layer, and etching the patterned redundant dielectric layer;

i2 Depositing a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer in sequence, electroplating on the surface of the seed layer, and polishing the electroplated layer by adopting a chemical mechanical polishing process to finally obtain a rewiring layer;

i3 Adopting Cu-Sn material on the second layer of wafer by ball-planting process, and electroplating to form cylindrical micro-bumps at an electroplating rate of 0.2 μm/min.

And step J, filling the second layer wafer cavity with the micro bumps.

The specific implementation of this step is the same as step 10 of example 1.

And K, thinning the back of the second layer of wafer.

The specific implementation of this step is the same as step 11 of example 1.

And step L, preparing a third bit mark on the back of the thinned second layer of wafer.

The specific implementation of this step is the same as step 12 of example 1.

And step M, bonding the wafer.

And step N, scribing and packaging the bonded wafer.

And cutting the bonded wafer by adopting laser with the power of 1KW to obtain a circuit module, scribing to obtain N modules with 3 Chiplets integrated inside, integrating the N modules on a packaging substrate, and packaging a shell to obtain N functional reconfigurable microsystems integrating the 3 Chiplets.

The foregoing description is only three specific examples of the present invention and is not intended to limit the invention in any way, and it will be apparent to those skilled in the art that various changes and modifications in form and detail may be made without departing from the principles and structures of the invention, after understanding the principles and principles of the invention, but the basic inventive concept is intended to be covered by the appended claims.

Claims

1. A microsystem reconfigurable network topology structure based on a chip is characterized by comprising a reconfigurable network topology control unit (1), a bonding pad (2), a tapered silicon through hole (3), a rewiring layer (4), micro bumps (5), a chip (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit (1) and the switch matrix (7) are integrated on a first layer of wafer, the chip (6) is integrated on a second layer of wafer, and the two layers of wafers are integrated in a three-dimensional mode; the bonding pad (2), the conical silicon through hole (3), the rewiring layer (4) and the micro bump (5) are used for achieving electrical interconnection of the micro system; the reconfigurable network topology control unit (1) is used for flexibly configuring a chip (6) and realizing that one set of hardware quickly constructs one or more microsystems with multiple functions.

2. The structure according to claim 1, characterized in that the reconfigurable network topology control unit (1) comprises a coding-decoding circuit and a switch matrix state storage circuit, wherein the coding-decoding circuit is used for generating a coding sequence and an enabling signal, the coding sequence is decoded by the decoding circuit to generate a control signal which is transmitted to the switch matrix storage circuit and stored, and when the control signal jumps, the control signal after jumping is transmitted to the switch matrix (7).

3. An arrangement according to claim 1, characterized in that the switch matrix (7) comprises:

the switching tube driving circuit is used for enhancing the driving capability of a control signal of the switching tube, and an output signal of the switching tube driving circuit is transmitted to the switching tube;

the switching tube is used for controlling the on-off of a circuit of the reconfigurable network topology, transmitting an enabling signal generated by the coding-decoding circuit after the switching tube is switched on, and transmitting the enabling signal to the signal filtering circuit;

the signal filtering circuit is used for filtering noise in the enabling signal, and the filtered enabling signal is transmitted to the signal conditioning circuit;

the signal conditioning circuit is used for modulating the waveform of the enabling signal and transmitting the modulated enabling signal to the signal holding circuit;

and the signal holding circuit is used for storing the enabling signal of each chip and transmitting the enabling signal to the corresponding chip when the enabling signal jumps.

4. The structure of claim 1, wherein the Chiplet (6) is a functional chip made of Si, gaAs or GaN material by using CMOS, biCMOS or Bipolar process, and is connected with the reconfigurable network topology control unit (1) to form a microsystem.

5. A realization method of a micro-system reconfigurable network topological structure based on Chiplet is characterized by comprising the following steps:

1) Preparing a conical through silicon via on a wafer:

preparing a TiN barrier layer in the through hole by adopting Physical Vapor Deposition (PVD), preparing a seed layer on the TiN barrier layer by adopting a Physical Vapor Deposition (PVD) process, and filling Cu in the through hole after the seed layer is deposited to form a tapered silicon through hole;

2) Thinning the first silicon wafer with the conical silicon through hole, namely polishing the first silicon wafer by adopting a chemical mechanical polishing process CMP (chemical mechanical polishing) to expose two ends of the conical silicon through hole;

6) Placing a chip in the chamber according to the second alignment mark;

7) Preparing an electrical interconnection structure on the second layer of wafer, namely preparing a rewiring layer by adopting a Damascus process, and leading out an enabling end of a chip to the surface of the second layer of wafer by utilizing the rewiring layer; preparing a salient point above the rewiring layer by adopting a ball mounting process so as to realize electrical interconnection with the conical silicon through hole and bonding with the wafer;

8) Filling the cavity with epoxy resin to fix the chip;

6. The method as claimed in claim 5, wherein the physical vapor deposition PVD is adopted in the step 1), and the process conditions are as follows:

the inert gas used for sputtering is argon, the sputtering target material is TiN, the pre-sputtering power is 40-60W, the sputtering power is 20-30W, and the sputtering time is 8-10min.

7. The method according to claim 5, wherein the CMOS process conditions used in step 3) are: the thickness of the silicon wafer is 0.1mm-1.5mm, and the annealing temperature is 1000-1200 ℃; the Damascus process conditions are as follows: the diffusion barrier layer is made of TiN, the metal material is Cu, the inert gas is argon, the circulation time is 100-600s, and the temperature is 20-350 ℃.

8. The method as claimed in claim 5, wherein the step 6) is performed by aligning the mark with a positive mark process, wherein the shape of the mark is a cross and the side length of the mark is 200-350 μm.

9. The method as claimed in claim 5, wherein the ball mounting process conditions in the step 7) are as follows:

the bump material is Cu, the height is 80-100 μm, and the electroplating speed is 0.2-0.4 μm/min.

10. The method according to claim 5, wherein the laser cutting process conditions in the step 10) are as follows:

the laser power is 1-1.5KW.