CN114843176B - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN114843176B CN114843176B CN202210785556.0A CN202210785556A CN114843176B CN 114843176 B CN114843176 B CN 114843176B CN 202210785556 A CN202210785556 A CN 202210785556A CN 114843176 B CN114843176 B CN 114843176B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
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- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a manufacturing method of a semiconductor structure, which belongs to the technical field of semiconductor manufacturing and comprises the following steps: providing a substrate; forming a plurality of zero alignment marks on the substrate; forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer covers the zero alignment mark and part of the substrate; implanting ions into the substrate by taking the patterned photoresist layer as a mask to form a doped region; depositing an isolation layer on the substrate, wherein the isolation layer covers the doped region; and carrying out high-temperature annealing on the doped region. The manufacturing method of the semiconductor structure can improve the quality of the semiconductor structure.
Description
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor structure.
Background
Power device chips can be generally classified into chips having an epitaxial layer and chips without an epitaxial layer. When an integrated chip having an epitaxial layer is fabricated, an ion implanted region is defined prior to deposition of the epitaxial layer and ions are implanted in the substrate to form a doped region. After the doped region is formed, a high-temperature annealing process is performed on the doped region. However, during high temperature annealing, implanted ions are easily diffused out, thereby affecting the quality of semiconductor integrated devices.
Disclosure of Invention
The invention aims to provide a method for manufacturing a semiconductor structure, which can improve the quality of the semiconductor structure.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate;
forming a plurality of zero alignment marks on the substrate;
forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer covers the zero alignment mark and part of the substrate;
implanting ions into the substrate by taking the patterned photoresist layer as a mask to form a doped region;
depositing an isolation layer on the substrate, wherein the isolation layer covers the doped region; and
and carrying out high-temperature annealing on the doped region.
In an embodiment of the present invention, a method for depositing an isolation layer on the substrate includes: the separation layer is formed by decomposition using tetraethoxysilane.
In an embodiment of the invention, the thickness of the isolation layer is 1000 to 4000 angstroms.
In an embodiment of the present invention, the method for manufacturing the semiconductor structure further includes: and forming a pad oxide layer on the substrate, wherein the thickness of the pad oxide layer is 80-500 angstroms.
In an embodiment of the present invention, the step of forming the isolation layer includes:
placing the substrate with the pad oxide layer in a reaction chamber;
presetting the temperature and pressure of the reaction chamber; and
and introducing tetraethoxysilane and oxygen-containing gas into the reaction cavity, wherein the tetraethoxysilane and the oxygen-containing gas react to generate silicon dioxide and the silicon dioxide is deposited on the surface of the pad oxide layer.
In an embodiment of the present invention, the oxygen-containing gas is oxygen or ozone.
In an embodiment of the present invention, when the tetraethoxysilane and the oxygen-containing gas are introduced into the reaction chamber, nitrogen gas is introduced into the reaction chamber at the same time.
In an embodiment of the invention, the doped region includes a first type doped region and a second type doped region, and the method for manufacturing the semiconductor structure includes the following steps:
forming a first photoresist layer on the zero alignment mark and a part of the pad oxide layer;
implanting first type ions into the substrate by taking the first photoresist layer as a mask to form a first type doped region;
forming a first isolation layer on the pad oxide layer, and performing high-temperature annealing on the first type doped region;
forming a second photoresist layer on the zero alignment mark and a part of the pad oxide layer;
implanting second type ions into the substrate by taking the second photoresist layer as a mask to form a second type doped region; and
and forming a second isolation layer on the pad oxide layer, and carrying out high-temperature annealing on the second type doping region.
In an embodiment of the invention, when the high-temperature annealing is performed on the doped region, the temperature of the high-temperature annealing is 1000 ℃ to 1250 ℃, and the time of the high-temperature annealing is 80min to 200 min.
In an embodiment of the present invention, after performing high temperature annealing on the doped region, the method for manufacturing the semiconductor structure further includes: and removing the isolation layer, forming an epitaxial layer on the substrate, and covering the zero alignment mark with the epitaxial layer.
In the manufacturing method of the semiconductor structure, the doped region is formed in the substrate, and after the doped region is formed, the isolation layer is deposited on the substrate, and the high temperature annealing treatment is performed on the doped region. The quality of the diffused doped region can be ensured, a flat substrate surface can be formed, and the growth of a later epitaxial layer and the formation of a subsequent semiconductor integrated device are facilitated. The manufacturing method of the semiconductor structure can improve the quality of a semiconductor integrated device.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure.
Fig. 2 is a schematic structural diagram of forming a pad oxide layer and a pad nitride layer in the present embodiment.
Fig. 3 is a schematic structural diagram of forming a null alignment mark in this embodiment.
FIG. 4 is a schematic diagram illustrating a structure of removing the pad nitride layer in the present embodiment.
Fig. 5 is a flowchart of a method for forming a first-type doped region and a second-type doped region in the present embodiment.
FIG. 6 is a structural diagram illustrating the formation of a first photoresist layer in this embodiment.
Fig. 7 is a schematic structural diagram of forming a first-type doped region in the present embodiment.
Fig. 8 is a schematic structural diagram of forming a first isolation layer in this embodiment.
Fig. 9 is a schematic structural diagram of the present embodiment in which the first isolation layer is removed.
FIG. 10 is a structural diagram illustrating the formation of a second photoresist layer in this embodiment.
Fig. 11 is a schematic structural diagram of forming a first-type doped region in the present embodiment.
Fig. 12 is a schematic structural diagram of forming a second isolation layer in this embodiment.
Fig. 13 is a schematic structural diagram of the second isolation layer removed in this embodiment.
Fig. 14 is a schematic structural diagram of an epitaxial layer formed in the present embodiment.
Description of reference numerals:
100 a substrate; 101 pad oxide layer; 102 pad nitride layer; 103 zero position alignment mark; 1041 a first photoresist layer; 1042 second photoresist layer; 1051 a first opening; 1052 second opening; 1061 a first type doped region; 1062 a second type doped region; 1071 a first isolation layer; 1072 a second isolation layer; 108 epitaxial layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.
The monolithic integration technology can integrate a bipolar device, a Complementary Metal Oxide Semiconductor (cmos) device, and a Diffused Metal Oxide Semiconductor (DOMS) device on the same chip. The chip integrates the advantages of high transconductance and strong load driving capability of a bipolar device, high CMOS integration level and low power consumption. In the substrate, a plurality of doped regions of different types or the same type need to be formed to form the doped region of each semiconductor device on the chip. The type of each doped region may be set according to the type of each semiconductor device. In the invention, a method for manufacturing a semiconductor structure with a high-performance doped region is provided.
Referring to fig. 1, the present invention provides a method for fabricating a semiconductor structure, which includes steps S11 to S19.
S11, providing a substrate.
And S12, forming a pad oxide layer and a pad nitride layer on the substrate.
And S13, etching the substrate to form a plurality of zero alignment marks.
And S14, removing the pad nitride layer.
S15, forming a patterned photoresist layer on the pad oxide layer.
And S16, implanting ions into the substrate by using the patterned photoresist layer as a mask to form a doped region.
S17, forming an isolation layer on the pad oxide layer.
And S18, carrying out high-temperature annealing on the doped region.
And S19, forming an epitaxial layer on the substrate, wherein the epitaxial layer covers the zero position alignment mark.
Referring to fig. 1 and 2, in an embodiment of the invention, the substrate 100 is, for example, a silicon substrate for forming a semiconductor structure, and the substrate 100 may include a base material and a silicon layer disposed above the base material, for example, silicon (Si), silicon carbide (SiC), sapphire (Al) 2 O 3 ) Gallium arsenide (GaAs), lithium aluminate (LiAlO) 2 ) And a silicon layer formed on the substrate. In this embodiment, different types of ions may be implanted into the silicon layer to form doped regions.
Referring to fig. 1 to 2, in the process of performing step S12, in an embodiment of the invention, first, the surface of the substrate 100 may be cleaned to remove impurities on the surface of the substrate 100, and then a pad oxide layer 101 is formed on the substrate 100, wherein the pad oxide layer 101 covers the substrate 100. In the present invention, the pad oxide layer 101 is, for example, a silicon dioxide layer, and the thickness of the pad oxide layer 101 is, for example, 80 angstroms to 500 angstroms. In the present embodiment, the thickness of the pad oxide layer 101 is, for example, 100 angstroms. In this embodiment, the pad oxide layer 101 with a desired size can be rapidly formed by a wet oxidation method or a dry oxidation method of a thermal oxidation method, and the pad oxide layer 101 formed by the thermal oxidation can have a good buffer effect, has good adhesion between the substrate 100 and the pad nitride layer 102, and can be easily removed in a subsequent process. Of course, the cvd is also suitable for forming the pad oxide layer 101, and the embodiment is not limited thereto. In the present embodiment, the pad oxide layer 101 may serve as a protection layer for the substrate 100, and protect the substrate 100 in the subsequent operation, so as to prevent the substrate 100 from being damaged. And the pad oxide layer 101 may serve as a buffer layer to improve the stress between the substrate 100 and the pad nitride layer 102.
Referring to fig. 1 and 2, in one embodiment of the present invention, after forming the pad oxide layer 101, a pad nitride layer 102 is formed on the pad oxide layer 101, and the pad nitride layer 102 covers the pad oxide layer 101. In the present embodiment, the pad nitride layer 102 is, for example, a silicon nitride layer. In other embodiments, the pad nitride layer 102 may be various nitrogen-containing compounds such as oxynitride or metal nitride. In the present invention, the pad nitride layer 102 may be formed on the pad oxide layer 101 by a Low Pressure Chemical Vapor Deposition (LPCVD) method, a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, or the like. Specifically, for example, a substrate 100 with a pad oxide layer 101 is placed in a reaction chamber filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2Torr to 10Torr and a temperature of, for example, 700 ℃ to 800 ℃ to deposit a pad nitride layer 102. And the thickness of the pad nitride layer 102 can be adjusted by controlling the high temperature reaction time. In the present embodiment, the thickness of the pad nitride layer 102 ranges from 1000 angstroms to 1500 angstroms, for example, 1200 angstroms. The pad nitride layer 102 may protect the substrate 100 from damage during etching. The size range of the pad nitride layer 102 is determined by comprehensively considering the overall structure of the device, the difficulty of the process, the etching blocking effect, and the like. If the pad nitride layer 102 is too thick, not only a long process time is required during the formation process, but also a long time is required for the subsequent removal, but if it is too thin, it does not function well to protect the substrate 100 during the etching process, and a well-defined trench isolation structure cannot be formed.
Referring to fig. 1, fig. 2 and fig. 3, in one embodiment of the present invention, in step S13, a patterned photoresist layer is first formed on the pad nitride layer 102, and then the substrate 100 is etched to form the null alignment mark 103 using the patterned photoresist layer as a mask. In the present embodiment, the depth of the null alignment mark 103 is, for example, 6000 angstroms to 8000 angstroms, specifically 7000 angstroms. Wherein the depth of the null alignment mark 103 is the depth from the surface of the substrate 100 to the bottom of the null alignment mark 103. The zero alignment mark 103 is disposed on the substrate 100 and located on the scribe line. As shown in fig. 14, in the present embodiment, the scribe lines are located at two sides of the second-type doped region 1062, for example. In other embodiments, the cutting streets may be located in other locations. When depositing a plurality of semiconductor layers on the substrate 100, the zero alignment mark 103 is used as a reference point for alignment with the shallow trench isolation process after epitaxial deposition. Specifically, a photoresist layer (not shown) may be formed on the pad nitride layer 102, and a patterned photoresist layer may be formed by a process such as exposure to light and development, where the position of the null alignment mark 103 is exposed. And then, taking the patterned photoresist layer as a mask, and quantitatively removing the pad nitride layer 102, the pad oxide layer 101 and part of the substrate 100 which are positioned below the patterned photoresist layer by using etching modes such as dry etching, wet etching or combination of the dry etching and the wet etching to obtain a zero alignment mark 103. In the present embodiment, the null alignment mark 103 is formed by, for example, dry etching, and the etching gas is, for example, chlorine (Cl) 2 ) Trifluoromethane (CHF) 3 ) Difluoromethane (CH) 2 F 2 ) Nitrogen trifluoride (NF) 3 ) And hexafluoro-fluorinationSulfur (SF) 6 ) Hydrogen bromide (HBr) or oxygen (O) 2 ) And the like, and combinations of one or more of them.
Referring to fig. 1, 3 and 4, in one embodiment of the present invention, the method for removing the pad nitride layer 102 is not limited by the invention when the step S14 is executed. In some embodiments, the pad nitride layer 102 may be removed using a dry etch, for example, CF may be used 4 And CHF 3 The pad nitride layer 102 is quantitatively removed by a one-step etching process. In other embodiments, the pad nitride layer 102 may be removed by a wet etch. Specifically, the pad nitride layer 102 is etched, for example, by hot phosphoric acid. The temperature of the hot phosphoric acid is, for example, 40 ℃ to 200 ℃, specifically, for example, 180 ℃. The concentration of hot phosphoric acid ranges, for example, from 80% to 90%, specifically, for example, 85%.
Referring to fig. 1 to 4, in one embodiment of the present invention, after the pad nitride layer 102 is removed, step S15 is performed to form a patterned photoresist layer on the pad oxide layer, and step S16 is performed to implant ions into the substrate using the patterned photoresist layer as a mask to form doped regions. The patterned photoresist layer covers the null alignment mark 103 and a portion of the pad oxide layer 101, and exposes an area to be implanted with ions. In this application, the region to be implanted with ions may be all regions of the substrate 100 to be implanted with ions. And the processes of forming the patterned photoresist layer and implanting ions into the substrate 100 may be performed several times due to the different types of ions to be implanted into the substrate 100. When the types of ions to be implanted are different, multiple times of implantation are required, and a different patterned photoresist layer needs to be formed during each implantation to block regions where the types of ions are not required to be implanted. That is, when it is desired to form an N-type doped region on the substrate 100, the patterned photoresist layer covers the null alignment mark 103 and the pad oxide layer 101 on the non-N-type doped region. When it is desired to form a P-type doped region on the substrate 100, the patterned photoresist layer covers the null alignment mark 103 and the pad oxide layer 101 on the non-P-type doped region. And after each doped region is formed, forming an isolation layer on each doped region, and carrying out high-temperature annealing on the doped regions under the protection of the isolation layer.
Referring to fig. 5 and 14, in an embodiment of the invention, the doped regions include a first-type doped region 1061 and a second-type doped region 1062. Specifically, the forming of the doped region includes step S151, forming a first photoresist layer in the null alignment mark and on the pad oxide layer. S161, using the first photoresist layer as a mask, and implanting first type ions into the substrate to form a first type doped region. S171, forming a first isolation layer on the pad oxide layer. And S181, carrying out high-temperature annealing on the first type doped region. S152, forming a second photoresist layer in the null position alignment mark and on the pad oxide layer. And S162, implanting second type ions into the substrate by taking the second photoresist layer as a mask to form a second type doping area. And S172, forming a first isolation layer on the pad oxide layer. And S182, carrying out high-temperature annealing on the second type doping region.
Referring to fig. 5 and 6, in an embodiment of the present invention, first, step S151 is executed to coat a photoresist layer on the pad oxide layer 101 and in the null alignment mark 103. After the exposure, the photoresist on the first type doping region 1061 to be ion-implanted is removed by an alkaline solution wet process or a dry ashing process (ashing), so as to form a first opening 1051, and the coated photoresist is patterned to form a first photoresist layer 1041. As shown in fig. 6, the first opening 1051 in the first photoresist layer 1041 exposes a first type doped region 1061 to be implanted with a first type of ions.
Referring to fig. 5to 7, in an embodiment of the invention, after the first photoresist layer 1041 is formed, step S161 is performed to implant ions into the substrate 100 by using the first photoresist layer 1041 as a mask, so as to form a first-type doped region 1061. In an embodiment of the invention, the first-type doped region 1061 is, for example, an N-type doped region. When the first type doped region 1061 is an N-type doped region, ions having five valence electrons may be implanted into the substrate 100 at the bottom of the first opening 1051 by using the first photoresist layer 1041 as a mask. For example, antimony ions, phosphorus ions or arsenic ions. When antimony ions replace silicon atoms, a negatively charged electron is provided to the valence band of the crystal, thereby forming an N-type doped region, i.e., the first type doped region 1061, on the substrate 100. In the present application, the dosage of each ion implantation is not limited for each position where the first type doped region 1061 needs to be formed, and the requirements of each semiconductor device can be satisfied. And is the mass and shape of the first-type doped region 1061, ions may be implanted multiple times, and the angle of ion implantation may be adjusted each time ions are implanted.
Referring to fig. 5 and 8, in an embodiment of the invention, after forming the first-type doped region 1061 on the substrate 100, step S171 is performed to form a first isolation layer 1071 on the pad oxide layer 101. In the present embodiment, the first isolation layer 1071 is, for example, an oxide layer, and is, for example, a silicon oxide layer. The first isolation layer 1071 has a thickness of 1000 to 4000 angstroms, for example, 2000 angstroms. The thicker first isolation layer 1071 prevents ions in the first type doped region 1061 from diffusing out of the surface of the substrate 100 during high temperature annealing, thereby affecting the quality of the semiconductor device. After the first isolation layer 1071 is formed, a step S181 of annealing the first type doped region 1061 at a high temperature is performed under the protection of the first isolation layer 1071.
Referring to fig. 5to 9, in an embodiment of the invention, after steps S151 to S181 are performed, the first isolation layer 1071 on the pad oxide layer is removed, and steps S152 to S182 are performed. Referring to fig. 9 and 10, in an embodiment of the invention, step S152 is first performed to coat a photoresist layer on the pad oxide layer 101 and in the null alignment mark 103. After the exposure, the photoresist above the second type doping region 1062 to be ion-implanted is removed by using an alkaline solution wet method or using a dry ashing process (ashing), so as to form a second opening 1052, and the coated photoresist is patterned, so as to form a second photoresist layer 1042. As shown in fig. 9 and 10, the second opening 1052 in the second photoresist layer 1042 exposes a second type doped region 1062 to be implanted with the second type ions.
Referring to fig. 5 and 11, in an embodiment of the invention, after forming the second photoresist layer 1042, step S162 is performed to implant ions into the substrate 100 by using the second photoresist layer 1042 as a mask to form a second-type doped region 1062. In an embodiment of the invention, the second-type doped region 1062 is, for example, a P-type doped region. When the second type doped region 1062 is a P type doped region, ions with three valence electrons, such as boron ions, are implanted into the substrate 100 at the bottom of the second opening 1052 by using the second photoresist layer 1042 as a mask. When the boron ions replace silicon atoms, a positively charged hole is provided to the valence band of the crystal, thereby forming a P-type doped region on the substrate 100. In the present application, the dosage of each ion implantation is not limited for each position where the second-type doped region 1062 needs to be formed, and thus the requirements of each semiconductor device can be met. And the mass and shape of the second type doping region 1062, ions can be implanted multiple times, and the angle of ion implantation can be adjusted each time ions are implanted.
Referring to fig. 5 and 12, in an embodiment of the invention, after forming the second-type doped region 1062 on the substrate 100, step S172 is performed to form a second isolation layer 1072 on the pad oxide layer 101. In the present embodiment, the second isolation layer 1072 is, for example, an oxide layer, and is, for example, a silicon oxide layer. The second isolation layer 1072 has a thickness of 1000 to 4000 angstroms, for example, 2000 angstroms. The thicker second isolation layer 1072 prevents the ions in the second-type doped region 1062 from diffusing out of the surface of the substrate 100 during high temperature annealing, thereby affecting the quality of the semiconductor device. After the second isolation layer 1072 is formed, a step S182 of annealing the second-type doped region 1062 at a high temperature is performed under the protection of the second isolation layer 1072.
Referring to fig. 8 and 12, in one embodiment of the present invention, the isolation layer (including the first isolation layer 1071 and the second isolation layer 1072) is an oxide layer and is formed by decomposition using Tetraethylorthosilicate (TEOS). After the substrate 100 is implanted with ions to form doped regions (including the first-type doped region 1061 and the second-type doped region 1062), since the doped regions have a larger amount of ions, the silicon inside the doped regions is in an amorphous state, and in an environment rich in oxygen, the amorphous silicon in the doped regions is prone to an oxygen reaction to form a silicon oxide layer. The silicon layer in the doped region is consumed, and a plurality of protrusions or depressions are formed on the surface of the substrate 100. In the present invention, the isolation layer is formed by decomposing tetraethyl orthosilicate (TEOS), which can prevent the consumption of amorphous silicon in the substrate 100, and further prevent the height difference between the doped region and the undoped region, so that the surface of the substrate 100 is a flat surface. And further, the phenomenon that the deposition of other epitaxial layers is influenced by the height difference formed in the subsequent zero alignment mark forming and depositing processes is avoided, and the quality of the semiconductor device is improved.
Referring to fig. 8 and 12, in one embodiment of the invention, the isolation layer may be formed by depositing Tetraethylorthosilicate (TEOS) by Low Pressure Chemical Vapor Deposition (LPCVD), for example. Specifically, the substrate 100 with the pad oxide layer 101 may be placed in a reaction chamber. The temperature in the reaction chamber is set to, for example, 650 ℃ to 680 ℃, specifically, 670 ℃, for example. The pressure in the reaction chamber is set to, for example, 0.55Torr to 0.65Torr, specifically, for example, 0.6 Torr. Under the condition, gaseous Tetraethoxysilane (TEOS) and nitrogen (N) are introduced into the reaction cavity 2 ) And oxygen (O) 2 ). Wherein, Tetraethoxysilane (TEOS) reacts with oxygen to generate silicon dioxide, and the silicon dioxide is deposited on the surface of the pad oxide layer 101 to form an isolation layer. The nitrogen is used as a carrier of the tetraethoxysilane, so that the tetraethoxysilane enters the reaction cavity. The flow rate of the tetraethoxysilane is, for example, 100sccm to 800sccm, specifically, 380 sccm. The oxygen flow rate is, for example, 1520sccm, and the ratio of the gas flow rate of oxygen to the gas flow rate of tetraethoxysilane is, for example, 4. By the LPCVD process, the isolation layer generated by the reaction of the tetraethoxysilane and the oxygen has high quality and good shape retention.
Referring to fig. 8 and 12, in another embodiment of the present invention, the isolation layer may be formed by depositing ethyl silicate by Chemical Vapor Deposition (CVD), for example. Specifically, the substrate 100 with the pad oxide layer 101 may be placed in a reaction chamber. The temperature in the reaction chamber is set to, for example, 300 to 500 ℃, specifically, for example, 400 ℃, and the pressure in the reaction chamber is set to normal atmospheric pressure. Under the condition, gaseous Tetraethoxysilane (TEOS) and nitrogen (N) are introduced into the reaction cavity 2 ) And ozone (O) 3 ) Wherein, the tetraethoxysilane reacts with the ozone to generate silicon dioxide, and the silicon dioxide is deposited on the surface of the pad oxide layer 101 to form an isolation layer. The nitrogen is used as a carrier of the tetraethoxysilane, so that the tetraethoxysilane enters the reaction cavity. Ozone and ortho silicic acidThe ethyl ester ratio is, for example, 4 to 5, the flow rate of tetraethoxysilane is, for example, 20 to 110sccm, and the flow rate of ozone is, for example, 160 sccm. The isolation layer with better performance is generated by the reaction of tetraethoxysilane and oxygen through a CVD process.
Referring to fig. 8 and 12, in yet another embodiment of the present invention, the isolation layer may be formed using plasma enhanced tetraethylorthosilicate (PE-TEOS), for example. Firstly, gasifying tetraethoxysilane, and then introducing oxygen and gasified tetraethoxysilane into a reaction cavity to enable tetraethoxysilane and oxygen to react to generate an isolation layer. The gas flow of the oxygen in the reaction chamber is 2000 sccm-4500 sccm, and the liquid flow of the ethyl orthosilicate is 500 mgm-1500 mgm. And the ratio of the gas flow of the oxygen to the liquid flow of the tetraethoxysilane ranges from 3.9 to 4.1. So that the tetraethoxysilane gas and the oxygen are fully reacted to completely consume C in the tetraethoxysilane 2 H 5 Ions are made to be discharged in the form of by-products, and C remaining on the surface of the silica film is avoided 2 H 5 The ions generate carbon-silicon compounds in the subsequent high-temperature process, so that the performance of silicon dioxide is influenced, and waste caused by excessive oxygen can be avoided. In this embodiment, the oxygen and the tetraethoxysilane may be dissociated by radio frequency. In this embodiment, the temperature of the reaction chamber is set to 380 ℃ to 420 ℃, for example, and specifically 400 ℃ for example. The pressure in the reaction chamber is set to, for example, 7to 8.5Torr, specifically, 7.5 Torr.
Referring to fig. 8 and 12, in an embodiment of the invention, after the isolation layer is formed, a high temperature annealing process is performed on the doped region, so that the ions implanted into the doped region are diffused to a desired region, and a doped region with a good appearance and quality is formed, and the ions in the doped region are uniformly distributed. In this embodiment, the temperature during the high temperature annealing is, for example, 1000 ℃ to 1250 ℃, specifically, for example, 1250 ℃. The high-temperature annealing time is, for example, 80min to 200min, specifically, 100 min. A longer ultra-high temperature anneal may repair damage to the surface of the substrate 100 during ion implantation. After ion implantation of all doped regions and high temperature annealing, the pad oxide layer 101 and spacers on the surface of the substrate 100 can be removed as shown in fig. 12 to 13Delamination, particularly by dry etching, e.g. using CF 4 And CHF 3 The pad oxide layer 101 and the isolation layer are removed by a single etching process. In other embodiments, the pad oxide layer 101 may be removed by wet etching, for example, hydrofluoric acid with a concentration of 1% to 10% may be used to etch the pad oxide layer 101 and the isolation layer.
Referring to fig. 1 and 14, in an embodiment of the invention, after the high temperature annealing is completed, step S19 may be performed to form the epitaxial layer 108 on the substrate 100, and the epitaxial layer 108 covers the null alignment mark 103. In the present embodiment, the epitaxial layer 108 may be any desired epitaxial layer, such as an aluminum nitride buffer layer, a gallium nitride epitaxial layer, a silicon epitaxial layer, and the like. The epitaxial layer 108 may also be composed of multiple epitaxial layers of different materials.
In summary, in the manufacturing method of the semiconductor structure provided by the present invention, after the pad oxide layer and the pad nitride layer are formed on the substrate, the plurality of null alignment marks are formed on the substrate. And then removing the pad nitride layer, forming a patterned photoresist layer on the substrate, and performing ion implantation on the substrate by using the patterned photoresist layer as a mask to form a doped region. And forming an isolation layer on the pad oxide layer in a deposition mode, and carrying out high-temperature annealing on the doping region under the protection of the isolation layer to uniformly diffuse ions in the doping region to a required region. And finally, after the isolation layer and the pad oxide layer are removed, an epitaxial layer is formed on the substrate and covers the zero alignment mark. The manufacturing method of the semiconductor structure provided by the embodiment enables the substrate and the epitaxial layer to have flat connection surfaces, provides a good-quality substrate with the epitaxial layer, and further can improve the quality of a semiconductor integrated device.
Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (7)
1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
forming a plurality of zero position alignment marks on the substrate, wherein the zero position alignment marks are positioned on the cutting path;
forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer covers the zero alignment mark and part of the substrate;
implanting ions into the substrate by taking the patterned photoresist layer as a mask to form a doped region;
depositing an isolation layer on the substrate, wherein the isolation layer covers the doped region;
carrying out high-temperature annealing on the doped region; and
after the high-temperature annealing is carried out on the doped region, the isolation layer is removed, an epitaxial layer is formed on the substrate, and the epitaxial layer covers the zero alignment mark;
the method for depositing the isolation layer on the substrate comprises the following steps: the method comprises the step of decomposing tetraethoxysilane to form an isolation layer, wherein the thickness of the isolation layer is 1000-4000 angstroms.
2. The method of claim 1, further comprising: and forming a pad oxide layer on the substrate, wherein the thickness of the pad oxide layer is 80-500 angstroms.
3. The method of claim 2, wherein the step of forming the isolation layer comprises:
placing the substrate with the pad oxide layer in a reaction chamber;
presetting the temperature and pressure of the reaction chamber; and
and introducing tetraethoxysilane and oxygen-containing gas into the reaction cavity, wherein the tetraethoxysilane and the oxygen-containing gas react to generate silicon dioxide and the silicon dioxide is deposited on the surface of the pad oxide layer.
4. The method of claim 3, wherein the oxygen-containing gas is oxygen or ozone.
5. The method as claimed in claim 3, wherein nitrogen is introduced into the reaction chamber while introducing tetraethoxysilane and oxygen-containing gas into the reaction chamber.
6. The method of claim 2, wherein the doped regions comprise a first type doped region and a second type doped region, and the method comprises:
forming a first photoresist layer on the zero alignment mark and a part of the pad oxide layer;
implanting first type ions into the substrate by taking the first photoresist layer as a mask to form a first type doping area;
forming a first isolation layer on the pad oxide layer, and performing high-temperature annealing on the first type doped region;
forming a second photoresist layer on the zero alignment mark and a part of the pad oxide layer;
implanting second type ions into the substrate by taking the second photoresist layer as a mask to form a second type doped region; and
and forming a second isolation layer on the pad oxide layer, and carrying out high-temperature annealing on the second type doping region.
7. The method of claim 1, wherein the high temperature annealing is performed at a temperature of 1000 ℃ to 1250 ℃ for 80min to 200 min.
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