CN114639599A - Local service life control method for semiconductor device - Google Patents
Local service life control method for semiconductor device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
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- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
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- 229910001385 heavy metal Inorganic materials 0.000 description 5
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- 238000002513 implantation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
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- 239000000377 silicon dioxide Substances 0.000 description 2
- -1 Pt or Au Chemical class 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2258—Diffusion into or out of AIIIBV compounds
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Abstract
The invention discloses a method for controlling the local service life of a semiconductor device, wherein the semiconductor device at least comprises a group of two different conductive types, and at least two materials are added into the semiconductor device, wherein the minority carrier lifetime of the first material is longer than that of the second material; local lifetime control is achieved using the second material having a relatively short minority carrier lifetime; the second material is completely doped or contains at least a portion of the second conductivity type. The method realizes local service life control, can reduce the number of carriers stored in the diode in reverse recovery, reduces the maximum reverse recovery current in the reverse recovery process, and improves the speed of reverse recovery.
Description
Technical Field
The invention relates to a method for controlling the service life of minority carriers of a semiconductor device, in particular to a method for controlling the local service life of the semiconductor device.
Background
In the last decades, controlling the spatial distribution of recombination centers parallel to the axial direction of two different conductivity types (PN junctions) has become a very attractive new technique for improving the performance of the device trade-off, which can result in shorter turn-off times, smaller reverse overshoot currents and greater softness than the classical lifetime control techniques, which optimizes the device performance, i.e. achieves a better performance trade-off. For the traditional service life control technology, deep-level metal impurities have high diffusion coefficients, and electron irradiation generates uniformly distributed composite centers, so that the composite centers cannot be distributed in narrow local areas. The controllable local lifetime provides a new design parameter and a larger design freedom for optimizing the performance compromise of the device, and compared with the traditional lifetime control technology which introduces a recombination center in a large range in the whole device, the new lifetime control technology is called local lifetime control technology.
Lifetime control techniques, which are widely used in bipolar power devices to accelerate the extraction of excess electrons and holes, have been used to achieve higher switching speeds. The following common life control technologies are currently available:
1. heavy metal ions, such as Pt or Au, are doped to form some deep energy levels in the forbidden band of the power device (mainly silicon), thereby accelerating the recombination of electrons and holes and thus reducing minority carrier lifetime. The deep level of Au formation is closer to the center of the forbidden band, so that its leakage is larger. The working junction temperature of the device is difficult to exceed 150 ℃;
in the following, Pt is taken as an example to describe a common method for realizing lifetime control:
a. firstly, growing ILD (after a dielectric layer) on the front surface of the device, sputtering a layer of Pt metal on the back surface of the device, and forming Pt Silicide (metal Silicide) at high temperature, wherein the typical process condition is 550 ℃ for 30 minutes.
b. And (4) wet etching, and removing Pt which does not completely form the Silicide.
c. And (4) performing a high-temperature thermal process to push knots. Typical conditions are 950 ℃, 30 minutes;
since the diffusion rate of Pt in Silicon is fast, 950 ℃, Pt can be completely diffused into Silicon in 30 minutes of thermal process. Therefore, the service life control realized by adopting a mode of doping heavy metal ions is also called global service life control.
The disadvantage of using heavy metal ions to achieve lifetime control is that heavy metal ions can cause pollution to the production line. After the device is doped with heavy metal ions, the subsequent process flow needs to be independently controlled by a machine table, so that the pollution is prevented. This adds significantly to the difficulty.
2. High energy ion implantation accelerates the recombination of electrons and holes by ions striking the wafer to form some defect levels.
The defect levels formed by ion implantation require a low temperature anneal, typically around 300 c for about 1 hour, to repair some of the unstable defect levels. However, higher temperature thermal processes, such as above 400 ℃, repair all defects that are formed and thus do not have any life control implications. The ion implantation is usually performed after the front side process is completed. The defect levels formed by ion implantation depend on where the ion implantation can reach.
The current common modes are electron irradiation, He injection and the like. Electrons are light and can easily penetrate through a wafer, so that the lifetime control formed by electron irradiation is generally global lifetime control, the defect energy level formed by electron irradiation is closer to the center of a forbidden band, and thus the leakage of the device, particularly the high-temperature leakage, is large, and the device is difficult to work under the condition that the junction temperature exceeds 150 ℃.
He is injected, because He is heavier, the highest energy of a common ion injection machine can only reach 1.5MeV, and the depth of the injection can be 5-6 um. However, after the front metal is manufactured on the device, the thickness of the front metal is usually 4-5 um, and the He is difficult to enter the surface of the silicon wafer after the thickness of the dielectric layer of 1um is added. Unless there is a higher energy ion implanter, for example, the highest energy may be up to 3MeV, or even 6 MeV; but the machine is more expensive and brings great difficulty to the production. The lifetime control of He implantation is a technique of local lifetime control.
Disclosure of Invention
The invention aims to provide a local service life control method of a semiconductor device, which can improve the performance and application environment of the semiconductor device through local service life control technology quickly at low cost.
To achieve the above technical object, the present invention provides a method for controlling local lifetime of a semiconductor device, the semiconductor device at least comprises a set of two different conductivity types, wherein: incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material; using said second material having a relatively short minority carrier lifetime to achieve localized lifetime control; the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type; the second material uses silicon germanium SiGe, polycrystalline silicon containing grains or a direct band gap semiconductor, which is gallium arsenide GaAs or indium phosphide InP, to reduce minority carrier lifetime.
In the present invention, the semiconductor device comprises at least two materials, one of which has a long minority carrier lifetime and the other of which has a short minority carrier lifetime. Minority carrier lifetime is short to realize local lifetime control. The device comprises at least one set of two different conductivity types (PN junctions). The material with a short minority carrier lifetime is completely doped or at least comprises a part of the second conductivity type. The scheme of the invention is a technology for controlling the local service life, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the reverse recovery speed. Meanwhile, because the technology of local area lifetime control is adopted, the softness factor in the reverse recovery process is not substantially deteriorated.
As a further improvement, additional buffer layers are added between the different materials.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned at the upper part, wherein a control layer made of the second material is arranged between the epitaxial layer and the second conductive type region.
As a further improvement, a second conductivity type doping is introduced during the growth of the second material, or formed by ion implantation after the production of the second material, the second conductivity type doping forming two different conductivity types at the bottom of the control layer or at the upper part of the epitaxial layer.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and used for forming a drift region of the first conductive type, and a second conductive type region positioned on the upper portion, wherein a control layer made of the second material is arranged on the upper portion of the second conductive type region.
As a further improvement, the semiconductor device is an insulated gate bipolar transistor IGBT, which includes: the transistor comprises a back second conductive type region, a back first conductive type region, a first conductive type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, wherein a control layer made of the second material is arranged on the outer side of the back second conductive type region.
As a further improvement, the semiconductor device is a metal oxide semiconductor field effect transistor MOSFET used in a bridge circuit and realizing soft switching, which includes: the MOSFET comprises a heavily doped first conduction type substrate, a first conduction type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conduction type region and a heavily doped second conduction type region, wherein the first conduction type drift region and the grid oxide layer are arranged on the substrate, the heavily doped first conduction type region and the heavily doped second conduction type region are arranged above the channel, the heavily doped second conduction type region is connected with the channel, the heavily doped first conduction type region and the heavily doped second conduction type region are connected with a source electrode through source electrode metal, the middle upper layer inside the channel is made of the second material, and the MOSFET is conducted by utilizing a parasitic body diode to realize zero-voltage switching.
As a further improvement, the method for disposing the second material comprises: the arrangement is introduced either on the whole silicon wafer or, for termination regions subjected to a higher breakdown voltage, only in the active region of the semiconductor device, by means of etching or selective production.
The control method is simple, convenient to produce and implement, suitable for various semiconductor devices and functional requirements, capable of improving the devices and the performance of the devices and capable of realizing the local service life control of the semiconductor devices at low cost.
Drawings
FIG. 1 is a diagram of a conventional fast recovery diode;
FIG. 2 is a schematic diagram of a first embodiment of a fast recovery diode according to the present invention;
FIG. 3 is a schematic diagram of a second embodiment of the fast recovery diode of the present invention;
FIG. 4 is a schematic diagram of a third embodiment of the fast recovery diode of the present invention;
FIG. 5 is a schematic diagram of an IGBT according to the present invention;
FIG. 6 is a diagram of a MOSFET in accordance with the present invention;
FIG. 7 is a schematic view of a production scheme of the present invention.
Reference numerals: the semiconductor device comprises a heavily doped first conductive type substrate 1, an epitaxial layer 2, a second conductive type region 3, a control layer 4, a back second conductive type region 11, a back first conductive type region 12, a first conductive type drift region 13, a gate oxide layer 14, a gate 15, a channel 16, a heavily doped first conductive type region 17, a heavily doped second conductive type region 18, a heavily doped first conductive type substrate 21 and an active region 22.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the field of semiconductor devices, the first conductivity type and the second conductivity type are opposite conductivity types, and may be the first conductivity type is an N type, and the second conductivity type is a P type; the first conductivity type may be P-type, and the second conductivity type may be N-type. The present invention is understood to mean that the first conductivity type is N-type and the second conductivity type is P-type.
As shown in fig. 1 to 7, the present invention provides a method for controlling local lifetime of a semiconductor device, wherein the semiconductor device at least comprises a set of two different conductivity types (PN junctions), wherein: incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material; using said second material having a relatively short minority carrier lifetime to achieve localized lifetime control; the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type; the second material uses silicon germanium SiGe, polycrystalline silicon containing grains or a direct band gap semiconductor, which is gallium arsenide GaAs or indium phosphide InP, to reduce minority carrier lifetime.
In the present invention, the semiconductor device includes at least two materials, one of which has a long minority carrier lifetime and the other of which has a short minority carrier lifetime. The minority carrier lifetime of the first material is standard and common semiconductor device material, and the control method provided by the invention is to introduce the minority carrier lifetime with short lifetime for realizing the local lifetime control. The device comprises at least one set of two different conductivity types (PN junctions). The material with a short minority carrier lifetime is completely doped or at least comprises a part of the second conductivity type. The scheme of the invention is a technology for controlling the local service life, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the reverse recovery speed. Meanwhile, because the technology of local lifetime control is adopted, the softness factor in the reverse recovery process is not basically deteriorated.
As a further improvement, additional buffer layers are added between the different materials.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and forming a first conductive type drift region, and a second conductive type region positioned at the upper part, wherein a control layer made of the second material is arranged between the epitaxial layer and the second conductive type region.
As a further improvement, a second conductivity type doping is introduced during the growth of the second material, or formed by ion implantation after the production of the second material, the second conductivity type doping forming two different conductivity types (PN junctions) at the bottom of the control layer or at the upper part of the epitaxial layer.
As a further improvement, the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate positioned at the bottom, an epitaxial layer positioned in the middle and used for forming a drift region of the first conductive type, and a second conductive type region positioned on the upper portion, wherein a control layer made of the second material is arranged on the upper portion of the second conductive type region.
As a further improvement, the semiconductor device is an insulated gate bipolar transistor IGBT, which includes: the transistor comprises a back second conductive type region, a back first conductive type region, a first conductive type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, wherein a control layer made of the second material is arranged on the outer side of the back second conductive type region.
As a further improvement, the semiconductor device is a MOSFET for use in a bridge circuit and implementing soft switching, comprising: the MOSFET comprises a heavily doped first conduction type substrate, a first conduction type drift region, a grid oxide layer, a grid, a channel, a heavily doped first conduction type region and a heavily doped second conduction type region, wherein the first conduction type drift region and the grid oxide layer are arranged on the substrate, the heavily doped first conduction type region and the heavily doped second conduction type region are arranged above the channel, the heavily doped second conduction type region is connected with the channel, the heavily doped first conduction type region and the heavily doped second conduction type region are connected with a source electrode through source electrode metal, the middle upper layer inside the channel is made of the second material, and the MOSFET is conducted by utilizing a parasitic body diode to realize zero-voltage switching.
As a further improvement, the method of disposing the second material comprises: the arrangement is introduced either on the whole silicon wafer or, for termination regions subjected to a higher breakdown voltage, only in the active region of the semiconductor device, by means of etching or selective production.
Fig. 1 is a simplest fast recovery reverse diode, the substrate being a heavily doped first conductivity type substrate 1, the doping concentration being high in order to form a good ohmic contact. An epitaxial layer 2 on top of the substrate to form a drift region of the first conductivity type, the thickness and doping concentration of the drift region being dependent on the breakdown voltage of the device. However, in order to improve the reverse recovery softness of the fast recovery diode, a graded region may be provided between the heavily doped first conductivity type substrate 1 and the epitaxial layer 2, and the doping concentration may gradually transition from a high concentration to a low concentration, or a Buffer region may be added. The second conductive type region 3 is formed by ion implantation, and in order to reduce the number of carriers stored in the diode during the reverse recovery process, the doping concentration of the second conductive type region 3 is usually relatively low, and the common doping concentration is 5e 12-5 e13/cm2In the meantime. The lower the doping concentration, the higher the on-state voltage drop of the device and the lower the number of carriers stored by reverse recovery, which is a trade-off relationship. However, too low a doping concentration may result in the ohmic contact of the second conductivity type region being affected and, in addition, may reduce the surge current capability of the device. This is all a matter of special attention in the design.
To further speed up the reverse recovery capability of the diode, the patent proposes the following local lifetime control technique. And additionally introducing a control layer 4 made of the second material on the heavily doped first conductive type substrate 1 and the epitaxial layer 2, wherein the control layer 4 is an additional material different from the heavily doped first conductive type substrate 1 and the epitaxial layer 2, and the material is characterized by lower minority carrier lifetime.
Some materials that can be selected, such as SiGe, have an order of magnitude lower minority carrier lifetime than Si because of the addition of Ge to silicon; in SiGe, if the Ge content exceeds 15%, the lattice deformation is severe, and therefore, in practical applications, it is usually less than 15%. Or polysilicon, which has a reduced minority carrier lifetime due to the introduction of some Grain. Silicon is an indirect bandgap semiconductor, and direct recombination of electrons and holes is difficult, so that minority carrier lifetime is long. If a layer of direct band gap semiconductor, such as GaAs and InP, is introduced, minority carrier lifetime can be greatly reduced. There may be some mismatch in the crystal lattice of different semiconductor materials, and an additional buffer layer may be required at this time. The minority carrier lifetime of the second material incorporated in the present invention is less than the minority carrier lifetime of the first material and can be 1/2, 1/3 or even 1/100 and 1/1000 of the minority carrier lifetime of the first material. A preferred embodiment is 1/10 where the first material has a minority carrier lifetime.
The material of the control layer 4 needs to be doped with a second conductivity type. The second conductivity type doping can be introduced during material growth, such as SiGe growth, and can be achieved. Or may be formed by ion implantation after the material is produced.
The location of the two different conductivity types (PN junctions) formed is shown in dashed lines in fig. 2. Because the place of the junction is usually the place where the electric field strength is strongest. The place where the electric field strength is strongest is inside the control layer 4, which may increase the leakage of the device, and a more preferred scheme is shown by the dotted line in fig. 3, where the junction is located below the control layer 4.
As another embodiment, as shown in fig. 4, the control layer 4 may be introduced after the heavily doped first conductive type substrate 1, the epitaxial layer 2, and the second conductive type region 3 of the device are formed, and the control layer 4 is then extended.
The invention is also applicable to bipolar power devices in which the device requires injection of electrons and holes to increase the concentration of carriers in the drift region, thereby reducing the on-resistance and achieving a low on-voltage drop. However, when the device is subjected to withstand voltage, the excess electrons and holes in the device need to be pumped away. The patent proposes a new local lifetime control mode to accelerate the extraction of carriers, thereby increasing the switching speed of the device. The patent is also applicable to unipolar devices, typically unipolar devices such as MOSFETs, having a parasitic body diode. When MOSFETs are used in bridge circuits, to achieve soft switching, ZVS is achieved by utilizing the parasitic body diode conduction, which also reduces the minority carrier lifetime to speed up the reverse recovery of the MOSFET parasitic body diode.
The invention provides a technical application embodiment of an Insulated Gate Bipolar Transistor (IGBT), as shown in fig. 5, the structure of a common Trench Based FS IGBT comprises: the rear second conductivity type region 11, the Collector, and the rear first conductivity type region 12 are used to form a field stop. The doping concentration and the thickness of the first conductivity type drift region 13 determine the breakdown voltage of the device. The gate oxide 14 and the gate 15 form a trench gate, wherein the gate oxide 14 is typically silicon dioxide and the gate 15 is polysilicon, which is used to form the gate. Further comprising: a channel 16, a heavily doped first conductivity type region 17, and a heavily doped second conductivity type region 18. The heavily doped second conductivity type region 18 is connected to the channel 16. The heavily doped first conductivity type region 17 and the heavily doped second conductivity type region 18 are together connected to the source via a source metal. In order to reduce the turn-off loss of the IGBT, it is desirable to implant the back surface second conductivity type region 11 with as little second conductivity type as possible, reducing the implantation efficiency thereof. The method is to reduce the doping dose of the second conductive type, such as the implantation dose is usually 5e 12-5 e13/cm2And reducing the energy injected from the second conductive type region to accelerate the recombination of electrons. And local lifetime control can be performed in the second conductivity type region on the back surface. According to the above concept, the second material is added to the rear second conductivity type region 11, and the minority carrier lifetime of the second material is reduced. Thus, the injection of holes can be reduced, thereby reducing the turn-off loss of the IGBT.
The invention also provides the technical application embodiment of the metal-oxide-semiconductor field effect transistor MOSFET, in particular to a MOSFET structure which is used in a bridge circuit and realizes soft switching. As shown in fig. 6, the transistor comprises a heavily doped first conductive type substrate, a first conductive type drift region, a gate oxide layer and a gate electrode on the substrate form a trench gate, the gate oxide layer is made of silicon dioxide, the gate electrode is made of polysilicon, a channel, a heavily doped first conductive type region and a heavily doped second conductive type region, the heavily doped second conductive type region is connected with the channel, and the heavily doped first conductive type region and the heavily doped second conductive type region are connected with a source electrode through a source electrode metal.
Although a MOSFET is a multi-sub device, its parasitic body diode needs to be turned on to realize ZVS, which also requires a local lifetime control technique. A new material may be introduced to reduce the lifetime control technique. The dotted line shown in fig. 6, i.e., the inner, middle and upper layer, is made of the second material, which is composed of the new material. The new material has short minority carrier lifetime and can help the recombination of electrons and holes, thereby improving the speed of reverse recovery.
In the prior art, the introduction of materials is introduced on the whole silicon wafer. However, the terminal region is required to bear a relatively high breakdown voltage, and the invention is also improved by the corresponding technology. As shown in fig. 7, we can introduce new materials only in the active region 22 of the device by etching or selective manufacturing scheme. There are also some applications, such as RC-IGBTs, where IGBTs and diodes are integrated. It is also possible that the new material is only used in the diode part and the IGBT part is not introduced with this new material.
The scheme of the invention is a technology for controlling the local service life, which can reduce the number of carriers stored in a diode in reverse recovery, reduce the maximum reverse recovery current in the reverse recovery process and improve the speed of the reverse recovery. Meanwhile, because the technology of local lifetime control is adopted, the softness factor in the reverse recovery process is not basically deteriorated. The control method is simple, convenient to produce and implement, suitable for various semiconductor devices and functional requirements, capable of improving the devices and the performance of the devices and capable of achieving local service life control of the semiconductor devices at low cost. The local lifetime control technique introduced in the patent can be used in cooperation with other lifetime control techniques, such as Au/Pt doping, resistance irradiation, He injection and the like, so that a better effect is achieved.
It is to be understood that the scope of the present invention is not to be limited to the non-limiting embodiments, which are illustrated as examples only. The essential protection sought herein is further defined in the scope provided by the independent claims, as well as in the claims dependent thereon.
Claims (8)
1. A method for controlling the local lifetime of a semiconductor device, said semiconductor device comprising at least one set of two different conductivity types, characterized by:
incorporating at least two materials into said semiconductor device, wherein the minority carrier lifetime of a first material is longer than the minority carrier lifetime of a second material, said minority carrier lifetime of said second material being 1/2 or less of the minority carrier lifetime of said first material;
using said second material having a relatively short minority carrier lifetime to achieve localized lifetime control;
the second material is completely doped with the second conductive type or at least comprises a part of the second conductive type;
the second material uses silicon germanium SiGe, polycrystalline silicon containing grains or a direct band gap semiconductor, which is gallium arsenide GaAs or indium phosphide InP, to reduce minority carrier lifetime.
2. The method as claimed in claim 1, wherein the step of controlling the local lifetime of the semiconductor device comprises the steps of: additional buffer layers are added between the different materials.
3. The method of claim 2, wherein: the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate (1) positioned at the bottom, an epitaxial layer (2) forming a drift region of the first conductive type positioned in the middle and a second conductive type region (3) positioned at the upper part, wherein a control layer (4) made of the second material is arranged between the epitaxial layer (2) and the second conductive type region (3).
4. A semiconductor device local lifetime controlling method according to claim 3, wherein: introducing a second conductivity type doping during the growth of the second material or forming a second conductivity type doping by ion implantation after the second material has been produced, the second conductivity type doping forming two different conductivity types at the bottom of the control layer (4) or at the upper part of the epitaxial layer (2).
5. The method of claim 2, wherein: the semiconductor device is a diode having: the transistor comprises a heavily doped first conductive type substrate (1) positioned at the bottom, an epitaxial layer (2) positioned in the middle and forming a drift region of the first conductive type, and a second conductive type region (3) positioned at the upper part, wherein a control layer (4) made of the second material is arranged at the upper part of the second conductive type region (3).
6. The method of claim 2, wherein: the semiconductor device is an Insulated Gate Bipolar Transistor (IGBT) and comprises: the structure comprises a back second conduction type region (11), a back first conduction type region (12), a first conduction type drift region (13), a grid oxide layer (14), a grid (15), a channel (16), a heavily doped first conduction type region (17) and a heavily doped second conduction type region (18), wherein a control layer (4) made of the second material is arranged on the outer side of the back second conduction type region (11).
7. The method of claim 2, wherein: the semiconductor device is a metal-oxide-semiconductor field effect transistor MOSFET used in a bridge circuit and realizing soft switching, and comprises: the MOS transistor comprises a heavily doped first conduction type substrate (21), a first conduction type drift region (13) on the substrate, a gate oxide layer (14), a gate (15), a channel (16), a heavily doped first conduction type region (17) and a heavily doped second conduction type region (18) which are positioned above the channel (16), wherein the heavily doped second conduction type region (18) is connected with the channel (16), the heavily doped first conduction type region (17) and the heavily doped second conduction type region (18) are connected with a source electrode through a source electrode metal together, an upper middle layer inside the channel (16) is made of the second material, and the MOS transistor is conducted by using a parasitic body diode and realizes zero-voltage switching.
8. The method of claim 2, wherein: the second material arrangement method comprises the following steps: the arrangement is introduced either over the entire silicon wafer or, for termination regions which are subjected to a higher breakdown voltage, only in the active region (22) of the semiconductor device by means of etching or selective production.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701162A (en) * | 2013-12-06 | 2015-06-10 | 江苏物联网研究发展中心 | Semiconductor device, PIN diode and IGBT manufacturing method |
| CN107516681A (en) * | 2016-06-15 | 2017-12-26 | 全球能源互联网研究院有限公司 | A kind of fast recovery diode and its manufacture method |
| CN107946360A (en) * | 2017-05-02 | 2018-04-20 | 中国电子科技集团公司第二十四研究所 | A kind of power MOSFET device and its manufacture method with carrier lifetime regulatory region |
| CN109216472A (en) * | 2018-08-28 | 2019-01-15 | 全球能源互联网研究院有限公司 | fast recovery diode and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104701162A (en) * | 2013-12-06 | 2015-06-10 | 江苏物联网研究发展中心 | Semiconductor device, PIN diode and IGBT manufacturing method |
| CN107516681A (en) * | 2016-06-15 | 2017-12-26 | 全球能源互联网研究院有限公司 | A kind of fast recovery diode and its manufacture method |
| CN107946360A (en) * | 2017-05-02 | 2018-04-20 | 中国电子科技集团公司第二十四研究所 | A kind of power MOSFET device and its manufacture method with carrier lifetime regulatory region |
| CN109216472A (en) * | 2018-08-28 | 2019-01-15 | 全球能源互联网研究院有限公司 | fast recovery diode and preparation method thereof |
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