CN109166916B - Insulated gate bipolar transistor and preparation method thereof - Google Patents
Insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
An insulated gate bipolar transistor and a preparation method thereof belong to the technical field of power semiconductors. According to the invention, on the basis of the traditional charge storage type IGBT device structure, a heterojunction structure is formed in the base region, so that a potential barrier for blocking minority carriers in the drift region from flowing into the base region is formed, the minority carrier concentration in the drift region close to one side of the emitter is greatly improved, the carrier distribution concentration in the drift region is improved, the conductance modulation effect of the IGBT is enhanced, the forward conduction voltage drop Vceon of the device is reduced, and the compromise characteristic between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the IGBT is optimized; the defect that the breakdown voltage is reduced when the Vceon is reduced in the traditional charge storage layer is overcome; and the working characteristics of the device can be further optimized by adjusting the combination of the semiconductor materials with different forbidden band widths for forming the heterojunction structure.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to an insulated gate bipolar transistor and a preparation method thereof.
Background
The IGBT is a device formed by compounding an MOSFET (input stage) and a PNP transistor (output stage), has the characteristics of easy driving, low input impedance and high switching speed of the MOSFET device, and has the advantages of large on-state current density, low on-state voltage, small loss and good stability of a bipolar device. Based on these excellent device characteristics, in recent years, IGBTs have become mainstream power devices widely used in medium-high voltage fields, such as high-speed rails, electric vehicles, motor drives, grid-connected technologies, energy storage power stations, AC/DA conversion, variable frequency speed control, and the like. The IGBT is adopted for power conversion, so that the power utilization efficiency and quality can be improved, the IGBT has the characteristics of high efficiency, energy conservation and environmental protection, and is a key support technology for solving the problem of energy shortage and reducing carbon emission, so that the IGBT is called as a CPU (central processing unit) of a power conversion product and a core of green economy.
The front side MOS structure of the IBGT includes a gate and an emitter region. The grid structure comprises a planar grid and a groove grid. The planar gate structure has good gate oxide layer quality, the gate capacitance is small, electric field concentration cannot be caused below the gate to affect voltage resistance, the planar gate structure can further reduce the gate capacitance through optimization and improvement, other working characteristics can be improved, such as gate storage time reduction, switching loss reduction, and gate voltage overshoot in a short circuit safety working area (SCSOA) test can be reduced. The trench gate structure changes the channel from the transverse direction to the longitudinal direction, and eliminates R in the on-resistanceJFETThe cell density can be increased at the same time, which is advantageous for reducing power consumption. The advanced enhancement technology in the industry at present improves the carrier injection efficiency close to one end of an emitting region by optimizing a front MOS structure, thereby optimizing the compromise relationship between the on-state voltage drop and the turn-off loss. A Carrier Stored Layer (CSL) is commonly used. Fig. 1 schematically shows an N-channel trench gate insulated gate bipolar transistor (csbt), and as can be seen from the figure, in the structure, an N-type charge storage layer 7 with higher doping concentration and a certain thickness is introduced below a P-type base region 5, the length of a channel is shortened by the N-type charge storage layer 7, and a hole barrier is introduced below the P-type base region 5, that is, a barrier for a hole carrier to flow to an IGBT emitter is increased, and as shown in fig. 2 and fig. 3, energy band distribution of the structure under zero bias and an additional 2V forward bias is shown. Therefore, the hole concentration of the device close to the emitter end is greatly improved, the carrier concentration distribution of the whole N-drift region 9 is improved, the conductivity modulation effect of the N-drift region 9 is enhanced, the IGBT obtains lower forward conduction voltage drop and better compromise relation between the forward conduction voltage drop and turn-off loss, and small turn-off time can be obtained under certain forward conduction voltage drop. However, as the doping concentration of the charge storage layer is increased, the conductivity modulation effect of the charge storage type IGBT is improved more, the forward conduction characteristic of the device is better, and at the same time, the charge storage layer is disadvantageous to the withstand voltage performance of the device, which isIt appears that as the doping concentration of the charge storage layer increases, the breakdown voltage of the device decreases significantly, which limits the doping concentration and thickness of the charge storage layer. Therefore, the influence of the doping concentration and thickness of the charge storage layer on the breakdown voltage of the device limits the optimized compromise among the breakdown voltage, the forward on-voltage drop and the turn-off loss of the charge storage type IGBT.
In order to effectively shield the adverse effect of the charge storage layer and further obtain a high breakdown voltage in the industry by combining the conventional csbt device structure shown in fig. 1, the following two methods are mainly adopted:
(1) increasing the depth of the trench gate, wherein the depth of the trench gate is generally larger than the junction depth of the N-type charge storage layer;
(2) the width of the unit cell is reduced, so that the channel density of the MOS structure is improved, and the distance between the groove gates is as small as possible.
The implementation of the method (1) can improve the withstand voltage through the deep trench structure, but at the same time, the gate capacitance is increased, which results in the reduction of the switching speed and the increase of the switching loss; in addition, the reliability of the device is reduced by the electric field concentration effect at the bottom of the trench. The implementation of the mode (2) will increase the gate capacitance of the device, resulting in the reduction of the switching speed and the increase of the switching loss of the device, and affecting the compromise characteristic of the conduction voltage drop and the switching loss of the device, and on the other hand, the large channel density will also increase the saturation current density of the device, and make the characteristic of the short-circuit safe operating area (SCSOA) of the device worse. In addition, the gate oxide layer in the trench gate structure is formed in the trench through one-time thermal oxidation, in order to guarantee a certain threshold voltage, the thickness of the whole gate oxide layer is required to be smaller, however, the size of the MOS capacitor is in inverse proportion to the thickness of the oxide layer, so that the thickness of the thin gate oxide layer in the traditional CSTBT device can obviously increase the gate capacitance of the device, and meanwhile, the problem of device breakdown voltage reduction caused by the electric field concentration effect at the bottom of the trench cannot be avoided, and the reliability of the device is poor.
Disclosure of Invention
Aiming at the adverse effect of the doping concentration and thickness of a charge storage layer on the breakdown voltage of a device in the prior art and limiting the defect of compromise among the breakdown voltage, the forward conduction voltage drop and the turn-off loss of the device, the invention provides the insulated gate bipolar transistor with the base region having the heterojunction structure. Meanwhile, doping with gradually changed concentration is formed in the base region where the heterojunction is formed, and a potential barrier is further formed through concentration gradient; meanwhile, the potential barrier can be further formed by changing the energy band width through the gradual change of the semiconductor material composition.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a kind of insulated gate bipolar transistor, its cellular structure includes: a collector metal 13, a second conductivity type semiconductor collector region 12, a first conductivity type semiconductor drift region 9, a second conductivity type semiconductor base region 5, a second conductivity type semiconductor emitter region 4, a first conductivity type semiconductor emitter region 3, a gate structure and an emitter metal 1; collector metal 13 is provided on the back surface of second conductivity type semiconductor collector region 12; the first conductivity type semiconductor drift region 9 is disposed on the front surface of the second conductivity type semiconductor collector region 12; the second conductive type semiconductor base region 5 is arranged on the top layer of the first conductive type semiconductor drift region 9; the second conductive type semiconductor emitter region 4 and the first conductive type semiconductor emitter region 3 which is contacted with two sides of the second conductive type semiconductor emitter region 4 are arranged on the top layer of the second conductive type semiconductor base region 5 side by side; the gate structure comprises a gate electrode 61 and a gate dielectric layer 62, wherein the gate electrode 61 is in contact with the first conductive type semiconductor emitter region 3 and the second conductive type semiconductor base region 5 through the gate dielectric layer 62; the emitter metal 1 is arranged on the uppermost surface of the device, is in contact with the upper surfaces of the second conduction type semiconductor emitting region 4 and the first conduction type semiconductor emitting region 3, and is in contact with the gate electrode 61 through the isolation dielectric layer 2; the method is characterized in that: the second conductive type semiconductor base region 5 comprises a first semiconductor base region 52 and a second semiconductor base region 51 arranged on the upper surface of the first forbidden band semiconductor base region 52, the forbidden band width of the second semiconductor is larger than that of the first semiconductor, and the first semiconductor base region 52 and the second semiconductor base region 51 with different forbidden band widths form homotype heterojunction at the contact interface.
Further, in the present invention, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
Further, the doping concentrations of the second conductivity type semiconductor base regions 5 may be the same or different, and when the doping concentrations are different, gradient doping is formed in which the concentration is reduced from the bottom layer first semiconductor base region 52 to the top layer second semiconductor base region 51, and a potential barrier is further formed through a concentration gradient, so that minority carriers in the drift region are prevented from entering the base region.
Further, the second conductive type semiconductor base region 5 further includes a third semiconductor base region 53 located on the lower surface of the first semiconductor base region 52, and the forbidden bandwidth of the third semiconductor layer is greater than that of the first semiconductor base region, so that another potential barrier is introduced in the heterojunction, and the voltage withstanding effect is also achieved, so that the device has no breakdown voltage loss while the conductance modulation effect is enhanced, and the defect of the conventional CSTBT structure is overcome.
Further, the inventive heterojunction can be formed of any semiconductor material with different forbidden band widths, such as Si1-xGex、Si、SiC、GaAs、Ga2O3Diamond or GaN.
Further, when the semiconductor material forming the heterojunction employs Si1-xGexWhen the grid structure is a groove grid structure, Si is close to two side regions of the groove grid structure in the base region1-xGexThe material has a value of x greater than the intermediate region Si1-xGexThe value x of the material is favorable for most minority carriers to flow out from the middle part of the base region, so that the function of inhibiting the latch-up effect of the IGBT is realized.
Further, when the semiconductor material forming the heterojunction employs Si1-xGexWhen the material is prepared, the forbidden bandwidth of the material can be adjusted by adjusting the component ratio x of Ge, so that different barrier heights are introduced, and further Si can be used1-xGexThe component ratio x of Ge in the material is gradually changed to change the energy band width to form a potential barrier, so that the carrier concentration distribution in a drift region is improved, and more excellent device characteristics are obtained. According to an embodiment of the present invention, the material of the first semiconductor base region 52 is Si1-xGexThe material of the second semiconductor base region 51 is Si.
Further, a first conductivity type semiconductor field stop layer 11 is further disposed between the second conductivity type semiconductor collector region 12 and the first conductivity type semiconductor drift region 9, so as to form an FS structure.
Furthermore, a charge storage type IGBT device is formed by interposing the first conductivity type semiconductor charge storage layer 7 between the second conductivity type semiconductor base region 5 and the first conductivity type semiconductor drift region 9. When the gate structure adopts a trench gate structure, the junction depth of the first conductivity type semiconductor charge storage layer 7 is smaller than the trench depth of the trench gate structure.
Further, the gate structure may be a trench gate structure or a planar gate structure.
Further, when the gate structure is a trench gate structure, the depth of the gate electrode 61 is larger than the depth of the lower surface of the first conductivity type semiconductor charge storage layer 7.
Furthermore, when the gate structure is a trench gate structure, a second conductivity type semiconductor layer 10 is further disposed at the bottom of the trench gate structure, and the second conductivity type semiconductor layer 10 laterally extends to the first conductivity type drift region 9 below the first conductivity type semiconductor charge storage layer 7 towards two sides.
Furthermore, when the gate structure is a trench gate structure, the trench gate structure is further provided with a split electrode 81 and a split electrode dielectric layer 82 which are located below the gate electrode 61; the gate electrode 61 is in contact with the split electrode 81 through the gate dielectric layer 62, the depth of the gate electrode 61 is greater than the junction depth of the second conductive type semiconductor base region 5 and less than the junction depth of the first conductive type semiconductor charge storage layer 7, the depth of the split electrode 81 is greater than the junction depth of the first conductive type semiconductor charge storage layer 7, and the split electrode 81 is in contact with the first conductive type semiconductor charge storage layer 7 and the first conductive type semiconductor drift region 9 through the split electrode dielectric layer 82; the split electrode 81 is equipotential with the emitter metal 1. Preferably, the thickness of the split electrode dielectric layer 82 is greater than the thickness of the gate dielectric layer 62,
further, the material of the gate electrode 61 may be selected from polysilicon, SiC, GaAs, or GaN.
A preparation method of an insulated gate bipolar transistor with a heterojunction charge storage layer is characterized by comprising the following steps: the method comprises the following steps:
step 1: preparing a semiconductor substrate for forming a first conductive type semiconductor drift region;
step 2: sequentially forming a second conductive type semiconductor base region consisting of a first semiconductor base region and a second semiconductor base region positioned on the upper surface of the first semiconductor base region on the upper surface of the first conductive type semiconductor drift region, wherein the forbidden bandwidth of the second semiconductor is larger than that of the first semiconductor;
and step 3: forming a trench gate structure by etching a trench, oxidizing and depositing;
and 4, step 4: depositing a dielectric layer on the surface of the device, and forming an isolation dielectric layer on the upper surface of the gate structure by adopting photoetching and etching processes;
and 5: forming first conductive type semiconductor emitter regions positioned at two sides of the top layer of the second conductive type semiconductor base region by photoetching and ion implantation of first conductive type impurities; then forming second conductive type semiconductor emitting regions which are contacted with the first conductive type semiconductor emitting regions on two sides and are arranged side by photoetching and ion implantation of second conductive type impurities;
step 6: depositing metal on the surface of the device, and forming emitter metal on the upper surfaces of the isolation dielectric layer, the first conduction type semiconductor emitting region and the second conduction type semiconductor emitting region by adopting photoetching and etching processes;
and 7: overturning the silicon wafer, reducing the thickness of the silicon wafer, injecting second conductive type impurities into the back of the silicon wafer and annealing to form a second conductive type semiconductor collector region;
and 8: and depositing metal on the back surface to form a collector metal.
Further, before the step 2, the method further comprises: and forming a device terminal structure positioned on the front surface of the semiconductor substrate on the surface through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes.
Further, before the step 2, forming a third semiconductor base region under the first semiconductor base region by adding an ion implantation process, wherein the forbidden bandwidth of the third semiconductor base region is greater than that of the first semiconductor, so as to form a heterojunction with the first semiconductor base region.
Further, step 2 is preceded by forming a first conductivity type semiconductor charge storage layer by ion implantation of first conductivity type impurities.
Further, the material of the semiconductor used for forming the heterojunction in the present invention is Si1-xGexDuring the process, germanium-silicon materials with different energy band structures can be obtained by adjusting the component ratio x and the strain of Ge, so that the forbidden bandwidth of the materials is changed.
Further, when the material of the first semiconductor base region 52 is Si1-xGexThe material of the second semiconductor base region 51 is Si, and the step 1 may specifically form P-type Si by using techniques such as Molecular Beam Epitaxy (MBE), low-pressure chemical vapor deposition (LPCVD), or ultra-high vacuum chemical vapor deposition (UHV/CVD)1-xGexBase region, then epitaxial process, on P-type Si1-xGexAnd a P-type Si base region is formed on the upper surface of the base region. The MBE can be divided into solid-phase MBE and gas-phase molecular beam epitaxy GSMBE, has higher degree of freedom of control, can independently control the substrate temperature and the growth rate, is convenient for realizing low-temperature growth, and is beneficial to obtaining steep component gradient change and high doping; CVD has the capability of mass production, can control lower growth rate, and can obtain high doping and steep interface distribution.
Further, the specific operation of etching the trench and filling the trench to form the gate structure in the step 3 is to deposit a protective layer on the surface of the drift region of the first conductivity type semiconductor, and photoetching a window to etch the trench, wherein the depth of the trench is greater than the junction depth of the heterojunction charge storage layer of the first conductivity type semiconductor; and then forming a gate dielectric layer on the inner wall of the groove, and depositing materials such as polysilicon, silicon carbide, gallium arsenide or gallium nitride and the like in the groove to form a gate electrode.
Further, the second conductive type semiconductor region may be formed by ion-implanting second conductive type impurities at the bottom of the trench after forming the trench gate structure in step 3.
Furthermore, in the step 3, when the trench gate structure is formed, a split trench gate structure may be formed by adding photolithography, etching, oxidation and polysilicon deposition processes.
Further, in step 7, a first conductivity type semiconductor field stop layer may be formed by first conductivity type impurities and annealing before forming the second conductivity type semiconductor collector region.
Furthermore, the semiconductor material used for the second semiconductor base region may be the same as or different from the semiconductor material used for the device.
Further, the inventive heterojunction can be formed of any semiconductor material with different forbidden band widths, such as Si1-xGex、Si、SiC、GaAs、Ga2O3Diamond or GaN.
Further, in the present invention, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
The principle of the invention is as follows: in order to avoid the adverse effect of a charge storage layer on the voltage resistance of the device, the conduction characteristic of the insulated gate bipolar transistor is improved, and meanwhile, a higher breakdown voltage value is kept. Specifically, the present invention is improved from the following three aspects:
1. the energy band of the heterojunction is bent by introducing the heterojunction into the base region, so that a potential barrier (a hole potential barrier for an N-channel device and an electron potential barrier for a P-channel device) for blocking minority carriers from flowing into the base region is arranged at one side of the drift region close to the low-doped drift region, thereby greatly improving the carrier concentration distribution of the drift region, enhancing the conductance modulation effect of the IGBT, reducing the forward conduction voltage drop Vceon, and improving the compromise characteristic between the forward conduction voltage drop Vceon and the turn-off loss Eoff;
2. different potential barrier heights are introduced by reasonably combining semiconductor materials with different forbidden band widths used by the base region to form a heterojunction, so that the carrier concentration distribution of the drift region is further optimized, and more excellent device characteristics are obtained.
3. The homotype semiconductor layer with the material forbidden band width larger than that of the contacted bottom narrow forbidden band semiconductor material is introduced below the base region for forming the heterojunction, so that the homotype semiconductor layer and the base region for forming the heterojunction form a double potential barrier, and the homotype semiconductor layer can play a voltage withstanding role, so that the device has no breakdown voltage loss while the conductance modulation effect is enhanced, and the defects of the traditional CSTBT structure are overcome.
4. When the semiconductor material forming the heterojunction adopts Si1-xGexWhen the grid structure is a groove grid structure, Si is close to two side regions of the groove grid structure in the base region1-xGexThe material has a value of x greater than the intermediate region Si1-xGexThe value x of the material is favorable for large outflow of most minority carriers from the middle part of the base region due to the large forbidden bandwidth, so that the function of inhibiting the latch-up effect of the IGBT is realized.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, on the basis of the traditional charge storage type IGBT device structure, a heterojunction structure is formed in the base region, so that a potential barrier for blocking minority carriers in the drift region from flowing into the base region is formed, the minority carrier concentration in the drift region close to one side of the emitter is greatly improved, the carrier distribution concentration in the drift region is improved, the conductance modulation effect of the IGBT is enhanced, the forward conduction voltage drop Vceon of the device is reduced, and the compromise characteristic between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the IGBT is optimized; the defect that the breakdown voltage is reduced when the Vceon is reduced in the traditional charge storage layer is overcome; the working characteristics of the device can be further optimized by adjusting the combination of semiconductor materials with different forbidden band widths forming the heterojunction structure; for the groove gate type IGBT device, the flowing-out path of minority carriers in a base region can be controlled by adjusting the forbidden bandwidth of the semiconductor close to the regions on two sides of the groove gate structure and the region sandwiched between the regions, so that the IGBT latch-up effect is suppressed.
Drawings
Fig. 1 is a schematic diagram of a half-cell structure of a conventional trench-gate charge storage igbtcsbt device.
Fig. 2 shows the energy band distribution of the P-type base region, the N-type charge storage layer and the N-drift region in the conventional trench gate charge storage type igbtcsbt device under zero bias.
FIG. 3 shows the energy band distributions of the P-type base region, the N-type charge storage layer and the N-drift region of a conventional trench-gate charge storage type IGBTCSTBT device under a positive bias of 2V,
FIG. 4 shows strained Si-Si according to example 1 of the present invention1-xGexAnd the half cell structure schematic diagram of the heterojunction trench type IGBT device.
FIG. 5 shows P-type Si-Si1-xGexThe energy band distribution of the heterojunction at zero bias.
FIG. 6 shows P-type Si-Si1-xGex-the band distribution of the Si heterojunction at zero bias.
FIG. 7 shows strained Si-S according to example 1 of the present inventioni0.4Ge0.6Of heterojunction P-type base regionsAnd energy bands of the P-type base region and the N-drift region of the trench type IGBT device are distributed when the trench type IGBT device is zero-biased.
FIG. 8 shows strained Si-Si according to example 1 of the present invention0.4Ge0.6The energy band distribution of the P-type base region and the N-drift region of the groove type IGBT device of the heterojunction P-type base region is realized when a positive bias voltage of 2V is applied.
FIG. 9 shows strained Si-Si according to example 1 of the present invention1-xGexEnergy band distribution of the P-type base region and the N-drift region of the groove type IGBT device with the heterojunction P-type base region is compared when the groove type IGBT device is under zero bias under different Ge component content x.
FIG. 10 shows strained Si-Si according to example 1 of the present invention1-xGexAnd energy band distribution of the P-type base region and the N-drift region of the groove type IGBT device of the heterojunction P-type base region is compared when a positive bias voltage of 2V is applied under different Ge component contents x.
FIG. 11 shows strained Si-Si according to example 2 of the present invention1-xGexAnd a schematic diagram of a half-cell structure of the trench type IGBT device with the Si heterojunction P type base region.
FIG. 12 shows strained Si-Si according to example 2 of the present invention0.4Ge0.6And energy band distribution of the P-type base region and the N-drift region of the trench type IGBT device of the Si heterojunction P-type base region at zero bias.
FIG. 13 shows strained Si-Si according to example 2 of the present invention0.4Ge0.6And energy band distribution of the P-type base region and the N-drift region of the trench type IGBT device of the Si heterojunction P-type base region when a positive bias voltage of 2V is applied.
FIG. 14 shows strained Si-Si according to example 2 of the present invention1-xGexEnergy band distribution of a P-type base region and an N-drift region of a trench type IGBT device of the Si heterojunction P-type base region is compared when the P-type base region and the N-drift region are zero offset under different Ge component contents x;
FIG. 15 shows strained Si-Si according to example 2 of the present invention1-xGexComparing the energy band distribution of the P-type base region and the N-drift region of the trench type IGBT device of the Si heterojunction P-type base region under different Ge component content x when a positive bias voltage is applied to the trench type IGBT device of the Si heterojunction P-type base region under different Ge component content x;
FIG. 16 is the present inventionEmbodiment 3 of the invention provides strained Si-Si1-xGexA schematic diagram of a half-cell structure of a trench gate charge storage type IGBT device of a Si heterojunction P type base region;
FIG. 17 shows strained Si-Si according to example 4 of the present invention1-xGexA schematic diagram of a half-cell structure of a trench gate charge storage type IGBT device of a Si heterojunction P type base region;
FIG. 18 shows strained Si-Si according to example 5 of the present invention1-xGexA schematic diagram of a half-cell structure of a trench gate charge storage type IGBT device of a Si heterojunction P type base region;
FIG. 19 shows strained Si-Si according to example 6 of the present invention1-xGexA schematic diagram of a half-cell structure of a planar IGBT device with a Si heterojunction P-type base region;
in fig. 1 to 19, 1 is an emitter metal, 2 is an isolation dielectric layer, 3 is an N + emitter region, 4 is a P + emitter region, 51 is a P-type Si base region, and 52 is a P-type Si base region1-xGexThe base region 53 is a P-type Si layer, 61 is a gate electrode, 62 is a gate dielectric layer, 7 is an N-type charge storage layer, 81 is a split electrode, 82 is a split electrode dielectric layer, 9 is an N-drift region, 10 is a P-type layer, 11 is an N-type field stop layer, 12 is a P-type collector region, and 13 is a collector metal.
Detailed Description
So that those skilled in the art can better understand the principle and the scheme of the present invention, the following detailed description is given with reference to the accompanying drawings and specific embodiments. The teachings of the present invention are not limited to any particular embodiment nor represent the best embodiment, and general alternatives known to those skilled in the art are also encompassed within the scope of the present invention.
The structure, the manufacturing process, the principle and the characteristics of the device are described below by taking an N-channel IGBT device as an example, and those skilled in the art can easily derive the structure, the manufacturing process, the principle and the characteristics of the P-channel IGBT device based on the disclosure of the N-channel device.
Example 1;
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor with a heterojunction base region, of which fig. 4 shows a half-cell structure, the cell structure comprising: a collector metal 13, a P-type collector region 12, an N-type drift region 9, a P-type base region 5, a P + emitter region 4, an N + emitter region 3, a gate structure and an emitter metal 1; the collector metal 13 is arranged on the back of the P-type collector region 12; the N-type drift region 9 is arranged on the front surface of the P-type collector region 12; the P-type base region 5 is arranged on the top layer of the N-type drift region 9; the P + emitter region 4 and the N + emitter regions 3 which are contacted with the two sides of the P + emitter region 4 are arranged on the top layer of the P-type base region 5 side by side; the gate structure comprises a gate electrode 61 and a gate dielectric layer 62, wherein the gate electrode 61 is in contact with the N + emitter region 3 and the P-type base region 5 through the gate dielectric layer 62; the emitter metal 1 is arranged on the uppermost surface of the device, is in contact with the upper surfaces of the P + emitting region 4 and the N + emitting region 3, and is in contact with the gate electrode 61 through the isolation dielectric layer 2; the method is characterized in that: the P-type base region 5 comprises P-type Si1-xGexBase region 52 and P-type Si1-xGexP-type Si base region 51 on upper surface of base region 52, P-type Si1-xGexThe base region 52 and the P-type Si base region 51 form a homotype heterojunction at their contact interface. In this embodiment, the junction depth of the P-type Si base region 51 is 2 μm, and the junction depth of the P-type Si base region 51 is 0.5 μm; the junction depth of the N + emission region 3 and the P + emission region 4 is 0.5 μm; the trench depth of the trench gate structure was 6 μm.
The principle of the invention is explained in detail below with reference to fig. 5 to 8:
as shown in FIG. 5, is P-type Si-Si1-xGexThe energy band distribution diagram of the heterojunction structure at zero offset shows that holes are formed from P-type Si1-xGexOne side implanted Si needs to overcome a certain barrier height. FIG. 6 shows P-type Si-Si1-xGexThe energy band distribution diagram of the Si heterojunction structure at zero offset indicates that Si in the structure1-xGexA heterojunction is formed with Si on both sides to create two hole barriers.
FIGS. 7 and 8 are diagrams of P-type Si-Si in the device structure provided in example 1, respectively1-xGexThe energy band distribution of the P-type base region 5 and the N-drift region 9 when the heterojunction is under zero bias and plus positive bias 2V; by introducing Si to Si1-xGexHeterojunction makes P type base regionThe energy band within 5 is bent and therefore the heterojunction introduces a hole barrier on the side close to the N-drift region 9, increasing the concentration of holes there. Therefore, the carrier concentration distribution of the N-drift region is greatly improved, the conductance modulation effect of the IGBT is enhanced, the forward conduction voltage drop of the device is reduced under the condition of the same depth of the groove of the device and the groove MOS structure density, and the compromise characteristic between the forward conduction voltage drop Vceon and the turn-off loss Eoff of the device is improved.
Fig. 9 and 10 are the energy band distributions of the P-type base region 5 and the N-drift region 9 when the device structure provided by the present embodiment 1 is biased at zero and forward bias 2V under different Ge composition contents of x value, respectively. As can be seen from the figure, P-type Si1-xGexThe Ge component content x of the material is different, and the introduced barrier height is changed accordingly. Thus based on Si to Si1-xGexThe IGBT device of the heterojunction charge storage layer can adjust the content of the Ge component with the value of x through a process so as to adjust the performance of the device, and obtain lower forward conduction voltage drop and better forward conduction voltage drop Vceon and turn-off loss Eoff compromise characteristics. .
Example 2:
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor in the heterojunction base region, a half-cell structure of which is shown in fig. 11. This example is except for in P-type Si1-xGexThe lower surface of the layer 52 is added with a P-type Si layer 53 to form a double barrier, the junction depth of the P-type Si base region 51 and the P-type Si layer 53 is 1 μm, and the rest structure is the same as that of the embodiment 1.
This embodiment is implemented by adding P-type Si1-xGexThe P-type Si layer 53 is added on the lower surface of the base region 52, so that a heterojunction hole barrier is introduced, the conductance modulation effect of the device is further improved, the forward conduction voltage drop and the conduction loss of the device are reduced, and the compromise relation between the turn-off loss and the forward conduction voltage drop is improved.
FIGS. 12 and 13 are Si-Si provided in example 2, respectively0.4Ge0.6And energy band distribution of the P-type base region and the N-drift region of the trench type IGBT device of the Si heterojunction P-type base region under zero bias and 2V of external forward bias. As can be seen from figures 12 and 13,Si1- xGexa heterojunction is formed with Si on both sides to create two hole barriers.
In this embodiment, while introducing the double barrier as shown in fig. 12 and fig. 13, the P-type Si layer 53 can also function as a voltage withstanding function, so that the device has no breakdown voltage loss while the conductance modulation effect is enhanced, and the defect of the conventional csbt structure is overcome.
Fig. 14 and fig. 15 are the energy band distributions of the P-type base region 5 and the N-drift region 9 when the device structure provided by the present embodiment 2 is biased at zero and forward bias 2V under different Ge composition contents of x value, respectively. As can be seen from the figure, P-type Si1-xGexThe Ge component content x of the material is different, and the introduced barrier height is changed accordingly. Thus based on Si to Si1-xGexThe IGBT device of the heterojunction charge storage layer can adjust the x value (Ge component content) through a process so as to adjust the performance of the device, and obtain lower forward conduction voltage drop and better forward conduction voltage drop Vceon and turn-off loss Eoff compromise characteristics.
Example 3:
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor in the heterojunction base region, a half-cell structure of which is shown in fig. 16. This embodiment is the same as embodiment 2 except that an N-type charge storage layer 7 having a junction depth of 2 μm is introduced below the P-type base region 5.
In the embodiment, the hole barrier is introduced at the side of the N-drift region 9 close to the emitter by introducing the N-type charge storage layer 7, so that the conductance modulation effect of the device is further improved, the forward conduction voltage drop and the conduction loss of the device are reduced, and the compromise relationship between the turn-off loss and the forward conduction voltage drop is improved.
Example 4:
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor of the heterojunction base region, a half-cell structure of which is shown in fig. 17. The structure of this embodiment is the same as that of embodiment 1 except that a P-type layer 10 with a junction depth of 0.5 to 1 μm is introduced at the bottom of the trench gate structure.
In the embodiment, the P-type layer 10 connected with the gate electrode 61 through the gate dielectric layer 62 is introduced, and the P-type layer 10 transversely extends towards two sides into the N-drift region 9 below the heterojunction N-type charge storage layer 7, so that the influence of negative charges in the N-type charge storage layer 7 is shielded, the electric field concentration at the bottom of the trench is improved, and the breakdown voltage and the reliability of the device are improved.
Example 5:
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor with a heterojunction base region, a half-cell structure of which is shown in fig. 18. This embodiment is the same as embodiment 2 except that the split electrode 81 and the split electrode dielectric layer 82 are introduced into the trench gate structure 6 to form a split trench gate structure.
The depth of a gate electrode 61 in the split trench gate structure is greater than the junction depth of the P-type base region 5 and less than the junction depth of the N-type charge storage layer 7; the depth of the split electrode 82 is greater than the junction depth of the N-type charge storage layer 7; the split electrode 82 is connected with the gate electrode 61 through the gate dielectric layer 62, and is connected with the N-type charge storage layer 7 and the N-drift region 9 through the split electrode dielectric layer 82; the thickness of the split electrode dielectric layer 82 is greater than the thickness of the gate dielectric layer 62; the split electrode 81 is equipotential with the emitter metal 1.
In the embodiment, the split electrode 81 and the thick split electrode dielectric layer 82 are introduced, and the depth of the gate electrode 61 is reduced, so that the influence of the doping concentration of the N-type charge storage layer 7 on the withstand voltage of the device is shielded, the gate capacitance is reduced, the switching speed of the device is increased, the switching loss is reduced, meanwhile, the electric field concentration at the bottom of the trench is improved, and the breakdown voltage and the reliability of the device are improved.
Example 6:
the present example provides a strained Si-Si1-xGexAn insulated gate bipolar transistor in the heterojunction base region, a half-cell structure of which is shown in fig. 19. This embodiment is the same as embodiment 1 except that a planar gate structure is used.
Example 7:
step 1: adopting N-type lightly doped monocrystalline silicon wafer as N-drift region of device, selecting siliconThe thickness of the sheet is 300-600 um, and the doping concentration is 1013～1014Per cm3；
Step 2: manufacturing a terminal structure of a device on the front surface of the silicon wafer through pre-oxidation, photoetching, etching, ion implantation and high-temperature annealing processes on the surface of the silicon wafer;
and step 3: the P-type Si is prepared on the upper surface of the N-drift region by Molecular Beam Epitaxy (MBE) or low-pressure chemical vapor deposition (LPCVD) or ultra-high vacuum chemical vapor deposition UHV/CVD1-xGexLayer, then epitaxial process, on P-type Si1-xGexGrowing a P-type Si layer base region on the upper surface of the layer, and P-type Si1-xGexThe layer and the P-type Si layer base region are jointly used as a P-type base region of the device;
and 4, step 4: depositing a TEOS protective layer with the thickness of 700-1000 nm on the surface of a silicon wafer, photoetching a window to perform groove silicon etching, and further etching an N-drift region to form a groove with a groove gate structure, wherein the depth of the groove is greater than the junction depth of a P-type base region;
and 5: o at 1050-1150 deg.C2Forming a gate dielectric layer on the inner wall of the trench under the atmosphere, and then depositing polycrystalline silicon in the trench at 750-950 ℃ to form a gate electrode;
step 6: carrying out photoetching and ion implantation of N-type impurities, wherein the energy of the ion implantation of the N-type impurities is 30-60 keV, and the implantation dosage is 1015～1016Per cm2Obtaining an N + emitting region of the device; then, photoetching and ion implantation of P-type impurities are carried out, the energy of the ion implantation of the P-type impurities is 60-80 keV, and the implantation dosage is 1015～1016Per cm2Annealing at 900 ℃ for 20-30 minutes to obtain a P + emitting region of the device; one side of the N + emission region is connected with the gate electrode through the gate dielectric layer, and the other side of the N + emission region is connected with the P + emission region; the N + emission region and the P + emission region are arranged in the P-type Si side by side1-xGexA layer top;
and 7: depositing a dielectric layer on the surface of the device, and forming the dielectric layer on the upper surfaces of the polysilicon gate electrode and the gate dielectric layer by adopting photoetching and etching processes;
and 8: depositing metal on the surface of the device, and forming emitter metal on the upper surfaces of the dielectric layer, the N + emitting region and the P + emitting region by adopting photoetching and etching processes;
and step 9: turning over the silicon wafer, thinning the thickness of the silicon wafer, injecting N-type impurities into the back of the silicon wafer, annealing and manufacturing an N-type field stop layer of the device, wherein the thickness of the N-type field stop layer is 15-30 mu m, the energy of ion injection is 1500-2000 keV, and the injection dosage is 1013～1014Per cm2The annealing temperature is 1200-1250 ℃, and the time is 300-600 minutes; injecting P-type impurities into the back of the N-type field stop layer to form a P-type collector region, wherein the injection energy is 40-60 keV, and the injection dosage is 1012～1013Per cm2In H2And N2Carrying out back annealing in a mixed atmosphere at the temperature of 400-450 ℃ for 20-30 minutes;
step 10: the backside deposited metal forms the collector metal.
Further, step 3 can be preceded by adding an ion implantation process to the P-type Si1-xGexA P-type Si layer 53 is formed below layer 52;
further, before step 3, an N-type charge storage layer 7 may be formed by ion implantation of N-type impurities, wherein the energy of the ion implantation is 200 to 500keV, and the implantation dose is 1013～1014Per cm2；
Further, the P-type layer 10 can be formed at the bottom of the trench by adding ion implantation P-type impurities;
further, a split trench gate structure can be formed by adding photolithography, etching, oxidation and polysilicon deposition processes;
further, the preparation of the N-type field stop layer 11 in step 9 of the present invention may be performed before the preparation of the front structure of the device; or a double-layer epitaxial material with an N-type field stop layer 11 and an N-drift region 9 can be directly selected as a silicon wafer material for starting the process;
further, the preparation of the N-type field stop layer 11 in step 9 of the process of the present invention may be omitted;
further, the materials of the isolation dielectric layer 2, the gate dielectric layer 62 and the split electrode dielectric layer 82 may be the same material or different materials.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A kind of insulated gate bipolar transistor, its cellular structure includes: a collector metal (13), a second conductivity type semiconductor collector region (12), a first conductivity type semiconductor drift region (9), a second conductivity type semiconductor base region (5), a second conductivity type semiconductor emitter region (4), a first conductivity type semiconductor emitter region (3), a gate structure and an emitter metal (1); a collector metal (13) is provided on the back surface of the second conductivity type semiconductor collector region (12); the first conduction type semiconductor drift region (9) is arranged on the front surface of the second conduction type semiconductor collector region (12); the second conductive type semiconductor base region (5) is arranged on the top layer of the first conductive type semiconductor drift region (9); the second conductive type semiconductor emitter region (4) and the first conductive type semiconductor emitter region (3) which is contacted with two sides of the second conductive type semiconductor emitter region (4) are arranged on the top layer of the second conductive type semiconductor base region (5) side by side; the grid structure comprises a grid electrode (61) and a grid dielectric layer (62), wherein the grid electrode (61) is in contact with the first conduction type semiconductor emitter region (3) and the second conduction type semiconductor base region (5) through the grid dielectric layer (62); the emitter metal (1) is arranged on the uppermost surface of the device, is in contact with the upper surfaces of the second conduction type semiconductor emitting region (4) and the first conduction type semiconductor emitting region (3), and is in contact with the gate electrode (61) through the isolation dielectric layer (2); the method is characterized in that: the second conductive type semiconductor base region (5) comprises a first semiconductor base region (52) and a second semiconductor base region (51) arranged on the upper surface of the first semiconductor base region (52), the forbidden bandwidth of the second semiconductor base region is larger than that of the first semiconductor base region, and the first semiconductor base region (52) and the second semiconductor base region (51) with different forbidden bandwidths form homotype heterojunction at the contact interface;
two sides of the second semiconductor base region (51) are contacted with the gate electrode (61) through a gate dielectric layer (62), and the first semiconductor base region (52) is arranged between the second semiconductor base region (51) and the first conductive type semiconductor drift region (9);
the material of the first semiconductor base region (52) is Si(1-x)Ge(x)The material of the second semiconductor base region (51) is Si, and the material of the first conduction type semiconductor drift region (9) is Si; the first semiconductor base region (52) and the first conduction type semiconductor drift region (9) with different forbidden band widths form a special-shaped heterojunction;
when the grid structure is a groove grid structure, the areas Si close to two sides of the groove grid structure in the second conductive type semiconductor base region(1-x)Ge(x)The material has a value of x greater than the intermediate region Si(1-x)Ge(x)The value of x for the material.
2. An insulated gate bipolar transistor according to claim 1, characterized in that a first conductivity type semiconductor field stop layer (11) is further provided between the second conductivity type semiconductor collector region (12) and the first conductivity type semiconductor drift region (9) to form an FS structure.
3. An insulated gate bipolar transistor according to claim 1, characterised in that the semiconductor base region (5) of the second conductivity type is separated from the semiconductor drift region (9) of the first conductivity type by a semiconductor charge storage layer (7) of the first conductivity type.
4. An insulated gate bipolar transistor according to claim 3, characterized in that when the gate structure is a trench gate structure, a second conductivity type semiconductor layer (10) is further disposed at the bottom of the trench gate structure, and the second conductivity type semiconductor layer (10) laterally extends to the first conductivity type semiconductor drift region (9) below the first conductivity type semiconductor charge storage layer (7) to both sides.
5. An insulated gate bipolar transistor according to claim 1, characterized in that when the gate structure is a trench gate structure, the trench gate structure is further provided with a split electrode (81) and a split electrode dielectric layer (82) under the gate electrode (61); the gate electrode (61) is in contact with the split electrode (81) through a gate dielectric layer (62), the depth of the gate electrode (61) is larger than the junction depth of the second conduction type semiconductor base region (5) and smaller than the junction depth of the first conduction type semiconductor charge storage layer (7), the depth of the split electrode (81) is larger than the junction depth of the first conduction type semiconductor charge storage layer (7), and the split electrode (81) is in contact with the first conduction type semiconductor charge storage layer (7) and the first conduction type semiconductor drift region (9) through a split electrode dielectric layer (82); the split electrode (81) is equipotential with the emitter metal (1).
6. The igbt of claim 1, wherein the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
7. A preparation method of an insulated gate bipolar transistor is characterized by comprising the following steps: the method comprises the following steps:
step 1: preparing a semiconductor substrate for forming a first conductive type semiconductor drift region;
step 2: a second conductive type semiconductor base region which is composed of a first semiconductor base region and a second semiconductor base region positioned on the upper surface of the first semiconductor base region is sequentially formed on the upper surface of the first conductive type semiconductor drift region, the forbidden bandwidth of the second semiconductor base region is larger than that of the first semiconductor base region, the first semiconductor base region (52) is made of Si(1-x)Ge(x)The material of the second semiconductor base region (51) is Si, and the first semiconductor base region (52) is arranged between the second semiconductor base region (51) and the first conductive type semiconductor drift region (9); the material of the first conduction type semiconductor drift region (9) is Si; different forbidden bandwidthThe first semiconductor base region (52) and the first conductive type semiconductor drift region (9) form a special-shaped heterojunction;
and step 3: forming a trench gate structure by etching a trench, oxidizing and depositing, wherein two sides of a second semiconductor base region (51) are in contact with the trench gate structure, and regions Si in the second conductive type semiconductor base region near two sides of the trench gate structure(1-x)Ge(x)The material has a value of x greater than the intermediate region Si(1-x)Ge(x)The value of x for the material;
and 4, step 4: depositing a dielectric layer on the surface of the device, and forming an isolation dielectric layer on the upper surface of the gate structure by adopting photoetching and etching processes;
and 5: forming first conductive type semiconductor emitter regions positioned at two sides of the top layer of the second conductive type semiconductor base region by photoetching and ion implantation of first conductive type impurities; then forming second conductive type semiconductor emitting regions which are contacted with the first conductive type semiconductor emitting regions on two sides and are arranged side by photoetching and ion implantation of second conductive type impurities;
step 6: depositing metal on the surface of the device, and forming emitter metal on the upper surfaces of the isolation dielectric layer, the first conduction type semiconductor emitting region and the second conduction type semiconductor emitting region by adopting photoetching and etching processes;
and 7: overturning the silicon wafer, reducing the thickness of the silicon wafer, injecting second conductive type impurities into the back of the silicon wafer and annealing to form a second conductive type semiconductor collector region;
and 8: and depositing metal on the back surface to form a collector metal.
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| CN113497112B (en) * | 2020-03-19 | 2023-05-05 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, intelligent power device and electronic product |
| CN114171598B (en) * | 2021-10-18 | 2023-03-24 | 浙江芯科半导体有限公司 | SiC MOSFET device based on boron nitride masking layer and preparation method thereof |
| CN116344573A (en) * | 2021-12-22 | 2023-06-27 | 苏州东微半导体股份有限公司 | IGBT device and manufacturing method thereof |
| CN114937691A (en) * | 2022-07-22 | 2022-08-23 | 深圳市威兆半导体股份有限公司 | Insulated gate bipolar transistor and preparation method thereof |
| CN117497576B (en) * | 2023-11-30 | 2024-09-27 | 江苏索力德普半导体科技有限公司 | Groove type SiC power device with heterojunction and preparation method |
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