CN114442786B - Power failure warning and recovering method, device and storage medium - Google Patents
Power failure warning and recovering method, device and storage medium Download PDFInfo
- Publication number
- CN114442786B CN114442786B CN202210072492.XA CN202210072492A CN114442786B CN 114442786 B CN114442786 B CN 114442786B CN 202210072492 A CN202210072492 A CN 202210072492A CN 114442786 B CN114442786 B CN 114442786B
- Authority
- CN
- China
- Prior art keywords
- fault
- power supply
- bit
- target power
- condition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 230000004044 response Effects 0.000 claims abstract description 66
- 238000011084 recovery Methods 0.000 claims abstract description 45
- 238000001514 detection method Methods 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 description 11
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The invention relates to a power failure warning and recovering method, a device and a storage medium. In the invention, after detecting that a fault position in a power state bit of a target power supply is set, pulling down a quick response pin of the target power supply; immediately reading a fault bit value in a power state bit of a target power supply in response to the low level of the quick response pin, and acquiring the setting condition of the fault bit; sending out corresponding fault alarm information according to the setting condition of the fault position, and selecting a corresponding fault clearing instruction to be sent to a target power supply; the target power supply restores the quick response pin to a high level after receiving the fault clearing instruction; after the target power supply executes the fault clearing instruction and meets the fault bit recovery condition, recovering the fault position bit; and acquiring and releasing the corresponding fault alarm information according to the fault position bit recovery condition. When the power supply fails, the power supply is accessed to obtain the power supply failure, corresponding failure alarm information is generated according to the failure, and corresponding failure clearing instructions are issued to recover the failure.
Description
Technical Field
The present invention relates to the field of power management technologies, and in particular, to a power failure warning and recovering method, apparatus, and storage medium.
Background
In order to ensure the power supply safety of the server, the power supply in the server often adopts a redundant design, and the continuous and stable power supply of the server is ensured through the redundancy of the power supply.
Currently, in a server power management design, a Baseboard Management Controller (BMC) is often used to poll and access a server power, and corresponding fault alarm information and fault release information are generated according to the setting condition of a fault position of the server power. The fault alarm is generated by the condition that the BMC polls the fault position of the power supply of the access server, when the power supply fails but is not polled by the BMC, the BMC cannot timely generate the fault alarm and adopts a corresponding fault processing means for fault aiming at the fault alarm, so that the problem of lag of the fault alarm exists. If the power supply fails and cannot be recovered in time, the redundant design of the power supply of the server is destroyed, the stable power supply of the server is influenced, and the service and data security of the server are threatened.
Disclosure of Invention
In order to solve the above technical problems or at least partially solve the above technical problems, the present invention provides a power failure warning and recovering method, a device and a storage medium.
In a first aspect, the present invention provides a power failure warning and recovery method, including:
after detecting that the fault bit in the power state bit of the target power supply is set, pulling down the fast response pin of the target power supply;
responding to the low level of the quick response pin, immediately reading a fault bit in a power state bit of the target power supply, sending corresponding fault alarm information according to the setting condition of the fault bit, and selecting a corresponding fault clearing instruction to send to the target power supply;
the target power supply restores the quick response pin to a high level after receiving the fault clearing instruction;
after the target power supply executes the fault clearing instruction and meets the fault bit recovery condition, recovering the fault position bit;
and releasing the corresponding fault alarm information according to the fault position bit recovery condition.
Further, before the fast response pin is restored to the high level, after the target power supply detects a new fault, the target power supply restores the fast response pin to the high level and pulls down again, and the fault bit in the power state bit of the target power supply is immediately read in response to the low level of the fast response pin, so that the setting condition of the fault bit is obtained.
Further, counting the set fault bit of the power supply as a reference setting condition, comparing whether the current set fault bit has the increase of the fault bit relative to the reference setting condition, and judging that a new fault occurs if the current set fault bit has the increase of the fault bit relative to the reference setting condition; and when the value of the fault bit is changed, the fault bit with the set power supply is counted to update the reference setting condition.
Further, after the target power supply executes the fault clearing instruction and satisfies the fault bit recovery condition, recovering the fault location bit includes:
after the target power supply executes the fault clearing instruction, detecting whether the target power supply is in a patched state;
if yes, the target power supply detects whether a transmitted restarting instruction is received, the target power supply executes the restarting instruction and after the restarting instruction is received, the target power supply fault is eliminated, the fault position bit is recovered by the target power supply, the fault position bit value of the target power supply is reserved if the fault of the target power supply is not eliminated, the fault position bit value is reserved if the restarting instruction is not received, and the target power supply is still in a patched state;
otherwise, the fault of the target power supply is eliminated, the fault position bit is recovered by the target power supply, and the fault position value is reserved if the fault of the target power supply is not eliminated.
Further, a fault represented by each fault position bit is preconfigured, and a fault clearing instruction corresponding to the fault is preconfigured;
determining the faults of the target power supply according to the fault position situation of the target power supply and faults represented by each preset fault position, and generating corresponding fault alarm information;
and selecting a corresponding fault clearing instruction according to the fault position condition of the target power supply, faults represented by each pre-configured fault position and the fault clearing instruction corresponding to the pre-configured faults, and sending the fault clearing instruction to the target power supply.
Further, the obtaining the fault location bit recovery condition and releasing the corresponding fault alarm information according to the fault location bit recovery condition includes: and accessing the power state bits of each power supply in a polling mode, and releasing corresponding fault alarm information after detecting that the fault bit of the power supply with the fault is recovered.
Further, the power status bits of each power supply are accessed by polling, the power status bits of the polling power supply are interrupted in response to the low level of the fast response pin of the target power supply, and the fault bit in the power status bits of the target power supply is immediately read.
In a second aspect, the present invention provides an apparatus for implementing a power failure warning and recovery method, including: the fault detection module detects faults generated by the power supply;
the fault position setting module is used for setting corresponding fault positions according to the faults detected by the fault detection module and recovering the corresponding fault positions according to the recovered faults;
the quick response module is used for controlling the level of the quick response pin according to the setting condition of the fault position and the condition of receiving a fault clearing instruction;
the instruction execution module receives and executes the fault clearing instruction;
the fault reading module is used for responding to the low level generated by the fast response pin of the target power supply to read fault bits in the power state bits of the target power supply;
the fault alarm module is used for sending corresponding fault alarm information according to the setting condition of the fault position of the target power supply;
the alarm releasing module is used for releasing corresponding fault alarm information according to the recovery condition of the fault bit of the target power supply;
and the fault processing module selects a corresponding fault clearing instruction according to the setting condition of the target power supply fault position and sends the fault clearing instruction to the instruction execution module.
Preferably, the device for implementing the power failure warning and recovering method further includes: the polling access module polls and accesses the fault bit of the power state bit of each power supply to acquire the fault bit value of each power supply, and obtains the fault bit recovery condition of the target power supply by comparing the fault bit condition reflected by the target power supply fault bit value acquired by polling with the fault bit condition of the target power supply when the target power supply fails.
In a third aspect, the present invention provides a storage medium for implementing a power failure warning and recovery method, where the storage medium implementing the power failure warning and recovery method stores at least one instruction, and reads and executes the instruction to implement the power failure warning and recovery method.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
when a fault is detected, the target power supply sets a corresponding fault position in power state bits of the target power supply, and after the fault position is detected, the quick response pin is controlled to generate low level; and immediately reading the fault bit value of the target power supply in response to the low level of the quick response pin, acquiring the fault position bit condition, generating corresponding fault alarm information according to the fault position bit condition, and selecting a corresponding fault clearing instruction according to the fault position bit condition and sending the fault clearing instruction to the target power supply. Therefore, the BMC is immediately informed of the fault of the target power supply, the BMC immediately generates corresponding fault alarm information according to the fault of the target power supply, and a corresponding fault clearing instruction is selected to issue so as to rapidly solve the fault of the target power supply. Compared with the mode of polling access to the power supply, the method has the advantages that the fault alarm and fault processing lag time is short, and the power supply safety of the server is fully ensured.
In the application, before the quick response pin is restored to the high level, after the target power supply detects a new fault, the target power supply restores the quick response pin to the high level and pulls down again, so that the BMC can be timely notified when the target power supply generates the new fault. The BMC is ensured to be capable of timely grasping all faults of the target power supply.
In the application, for faults affecting the continuous work of the power supply, after the faults are recovered, a restarting instruction can be timely sent to the power supply according to the patched state of the power supply, the corresponding power supply is timely restarted, and the power supply safety of the server is fully guaranteed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a power failure warning and recovery method according to an embodiment of the present invention;
FIG. 2 is a flow chart of sending out corresponding fault alarm information according to the setting condition of a fault bit and selecting a corresponding fault clearing instruction to be sent to a target power supply according to the embodiment of the invention;
FIG. 3 is a flowchart of recovering a fault location bit after a target power supply executes a fault clearing instruction and satisfies a fault bit recovery condition according to an embodiment of the present invention;
FIG. 4 is a flowchart of obtaining a fault location bit recovery condition and releasing corresponding fault alarm information according to the fault location bit recovery condition according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an apparatus for implementing a power failure warning and recovery method according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Example 1
Referring to fig. 1, an embodiment of the present invention provides a power failure warning and recovering method, including:
s100, after detecting that a fault position in a power state bit of a target power supply is set, pulling down a quick response pin of the target power supply; in the server, the BMC is generally connected with the power supply in a communication way, and the BMC polls and accesses all power supply status bits of the power supply of the server to acquire the power supply status and monitor and manage the power supply. The power supply has an idle output pin, such as a B21 pin, and the B21 pin of the power supply is defined as a quick response pin and is connected with the BMC; the default level of the quick response pin is high level, when the power supply fails, the corresponding failure bit in the power supply state bit is set, and after the failure bit of the power supply is set, the power supply pulls down the level of the quick response pin of the power supply.
S200, immediately reading the fault bit value in the power state bit of the target power supply in response to the low level of the quick response pin, and obtaining the setting condition of the fault bit of the target power supply. Specifically, after receiving the low-level signal sent by the target power supply quick response pin, the BMC interrupts the power supply state bit of the polling power supply, immediately reads the fault bit value in the power supply state bit of the target power supply, and obtains the setting condition of the fault bit of the target power supply.
S300, corresponding fault alarm information is sent out according to the setting condition of the fault position, and a corresponding fault clearing instruction is selected to be sent to a target power supply; in the implementation process, referring to fig. 2, S300 includes:
s301, preconfiguring faults represented by each fault position bit, and preconfiguring fault clearing instructions corresponding to the faults;
s302, determining the faults of the target power supply according to the fault position situation of the target power supply and faults represented by each fault position bit which is preconfigured, and generating corresponding fault alarm information; the fault alert information includes the identity of the target power source and the fault that the target power source has.
S303, selecting a corresponding fault clearing instruction according to the fault position situation of the target power supply, faults represented by each pre-configured fault position and the fault clearing instruction corresponding to the pre-configured faults, and sending the fault clearing instruction to the target power supply. In the implementation process, the fault of the target power supply is determined according to the fault position condition of the target power supply and faults represented by each fault position bit which is preconfigured, and the corresponding fault clearing instruction is selected and sent to the target power supply by utilizing the fault of the target power supply and the fault clearing instruction corresponding to the preconfigured fault.
S400, the target power supply restores the quick response pin to a high level after receiving the fault clearing instruction; in the specific implementation process, before receiving a fault clearing instruction issued by the BMC to restore the quick response pin to a high level, the target power supply restores the quick response pin to the high level and pulls down again after each time the target power supply detects a new fault, and immediately reads the value of a fault bit in a power state bit of the target power supply in response to the low level of the quick response pin to obtain the setting condition of the fault bit, so that the BMC can access the value of the power fault bit after the power supply fails, and obtain the condition of the fault position bit of the power supply.
In the specific implementation process, each power supply counts the set fault bit as a reference setting condition, compares whether the set fault bit recorded by the current set fault bit relative to the reference setting condition has the increase of the fault bit, and judges that a new fault occurs if the set fault bit has the increase of the fault bit; and when the value of the power failure bit is changed, the set failure bit is counted again to update the reference setting condition.
S500, after the target power supply executes the fault clearing instruction and meets the fault bit recovery condition, recovering the fault position bit; in the specific implementation process, part of faults of the power supply can influence the continuous operation of the power supply, so that the power supply is in a patched state, and even if the faults are solved through corresponding fault clearing instructions, the power supply can still normally operate after the restarting instructions restart the power supply. The other part of the power supply fails to work continuously, and the power supply still supplies power after failure.
For the above situation, referring to fig. 3, after the target power supply executes the fault clearing instruction and satisfies the fault bit recovery condition, recovering the fault location bit includes:
s501, after a target power supply executes a fault clearing instruction, detecting whether the target power supply is in a patched state; if yes, S502 is executed, otherwise S507 is executed,
s502, the target power supply detects whether the issued restart instruction is received, if so, S503 is executed, if not, S506 is executed,
s503, after the target power supply executes the restarting instruction and executes the restarting instruction, detecting whether the target power supply fault is eliminated, if so, executing S504, otherwise, executing S505;
and S504, the target power supply restores the corresponding fault position according to the restored fault.
S505, the fault bit value of the target power supply is reserved, and the restart failure of the target power supply is in a patched state.
S506, the fault bit value of the target power supply is reserved, and the target power supply is still in a patched state;
s507, whether the target power failure is eliminated is detected, if yes, S508 is executed, otherwise S509 is executed.
And S508, the target power supply restores the corresponding fault position according to the restored fault.
S509, the fault bit value is reserved.
S600, acquiring fault position bit recovery conditions and releasing corresponding fault alarm information according to the fault position bit recovery conditions. In the implementation process, referring to fig. 4, the obtaining the fault location bit recovery condition and releasing the corresponding fault alarm information according to the fault location bit recovery condition includes:
s601, the BMC accesses the fault bit value of the power status bit of each power supply by polling.
S602, comparing the setting condition of the fault bit of the power supply with the value of the fault bit obtained by polling to determine the recovery condition of the fault bit.
S603, the corresponding fault alarm information is released according to the recovered fault position bit.
Example 2
Referring to fig. 5, an embodiment of the present invention provides an apparatus for implementing a power failure alarm and recovery method, including: the fault detection module detects faults generated by the power supply;
the fault position setting module is used for setting corresponding fault positions according to the faults detected by the fault detection module and recovering the corresponding fault positions according to the recovered faults;
the quick response module is used for controlling the level of the quick response pin according to the setting condition of the fault position and the condition of receiving a fault clearing instruction; in the specific implementation process, when the fault bit setting module sets a fault bit, the quick response module controls the quick response pin to generate low level; and when the target power supply receives the fault clearing instruction, the quick response module controls the quick response pin to recover the high level. And during the period that the target power supply waits for the fault clearing instruction, the quick response module controls the quick response pin to recover high level and pull down again according to the setting of the fault bit by the fault bit setting module.
And the instruction execution module receives and executes the fault clearing instruction.
The device for realizing the power failure warning and recovering method further comprises the following steps:
the fault reading module is used for responding to the low level generated by the rapid response pin of the target power supply to read the fault bit value in the power state bit of the target power supply and obtaining the setting condition of the fault bit;
the fault alarm module is used for sending corresponding fault alarm information according to the setting condition of the fault position of the target power supply;
the alarm releasing module is used for releasing corresponding fault alarm information according to the recovery condition of the fault bit of the target power supply; in the specific implementation process, the fault bit value of each power supply is obtained through the fault bit in the fault bit of the power supply state bit of each power supply which is accessed through the polling access module; the alarm releasing module compares the fault position condition reflected by the fault position value of the target power supply obtained by polling with the fault position condition of the target power supply when the target power supply fails to obtain the fault position recovery condition of the target power supply, and releases the corresponding fault alarm information according to the recovered fault position.
And the fault processing module selects a corresponding fault clearing instruction according to the setting condition of the fault position of the target power supply and sends the fault clearing instruction to the target power supply.
Example 3
The embodiment of the invention provides a storage medium for realizing a power failure warning and recovering method, which stores at least one instruction, reads and executes the instruction to realize the power failure warning and recovering method.
When a fault is detected, the target power supply sets a corresponding fault position in power state bits of the target power supply, and after the fault position is detected, the quick response pin is controlled to generate low level; and immediately reading the fault bit value of the target power supply in response to the low level of the quick response pin, acquiring the fault position bit condition, generating corresponding fault alarm information according to the fault position bit condition, and selecting a corresponding fault clearing instruction according to the fault position bit condition and sending the fault clearing instruction to the target power supply. Therefore, the BMC is immediately informed of the fault of the target power supply, the BMC immediately generates corresponding fault alarm information according to the fault of the target power supply, and a corresponding fault clearing instruction is selected to issue so as to rapidly solve the fault of the target power supply. Compared with the mode of polling access to the power supply, the method has the advantages that the fault alarm and fault processing lag time is short, and the power supply safety of the server is fully ensured.
In the application, before the quick response pin is restored to the high level, after the target power supply detects a new fault, the target power supply restores the quick response pin to the high level and pulls down again, so that the BMC can be timely notified when the target power supply generates the new fault. The BMC is ensured to be capable of timely grasping all faults of the target power supply.
In the application, for faults affecting the continuous work of the power supply, after the faults are recovered, a restarting instruction can be timely sent to the power supply according to the patched state of the power supply, the corresponding power supply is timely restarted, and the power supply safety of the server is fully guaranteed.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A power failure warning and recovery method, comprising:
after detecting that the fault bit in the power state bit of the target power supply is set, pulling down the quick response pin of the target power supply;
immediately reading a fault bit value in a power state bit of a target power supply in response to the low level of the quick response pin, and acquiring the setting condition of the fault bit;
sending out corresponding fault alarm information according to the setting condition of the fault position, and selecting a corresponding fault clearing instruction to be sent to a target power supply;
the target power supply restores the quick response pin to a high level after receiving the fault clearing instruction; before the quick response pin is restored to the high level, after the target power supply detects a new fault, the target power supply restores the quick response pin to the high level and pulls down again, and the fault bit in the power state bit of the target power supply is immediately read in response to the low level of the quick response pin to acquire the setting condition of the fault bit;
after the target power supply executes the fault clearing instruction and meets the fault bit recovery condition, recovering the fault position bit;
and acquiring the recovery condition of the fault position bit of the target power supply and releasing the corresponding fault alarm information according to the recovery condition of the fault position bit.
2. The power failure warning and recovering method according to claim 1, wherein the failure bit set by the power is counted as a reference setting condition, whether the current failure bit set is increased relative to the reference setting condition, and if so, a new failure is judged to occur; and when the value of the fault bit is changed, the fault bit with the set power supply is counted to update the reference setting condition.
3. The power failure warning and recovery method according to claim 1, wherein after the target power supply executes the failure clearing instruction and satisfies the failure bit recovery condition, recovering the failure position bit includes:
after the target power supply executes the fault clearing instruction, detecting whether the target power supply is in a patched state;
if yes, the target power supply receives the issued restarting instruction, the target power supply executes the restarting instruction and after the restarting instruction is received, the target power supply fault is eliminated, the fault position bit is recovered by the target power supply, the fault position bit value of the target power supply is reserved if the fault of the target power supply is not eliminated, the fault position bit value is reserved if the restarting instruction is not received, and the target power supply is still in a patched state;
otherwise, the fault of the target power supply is eliminated, the fault position bit is recovered by the target power supply, and the fault position value is reserved if the fault of the target power supply is not eliminated.
4. The power failure warning and recovering method according to claim 1, wherein a failure represented by each failure position bit is preconfigured, and a failure clearing instruction corresponding to the failure is preconfigured;
determining the faults of the target power supply according to the fault position situation of the target power supply and faults represented by each preset fault position, and generating corresponding fault alarm information;
and selecting a corresponding fault clearing instruction according to the fault position condition of the target power supply, faults represented by each pre-configured fault position and the fault clearing instruction corresponding to the pre-configured faults, and sending the fault clearing instruction to the target power supply.
5. The power failure warning and recovering method according to claim 1, wherein the obtaining the target power failure location bit recovery condition and releasing the corresponding failure warning information according to the failure location bit recovery condition includes: the fault bit values of the power state bits of all the power supplies are accessed in a polling mode, the setting condition of the fault bit of the target power supply is compared with the fault bit condition reflected by the fault bit values obtained through polling to obtain the recovery condition of the fault bit of the target power supply, and the corresponding fault alarm information is released according to the recovered fault bit.
6. The power failure warning and restoration method according to claim 1, wherein the power status bits of the respective power supplies are accessed by polling, the power status bits of the polling power supplies are interrupted in response to a low level of the fast response pin of the target power supply, and the failed bit in the power status bits of the target power supply is immediately read.
7. An apparatus for implementing a power failure warning and recovery method, comprising: the fault detection module detects faults generated by the power supply;
the fault position setting module is used for setting corresponding fault positions according to the faults detected by the fault detection module and recovering the corresponding fault positions according to the recovered faults;
the quick response module controls the level of the quick response pin according to the setting condition of the fault bit and the condition that the instruction execution module receives the fault clearing instruction; comprising the following steps: after the fault position is set, the quick response pin of the target power supply is pulled down by the quick response module; after the instruction execution module receives the fault clearing instruction, the quick response module restores the quick response pin to a high level; before the quick response pin is restored to the high level, the quick response pin is restored to the high level and pulled down again after the fault detection module detects a new fault;
the instruction execution module receives and executes the fault clearing instruction;
the fault reading module is used for responding to the low level generated by the fast response pin of the target power supply to read fault bits in the power state bits of the target power supply;
the fault alarm module is used for sending corresponding fault alarm information according to the setting condition of the fault position of the target power supply;
the alarm releasing module is used for releasing corresponding fault alarm information according to the recovery condition of the fault bit of the target power supply;
and the fault processing module selects a corresponding fault clearing instruction according to the setting condition of the target power supply fault position and sends the fault clearing instruction to the instruction execution module.
8. The apparatus for implementing a power failure warning and recovery method according to claim 7, further comprising: the polling access module polls and accesses the fault bit of the power state bit of each power supply to acquire the fault bit value of each power supply, and obtains the fault bit recovery condition of the target power supply by comparing the fault bit condition reflected by the target power supply fault bit value acquired by polling with the fault bit condition of the target power supply when the target power supply fails.
9. A storage medium for implementing a power failure warning and recovery method, wherein the storage medium for implementing a power failure warning and recovery method stores at least one instruction, and a processor reads and executes the instruction to implement the power failure warning and recovery method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210072492.XA CN114442786B (en) | 2022-01-21 | 2022-01-21 | Power failure warning and recovering method, device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210072492.XA CN114442786B (en) | 2022-01-21 | 2022-01-21 | Power failure warning and recovering method, device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114442786A CN114442786A (en) | 2022-05-06 |
| CN114442786B true CN114442786B (en) | 2023-07-14 |
Family
ID=81367826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210072492.XA Active CN114442786B (en) | 2022-01-21 | 2022-01-21 | Power failure warning and recovering method, device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114442786B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955864A (en) * | 2016-04-26 | 2016-09-21 | 浪潮(北京)电子信息产业有限公司 | Power supply fault processing method, power supply module, monitoring management module and server |
| CN109284207A (en) * | 2018-08-30 | 2019-01-29 | 紫光华山信息技术有限公司 | Hard disc failure processing method, device, server and computer-readable medium |
| CN111966559A (en) * | 2020-07-14 | 2020-11-20 | 中国长城科技集团股份有限公司 | Fault recovery method and device, electronic equipment and storage medium |
| WO2021212943A1 (en) * | 2020-04-23 | 2021-10-28 | 苏州浪潮智能科技有限公司 | Server power supply maintenance method, apparatus and device, and medium |
-
2022
- 2022-01-21 CN CN202210072492.XA patent/CN114442786B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105955864A (en) * | 2016-04-26 | 2016-09-21 | 浪潮(北京)电子信息产业有限公司 | Power supply fault processing method, power supply module, monitoring management module and server |
| CN109284207A (en) * | 2018-08-30 | 2019-01-29 | 紫光华山信息技术有限公司 | Hard disc failure processing method, device, server and computer-readable medium |
| WO2021212943A1 (en) * | 2020-04-23 | 2021-10-28 | 苏州浪潮智能科技有限公司 | Server power supply maintenance method, apparatus and device, and medium |
| CN111966559A (en) * | 2020-07-14 | 2020-11-20 | 中国长城科技集团股份有限公司 | Fault recovery method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114442786A (en) | 2022-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101071392B (en) | Method and system for maintaining backup copies of firmware | |
| US20160239370A1 (en) | Rack having automatic recovery function and automatic recovery method for the same | |
| TW454128B (en) | Shared disk type multiple system | |
| KR20040047209A (en) | Method for automatically recovering computer system in network and recovering system for realizing the same | |
| CN111176952A (en) | Monitoring method, monitoring system and related device for I2C channel | |
| EP1837763A2 (en) | Protection of devices in a redundant configuration | |
| JP3653335B2 (en) | Computer management system | |
| US10721135B1 (en) | Edge computing system for monitoring and maintaining data center operations | |
| CN111737037A (en) | Substrate management control method, master-slave heterogeneous BMC control system and storage medium | |
| CN114442786B (en) | Power failure warning and recovering method, device and storage medium | |
| JP2012128573A (en) | Duplex system and building management system using the same | |
| EP0607660B1 (en) | Data processing system | |
| JPH10307635A (en) | Computer system and temperature monitoring method applied to the same system | |
| JP2001331330A (en) | Process abnormality detection and restoration system | |
| JP3190880B2 (en) | Standby system, standby method, and recording medium | |
| CN116069373A (en) | BMC firmware upgrading method, device and medium thereof | |
| WO2019041685A1 (en) | Apparatus unit control method, device and apparatus unit | |
| JP2001211232A (en) | Device management control method and system for remote access | |
| JPH10247962A (en) | Computer communication monitor system | |
| JP3794358B2 (en) | Power control method | |
| JP3480881B2 (en) | Remote monitoring device | |
| JP2009080780A (en) | Remote power supply controller | |
| JPH08329023A (en) | Parallel electronic computer system | |
| JP2001142361A (en) | Remote centralized control system | |
| JPH08147255A (en) | Fault monitoring system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |