CN114447142B - N-type TOPCON solar cell and manufacturing method thereof - Google Patents
N-type TOPCON solar cell and manufacturing method thereof Download PDFInfo
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- CN114447142B CN114447142B CN202111598644.1A CN202111598644A CN114447142B CN 114447142 B CN114447142 B CN 114447142B CN 202111598644 A CN202111598644 A CN 202111598644A CN 114447142 B CN114447142 B CN 114447142B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 95
- 230000005641 tunneling Effects 0.000 claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000005388 borosilicate glass Substances 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 70
- 229920005591 polysilicon Polymers 0.000 claims description 63
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 17
- 229910052796 boron Inorganic materials 0.000 claims description 17
- 239000002003 electrode paste Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 238000000137 annealing Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000007650 screen-printing Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000011267 electrode slurry Substances 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 4
- 238000005245 sintering Methods 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000002002 slurry Substances 0.000 claims description 2
- 230000003667 anti-reflective effect Effects 0.000 claims 6
- 230000000694 effects Effects 0.000 abstract description 16
- 238000006243 chemical reaction Methods 0.000 abstract description 5
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- 230000003071 parasitic effect Effects 0.000 description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
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- 229910021641 deionized water Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
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- 239000003513 alkali Substances 0.000 description 1
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- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1868—Passivation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
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Abstract
Provided are an N-type TOPCON solar cell and a method for manufacturing the same, comprising: forming a first tunneling passivation contact layer with a plurality of through holes on the front surface of an N-type silicon wafer substrate; forming a first borosilicate glass layer on the first tunneling passivation contact layer and in the via hole; forming a second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate; forming a first anti-reflection layer on the first borosilicate glass layer, and forming a second anti-reflection layer on the second tunneling passivation contact layer; a front electrode is formed on the first anti-reflection layer and a back electrode is formed on the second anti-reflection layer to obtain the N-type Topcon cell. According to the invention, the tunneling passivation contact structure is locally applied to the front surface of the battery and simultaneously applied to the back surface of the battery, so that excellent surface passivation effect is realized, and the photoelectric conversion efficiency of the battery is improved; and the tunneling passivation contact structure on the front surface of the battery can be manufactured according to the size and the graph which are actually required, so that the method is suitable for industrial production.
Description
Technical Field
The invention belongs to the technical field of solar cells, and particularly relates to an N-type TOPCON solar cell and a manufacturing method thereof.
Background
TOPCon (Tunnel Oxide Passivated Contact, tunnel oxide passivation contact) cell is a solar cell with surface passivation by using a tunnel passivation contact structure formed by a stack structure of a tunnel oxide layer and a doped polysilicon layer. The tunneling oxidation passivation contact structure is formed, so that majority carriers can penetrate through the oxide layer and have a blocking effect on minority carriers, the selective passing performance of carriers is effectively realized, the surface recombination and the metal recombination of the battery are greatly reduced, and an excellent surface passivation effect is realized. Therefore, the tunneling passivation contact structure has been applied to the fabrication of many high-efficiency crystalline silicon solar cells, for example, the tunneling passivation contact structure is applied to the cell structures such as PERC, PERT and IBC, thereby achieving higher cell conversion efficiency.
Because the doped polysilicon layer has stronger parasitic absorption and absorption effects on light, the conventional TOPCon battery can only apply the tunneling passivation contact structure to the back surface of the battery to reduce optical loss, and cannot be applied to the front surface of the battery, so that the improvement of the battery efficiency is limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an N-type TOPCON solar cell and a manufacturing method thereof.
According to an aspect of embodiments of the present invention, a method for manufacturing an N-type TOPCon solar cell includes: forming a first tunneling passivation contact layer with a plurality of through holes on the front surface of an N-type silicon wafer substrate; forming a first borosilicate glass layer on the first tunneling passivation contact layer and in the through hole; forming a second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate; forming a first anti-reflection layer on the first borosilicate glass layer, and forming a second anti-reflection layer on the second tunneling passivation contact layer; forming a front electrode on the first anti-reflection layer, which passes through the first anti-reflection layer and the first borosilicate glass layer and is contacted with the first tunneling passivation contact layer, and forming a back electrode on the second anti-reflection layer, which passes through the second anti-reflection layer and is contacted with the second tunneling passivation contact layer, so as to obtain the N-type Topcon battery.
In the method for manufacturing an N-type TOPCon solar cell provided in the above aspect, the forming a first tunneling passivation contact layer with a plurality of through holes on the front surface of the N-type silicon wafer substrate includes: sequentially depositing a first tunneling oxide layer and an intrinsic polycrystalline silicon layer which are stacked on the front surface of the N-type silicon wafer substrate; depositing a second borosilicate glass layer on the intrinsic polysilicon layer; pushing boron in the second borosilicate glass layer opposite to the region outside the through hole region into the intrinsic polysilicon layer opposite to the region outside the through hole region by using laser so that the intrinsic polysilicon layer opposite to the region outside the through hole region is formed as a first polysilicon layer; removing the second borosilicate glass layer; the intrinsic polysilicon layer and the first tunneling oxide layer opposite the via region are removed to form the plurality of vias.
In the method for fabricating an N-type TOPCon solar cell according to the above aspect, the first polysilicon layer and the first tunneling oxide layer opposite to the region outside the via region have a width of 50um to 200um, the first polysilicon layer is a boron doped polysilicon layer with a thickness of 100nm to 180nm, and the first tunneling oxide layer is a silicon dioxide layer with a thickness of 1nm to 3 nm.
In the method for manufacturing the N-type TOPCon solar cell provided in the above aspect, forming a first borosilicate glass layer on the first tunneling passivation contact layer and in the through hole includes: and depositing and forming the first borosilicate glass layer on the first tunneling passivation contact layer and in the through hole by using high-temperature diffusion equipment, wherein the deposition temperature is 800-900 ℃.
In the method for manufacturing an N-type TOPCon solar cell provided in the above aspect, forming a second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate includes: forming a second tunneling oxide layer and a second polysilicon layer which are stacked on the back surface of the N-type silicon wafer substrate by utilizing a plasma enhanced chemical vapor deposition method; the second tunneling oxide layer is a silicon dioxide layer with the thickness of 1-3 nm, and the second polysilicon layer is a phosphorus doped polysilicon layer with the thickness of 80-100 nm.
In the method for manufacturing an N-type TOPCon solar cell provided in the above aspect, after forming the second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate and before forming the first anti-reflection layer on the first borosilicate glass layer, the method further includes:
annealing the N-type silicon wafer substrate at an annealing temperature of 880-910 ℃ for 10-30 min to push boron in the first borosilicate glass layer and activate phosphorus in the second polysilicon layer;
and carrying out partial cleaning removal on the first borosilicate glass layer to keep the first borosilicate glass layer with the thickness of 5-10 nm.
In the method for fabricating an N-type TOPCon solar cell according to the above aspect, the boron doping concentration in the first polysilicon layer opposite to the region outside the via region is 5×10 19 cm -3 ～2×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of phosphorus in the second polysilicon layer is 1 multiplied by 10 21 cm -3 ～5×10 21 cm -3 。
In the method for manufacturing an N-type TOPCon solar cell provided in the above aspect, forming a first anti-reflection layer on the first borosilicate glass layer, and forming a second anti-reflection layer on the second tunneling passivation contact layer includes: and forming the first anti-reflection layer with the thickness of 70-80 nm on the first borosilicate glass layer by utilizing a plasma enhanced chemical vapor deposition method, and forming the second anti-reflection layer with the thickness of 70-80 nm on the second tunneling passivation contact layer.
In the method for manufacturing an N-type TOPCon solar cell provided in the above aspect, forming a front electrode on the first anti-reflection layer, which passes through the first anti-reflection layer and the first borosilicate glass layer and contacts the first tunnel passivation contact layer, and forming a back electrode on the second anti-reflection layer, which passes through the second anti-reflection layer and contacts the second tunnel passivation contact layer, the method comprising: screen printing front electrode paste on the first anti-reflection layer opposite to the region outside the through hole region, and screen printing back electrode paste on the second anti-reflection layer;
firing the front electrode paste through the first anti-reflection layer and the first borosilicate glass layer to form ohmic contact with the first tunneling passivation contact layer and firing the back electrode paste through the second anti-reflection layer to form ohmic contact with the second tunneling passivation contact layer to form the front electrode and the back electrode, respectively;
the front electrode slurry and the back electrode slurry are silver slurry, and the high-temperature sintering temperature is 700-760 ℃.
According to another aspect of the embodiment of the invention, the N-type TOPCon solar cell is manufactured by the manufacturing method.
The beneficial effects are that: according to the invention, the tunneling passivation contact layer with the plurality of through holes is formed on the front surface of the battery, so that the tunneling passivation contact structure is locally applied to the front surface of the battery, the front surface passivation effect of the battery is improved, the optical loss caused by the parasitic absorption effect of the doped polysilicon layer on the non-electrode area of the front surface of the battery is avoided, and meanwhile, the tunneling passivation contact structure is applied to the back surface of the battery, thereby realizing the excellent surface passivation effect of the battery and improving the photoelectric conversion efficiency of the TOPCO solar battery. In addition, compared with the traditional thermal diffusion mode, the method can only carry out whole-surface doping on the intrinsic polycrystalline silicon layer, the manufacturing method can manufacture the tunneling passivation contact structure on the front surface of the battery according to the size and the graph which are actually required, the shape and the size of the tunneling passivation contact structure are kept consistent with the shape and the size of the front electrode, the manufacturing method is simple and convenient, the manufacturing process flow of the battery is simplified, and the method is suitable for industrial manufacturing.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings in which:
fig. 1 is a flowchart of a method of fabricating an N-type TOPCon solar cell according to an embodiment of the present invention;
fig. 2 is a block diagram of an N-type TOPCon solar cell according to an embodiment of the present invention.
Detailed Description
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application so that others skilled in the art will be able to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein, the term "comprising" and variations thereof mean open-ended terms, meaning "including, but not limited to. The terms "based on", "in accordance with" and the like mean "based at least in part on", "in part in accordance with". The terms "one embodiment" and "an embodiment" mean "at least one embodiment. The term "another embodiment" means "at least one other embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other definitions, whether explicit or implicit, may be included below. Unless the context clearly indicates otherwise, the definition of a term is consistent throughout this specification.
As described in the background art, the doped polysilicon layer has a strong parasitic absorption and absorption effect on light, so that the conventional TOPCon battery can mostly only apply the tunneling passivation contact structure to the back surface of the battery to reduce optical loss, and cannot apply the tunneling passivation contact structure to the front surface of the battery, thereby limiting the improvement of the battery efficiency. Therefore, in order to solve the technical problems related to the TOPCON solar cell in the prior art, an N-type TOPCON solar cell and a manufacturing method thereof are provided according to an embodiment of the invention.
According to the manufacturing method, the tunneling passivation contact structure is applied to the back surface of the battery, and meanwhile, the tunneling passivation contact layer with a plurality of through holes is formed on the front surface of the battery, so that the tunneling passivation contact structure is locally applied to the front surface of the battery, the front passivation effect of the battery is improved, the parasitic absorption effect of the doped polysilicon layer on the non-electrode area of the front surface of the battery on light is solved, the optical loss is reduced, the excellent surface passivation effect of the battery is achieved, and the photoelectric conversion efficiency of the TOPCO solar battery is improved.
An N-type TOPCon solar cell and a method of fabricating the same according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 1 is a flowchart of a method of fabricating an N-type TOPCon solar cell according to an embodiment of the present invention.
Referring to fig. 1, in step S110, a first tunnel passivation contact layer 20 having a plurality of through holes is formed on the front surface of an N-type silicon wafer substrate 10, wherein the first tunnel passivation contact layer 20 includes a first tunnel oxide layer 201 and a first polysilicon layer 202 stacked.
Specifically, the step S110 includes:
the first step is to sequentially deposit and form a first tunneling oxide layer 201 and an intrinsic polysilicon layer on the front side of the N-type silicon wafer substrate 10 by using a low-pressure chemical vapor deposition method, wherein the growth temperature of the first tunneling oxide layer 201 is 500-700 ℃, and the growth temperature of the intrinsic polysilicon layer is 550-650 ℃.
The front and back surfaces of the N-type silicon wafer substrate 10 are the opposite and identical surfaces of the N-type silicon wafer substrate 10.
And a second step of depositing a second borosilicate glass layer on the intrinsic polycrystalline silicon layer by using high-temperature diffusion equipment.
And thirdly, pushing boron in the second borosilicate glass layer opposite to the region outside the through hole region into the intrinsic polysilicon layer opposite to the region outside the through hole region by using laser so that the intrinsic polysilicon layer opposite to the region outside the through hole region is formed as a first polysilicon layer 202.
In this embodiment, the spot size of the laser is (30-200) um (100-600) um, the power of the laser is 20W-80W, the frequency of the laser is greater than or equal to 15000Hz, and the pulse width of the laser is 4us.
Step four, cleaning and removing the second borosilicate glass layer by using the first solution to avoid the second borosilicate glass layer from affecting the subsequent etching process of the N-type silicon wafer substrate 10; wherein the first solution is HF solution with the mass percent concentration of 1% -3%.
Etching and removing the intrinsic polysilicon layer and the first tunneling oxide layer 201 opposite to the through hole area by using a second solution, and then flushing by using deionized water to form a plurality of through holes; wherein the second solution is a potassium hydroxide solution with the mass percent concentration of 5% -20%, and the etching time by using the second solution is 10 s-300 s.
In this embodiment, the width of the first polysilicon layer 202 and the first tunneling oxide layer 201 opposite to the region outside the via region is 50um to 200um, the first tunneling oxide layer 201 is a silicon dioxide layer with a thickness of 1nm to 3nm, and the first polysilicon layer 202 is a boron doped polysilicon layer with a thickness of 100nm to 180 nm.
The through hole region is opposite to the non-electrode region of the front surface of the battery, and the region outside the through hole region is opposite to the electrode region of the front surface of the battery, so that the first tunneling passivation contact layer 20 opposite to the region outside the through hole region is in contact with the electrode on the front surface of the battery; in addition, the first tunneling passivation contact layer 20 has a shape consistent with that of the electrode on the front surface of the subsequently formed battery, and is a plurality of parallel grid lines.
According to the manufacturing method, the first tunneling passivation contact layer 20 with the plurality of through holes is formed on the front surface of the N-type silicon wafer substrate 10, so that the tunneling passivation contact structure is locally applied to the front surface of the battery, the front surface passivation effect of the battery is improved, and optical loss caused by parasitic absorption effect of the doped polycrystalline silicon layer on the front surface of the battery opposite to the non-electrode area of the front surface of the battery is avoided; in addition, compared with the traditional thermal diffusion mode, the method can only carry out whole-surface doping on the intrinsic polycrystalline silicon layer, and the tunneling passivation contact structure can be formed on the front surface of the N-type silicon wafer substrate according to the size and the graph which are actually required, so that the shape and the size of the formed tunneling passivation contact structure are kept consistent with those of the electrode on the front surface of a battery which is formed subsequently.
In one example, before forming the first tunneling passivation contact layer 20 with the plurality of through holes on the front surface of the N-type silicon wafer substrate 10, the fabrication method further includes: the process of removing the damaged layer on the N-type silicon wafer substrate 10 specifically includes:
firstly, placing the N-type silicon wafer substrate 10 into H with the mass percentage concentration of 0.2% -1% 2 O 2 Cleaning and removing greasy dirt on the surface of the substrate in the solution;
secondly, polishing the N-type silicon wafer substrate 10 by using NaOH solution with the mass percent concentration of 5% -20%;
thirdly, neutralizing the NaOH solution remained on the surface of the N-type silicon wafer substrate 10 by utilizing a mixed solution of HCl solution and HF solution, and cleaning and removing metal ions and an oxide layer remained on the surface of the substrate; wherein, the mass percentage concentration of the HCl solution and the HF solution is 1% -5%, and the mixing ratio is 1:1, a step of;
and fourthly, washing the N-type silicon wafer substrate 10 by using deionized water, and performing heat drying treatment.
In step S120, forming a first borosilicate glass layer 30 on the first tunneling passivation contact layer 20 and in the via hole specifically includes: depositing the first borosilicate glass layer 30 on the first tunneling passivation contact layer 20 and in the via hole using a high temperature diffusion apparatus; wherein the deposition temperature is 800-900 ℃,
the first borosilicate glass layer 30 may effectively protect the front side of the N-type silicon wafer substrate 10 from corrosion during a subsequent back side etching process, and may provide a boron doping source for a subsequent annealing process step.
In one example, before forming the first borosilicate glass layer 30 on the front surface of the N-type silicon wafer substrate 10, the manufacturing method further includes: the texturing and cleaning treatment is performed on the N-type silicon wafer substrate 10, and specifically includes:
firstly, placing the N-type silicon wafer substrate 10 in KOH solution with the mass percentage concentration of 1% -3%, so as to perform surface texturing in the through hole area on the front surface of the N-type silicon wafer substrate 10 to form a textured structure;
then, cleaning and drying the N-type silicon wafer substrate 10 by utilizing a mixed solution of HCl solution and HF solution to remove impurities and metal ions remained on the surface of the N-type silicon wafer substrate 10; wherein, the mass percentage concentration of the HCl solution and the HF solution is 1% -5%, and the mixing ratio is 1:1.
in one example, after forming the first borosilicate glass layer 30 on the front surface of the N-type silicon wafer substrate 10, the manufacturing method further includes: the back etching treatment is performed on the N-type silicon wafer substrate 10, and specifically includes:
the first step, the N-type silicon wafer substrate 10 is placed in a single-sided etching device to etch the back of the substrate, and HF and HNO are utilized 3 Etching the back surface of the substrate 10 from a suede surface to a polished surface;
the boron doping caused by the edge of the N-type silicon wafer substrate 10 in the process of forming the first borosilicate glass layer 30 is removed by etching, so that the electric leakage of the edge of the battery is avoided; and the back surface of the substrate 10 is corroded to be a polished surface, so that the passivation effect of the back surface of the substrate 10 is improved.
And secondly, soaking and cleaning the N-type silicon wafer substrate 10 by using an alkali solution with the mass percent concentration of 5% -10% for 3-10 s so as to remove porous silicon on the back surface of the substrate 10, and then cleaning and drying by using deionized water.
In step S130, a second tunneling passivation contact layer 40 is formed on the back surface of the N-type silicon substrate 10, where the second tunneling passivation contact layer 40 includes a stacked second tunneling oxide layer 401 and a second polysilicon layer 402.
Specifically, the second tunneling oxide layer 401 having a thickness of 1nm to 3nm and the second polysilicon layer 402 having a thickness of 80nm to 100nm are formed on the back surface of the N-type silicon wafer substrate 10 by a plasma enhanced chemical vapor deposition method; wherein the second polysilicon layer 402 is a phosphorus doped polysilicon layer.
By sequentially forming the second tunneling oxide layer 401 and the second polysilicon layer 402, which are stacked, on the back surface of the N-type silicon wafer substrate 10, the tunneling passivation contact structure is applied to the back surface of the battery.
In this embodiment, after forming the stacked second tunneling oxide layer 401 and second polysilicon layer 402 on the back surface of the N-type silicon wafer substrate 10, the manufacturing method further includes:
the first step, annealing the N-type silicon wafer substrate 10 at an annealing temperature of 880-910 ℃ for 10-30 min to push boron in the first borosilicate glass layer 30 and activate phosphorus in the second polysilicon layer 402;
by performing annealing treatment, on one hand, boron in the first borosilicate glass layer 30 is pushed, so that not only the doping concentration of boron in the first polysilicon layer 202 can be increased, the contact resistance can be reduced, but also a PN junction can be formed in the through hole region with the textured structure; on the other hand, phosphorus within the second polysilicon layer 402 may be activated.
In one example, the boron doping concentration in the first polysilicon layer 202 is 5×10 after annealing 19 cm -3 ～2×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of boron in the PN junction formed in the through hole region is 1 multiplied by 10 19 cm -3 ～3×10 19 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of phosphorus in the second polysilicon layer 402 is 1×10 21 cm -3 ～5×10 21 cm -3 。
And secondly, partially cleaning and removing the first borosilicate glass layer 30 by using a hydrofluoric acid solution with the mass percentage concentration of 1% -3% so as to reserve the first borosilicate glass layer 30 with the thickness of 5-10 nm, wherein the reserved first borosilicate glass layer 30 can be used as a passivation layer.
In step S140, forming the first anti-reflection layer 50 on the first borosilicate glass layer 30 and forming the second anti-reflection layer 60 on the second tunneling passivation contact layer 40 specifically includes:
forming a first anti-reflection layer 50 having a thickness of 70nm to 80nm on the first borosilicate glass layer 30 by using a plasma enhanced chemical vapor deposition method, and forming the second anti-reflection layer 60 having a thickness of 70nm to 80nm on the second polysilicon layer 402 of the second tunneling passivation contact layer 40; wherein the first antireflection layer 50 and the second antireflection layer 60 are both silicon nitride antireflection layers, and refractive indexes of the first antireflection layer 50 and the second antireflection layer 60 are both 2.03-2.05.
In step S150, forming a front electrode 70 on the first anti-reflection layer 50, which is in contact with the first tunneling passivation contact layer 20 through the first anti-reflection layer 50 and the first borosilicate glass layer 30, and forming a back electrode 80 on the second anti-reflection layer 60, which is in contact with the second tunneling passivation contact layer 40 through the second anti-reflection layer 60, specifically includes:
a first step of screen-printing a front electrode paste on the first anti-reflection layer 50 opposite to the region outside the through-hole region, and screen-printing a rear electrode paste on the second anti-reflection layer 60;
in a second step, the front electrode paste is fired through the first anti-reflection layer 50 and the first borosilicate glass layer 30 by high temperature sintering to form ohmic contacts with the first polysilicon layer 202 of the first tunneling passivation contact layer 20, and the back electrode paste is fired through the second anti-reflection layer 60 to form ohmic contacts with the second polysilicon layer 402 of the second tunneling passivation contact layer 40 to form the front electrode 70 and the back electrode 80, respectively.
In one example, the front electrode paste and the back electrode paste are both silver paste, and the high temperature sintering temperature is 700 ℃ to 760 ℃.
By screen printing a front electrode paste on the first anti-reflection layer 50 opposite to the region outside the via region, it is ensured that the front electrode 70 is formed in contact with the first polysilicon layer 202 opposite to the region outside the via region.
Fig. 2 is a block diagram of an N-type TOPCon solar cell according to an embodiment of the present invention. The N-type TOPCon solar cell shown in fig. 2 is an N-type TOPCon solar cell manufactured by the manufacturing method described above (i.e., the manufacturing method shown in fig. 1). The N-type TOPCon solar cell described with reference to fig. 2 includes: the front electrode 70, the first anti-reflection layer 50, the first borosilicate glass layer 30, the first tunnel passivation contact layer 20 (including the first tunnel oxide layer 201 and the first polysilicon layer 202), the N-type silicon wafer substrate 10, the second tunnel passivation contact layer 40 (including the second tunnel oxide layer 401 and the second polysilicon layer 402), the second anti-reflection layer 60, and the back electrode 80.
Wherein the front electrode 70 forms an ohmic contact with the first polysilicon layer 202 through the first anti-reflection layer 50 and the first borosilicate glass layer 30; the back electrode 80 penetrates the second anti-reflection layer 60 to form an ohmic contact with the second polysilicon layer 402.
In summary, according to the TOPCon solar cell and the method for manufacturing the same according to the embodiments of the present invention, when the tunneling passivation contact structure is applied to the back surface of the cell, the tunneling passivation contact layer having a plurality of through holes is formed on the front surface of the cell, so that the tunneling passivation contact structure is locally applied to the front surface of the cell, which is not only beneficial to improving the passivation effect of the front surface of the cell, but also avoids the optical loss caused by the parasitic absorption effect of the doped polysilicon layer on the non-electrode area of the front surface of the cell, thereby realizing the excellent surface passivation effect of the cell and improving the photoelectric conversion efficiency of the TOPCon solar cell. In addition, compared with the traditional thermal diffusion mode, the method can only carry out whole-surface doping on the intrinsic polycrystalline silicon layer, and the manufacturing method can manufacture the tunneling passivation contact structure on the front surface of the battery according to the actual needed size and pattern, so that the tunneling passivation contact structure is consistent with the shape and size of the front electrode, and the manufacturing method is simple and convenient, is beneficial to simplifying the manufacturing process flow of the battery, and is suitable for industrial manufacturing.
The foregoing describes specific embodiments of the present invention. Other embodiments are within the scope of the following claims.
The terms "exemplary," "example," and the like, as used throughout this specification, mean "serving as an example, instance, or illustration," and do not mean "preferred" or "advantageous" over other embodiments. The detailed description includes specific details for the purpose of providing an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described embodiments.
The alternative implementation of the embodiment of the present invention has been described in detail above with reference to the accompanying drawings, but the embodiment of the present invention is not limited to the specific details of the foregoing implementation, and various simple modifications may be made to the technical solutions of the embodiment of the present invention within the scope of the technical concept of the embodiment of the present invention, and these simple modifications all fall within the protection scope of the embodiment of the present invention.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. The manufacturing method of the N-type Topcon battery is characterized by comprising the following steps of:
forming a first tunneling passivation contact layer with a plurality of through holes on the front surface of an N-type silicon wafer substrate;
forming a first borosilicate glass layer on the first tunneling passivation contact layer and in the through hole;
forming a second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate;
forming a first anti-reflection layer on the first borosilicate glass layer, and forming a second anti-reflection layer on the second tunneling passivation contact layer;
forming a front electrode on the first anti-reflection layer, which passes through the first anti-reflection layer and the first borosilicate glass layer and is in contact with the first tunneling passivation contact layer, and forming a back electrode on the second anti-reflection layer, which passes through the second anti-reflection layer and is in contact with the second tunneling passivation contact layer, so as to obtain the N-type Topcon battery;
the forming a first tunneling passivation contact layer with a plurality of through holes on the front surface of an N-type silicon wafer substrate comprises the following steps:
sequentially depositing a first tunneling oxide layer and an intrinsic polycrystalline silicon layer which are stacked on the front surface of the N-type silicon wafer substrate;
depositing a second borosilicate glass layer on the intrinsic polysilicon layer;
pushing boron in the second borosilicate glass layer opposite to the region outside the through hole region into the intrinsic polysilicon layer opposite to the region outside the through hole region by using laser so that the intrinsic polysilicon layer opposite to the region outside the through hole region is formed as a first polysilicon layer;
removing the second borosilicate glass layer;
the intrinsic polysilicon layer and the first tunneling oxide layer opposite the via region are removed to form the plurality of vias.
2. The method of claim 1, wherein the first polysilicon layer and the first tunnel oxide layer have a width of 50um to 200um opposite to the region outside the via region, and the first polysilicon layer is a boron doped polysilicon layer having a thickness of 100nm to 180nm, and the first tunnel oxide layer is a silicon dioxide layer having a thickness of 1nm to 3 nm.
3. The method of claim 1, wherein forming a first borosilicate glass layer over the first tunneling passivation contact layer and in the via hole comprises: and depositing and forming the first borosilicate glass layer on the first tunneling passivation contact layer and in the through hole by using high-temperature diffusion equipment, wherein the deposition temperature is 800-900 ℃.
4. The method of claim 1, wherein forming a second tunneling passivation contact layer on the back side of the N-type silicon wafer substrate comprises: forming a second tunneling oxide layer and a second polysilicon layer which are stacked on the back surface of the N-type silicon wafer substrate by utilizing a plasma enhanced chemical vapor deposition method;
the second tunneling oxide layer is a silicon dioxide layer with the thickness of 1-3 nm, and the second polysilicon layer is a phosphorus doped polysilicon layer with the thickness of 80-100 nm.
5. The method of claim 4, wherein after forming the second tunneling passivation contact layer on the back surface of the N-type silicon wafer substrate and before forming the first anti-reflection layer on the first borosilicate glass layer, the method further comprises:
annealing the N-type silicon wafer substrate at an annealing temperature of 880-910 ℃ for 10-30 min to push boron in the first borosilicate glass layer and activate phosphorus in the second polysilicon layer;
and carrying out partial cleaning removal on the first borosilicate glass layer to keep the first borosilicate glass layer with the thickness of 5-10 nm.
6. The method of claim 5, wherein the boron doping concentration in the first polysilicon layer opposite the region outside the via region is 5 x 10 19 cm -3 ～2×10 20 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The doping concentration of phosphorus in the second polysilicon layer is 1 multiplied by 10 21 cm -3 ～5×10 21 cm -3 。
7. The method of claim 1, wherein forming a first anti-reflective layer on the first borosilicate glass layer and a second anti-reflective layer on the second tunneling passivation contact layer comprises: and forming the first anti-reflection layer with the thickness of 70-80 nm on the first borosilicate glass layer by utilizing a plasma enhanced chemical vapor deposition method, and forming the second anti-reflection layer with the thickness of 70-80 nm on the second tunneling passivation contact layer.
8. The method of claim 1, wherein forming a front electrode on the first anti-reflective layer through the first anti-reflective layer and the first borosilicate glass layer in contact with the first tunneling passivation contact layer, and forming a back electrode on the second anti-reflective layer through the second anti-reflective layer in contact with the second tunneling passivation contact layer, comprises:
screen printing front electrode paste on the first anti-reflection layer opposite to the region outside the through hole region, and screen printing back electrode paste on the second anti-reflection layer;
firing the front electrode paste through the first anti-reflection layer and the first borosilicate glass layer to form ohmic contact with the first tunneling passivation contact layer, and firing the back electrode paste through the second anti-reflection layer to form ohmic contact with the second tunneling passivation contact layer to form the front electrode and the back electrode, respectively;
the front electrode slurry and the back electrode slurry are silver slurry, and the high-temperature sintering temperature is 700-760 ℃.
9. An N-type TOPCon solar cell fabricated by the fabrication method of any one of claims 1 to 8.
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| CN105226115A (en) * | 2015-09-07 | 2016-01-06 | 中国东方电气集团有限公司 | A kind of N-type crystal silicon battery and preparation method thereof |
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