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CN114420663A - Power semiconductor device and manufacturing method - Google Patents

Power semiconductor device and manufacturing method Download PDF

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Publication number
CN114420663A
CN114420663A CN202111606361.7A CN202111606361A CN114420663A CN 114420663 A CN114420663 A CN 114420663A CN 202111606361 A CN202111606361 A CN 202111606361A CN 114420663 A CN114420663 A CN 114420663A
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frame
electrode
chip
power
semiconductor device
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CN202111606361.7A
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Chinese (zh)
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晏新海
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Individual
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Priority to CN202111606361.7A priority Critical patent/CN114420663A/en
Publication of CN114420663A publication Critical patent/CN114420663A/en
Priority to CN202210698374.XA priority patent/CN114937651A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H01L29/78—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a power semiconductor device and a manufacturing method thereof.A source electrode or an emitting electrode of a chip is directly welded to a packaging frame, and the heat generated by the chip is conducted to the outside through the source electrode or the emitting electrode and a base of the packaging frame to dissipate the heat; and the welding areas of the frame and the source electrode or the emitter electrode and the grid electrode of the power chip are bulges. The protruding areas of the source electrode or the emitting electrode and the grid electrode of the frame are manufactured by punching and molding after the frame is extruded into strip-shaped copper strips, and the strip-shaped copper strips are correspondingly welded with the protruding areas of the source electrode or the emitting electrode and the grid electrode of the power chip. The power semiconductor device and the common packaged power semiconductor device have the same appearance and the same pin arrangement, but the thermal resistance is reduced by more than half, and the heat dissipation performance is obviously improved.

Description

Power semiconductor device and manufacturing method
Technical Field
The invention belongs to the technical field of power semiconductor device manufacturing, and particularly relates to a device structure and a manufacturing method for improving the performance of a power semiconductor device.
Background
The power semiconductor devices such as MOS and IGBT produced at present are generally 3 electrodes, that is, two electrodes of a front source electrode or an emitter electrode and a gate electrode, and one electrode of a back drain electrode or a collector electrode. The semiconductor industry has been gradually developing from low frequency and low power, and has gradually developed to high frequency and high power along with different requirements of device applications.
The design and manufacturing level of an early semiconductor device is low, so that the production process is mainly simple and easy to pursue, obviously one electrode is convenient to weld, two electrodes are easy to cause electrode short circuit, and the welding process is difficult to control, so that the drain electrode or the collector electrode of a chip, namely the back surface of the chip, is welded or adhered to an encapsulation frame in the traditional semiconductor device manufacturing process; the surface of the packaging frame is flat, and after the back surface of the chip is welded to the frame, the front surface connects the source electrode or the emitter electrode and the grid electrode to a frame lead in a wire bonding mode; in recent years, in order to cope with the increase in power of semiconductor devices, it is necessary to reduce the package resistance, and processes such as CLIP jumper have been also developed.
Although few manufacturers have recently proposed source bottom-mounted MOS products, that is, the source is connected to the package base, the package frame bottom plate is always flat no matter in the traditional forward mounting process, CLIP jumper package, or the newly developed source bottom-mounted process, and the source bottom-mounted is only a few MOS products with low power, low voltage, and chip package, and is not popularized in the category of high-voltage and high-power devices so far.
Therefore, how to reduce the thermal resistance of the high-power semiconductor device, improve the heat dissipation performance of the power semiconductor device, reduce the high-frequency radiation of the power device housing, and improve the switching frequency characteristic of the power device has become the problem to be solved by the semiconductor high-power device.
Disclosure of Invention
In order to solve the problems existing in the prior semiconductor device technology and meet the development trend of continuously increasing the power of the application market of the semiconductor technology, the invention adopts the following technical scheme:
a power semiconductor device, its chip source or emitter is welded to the encapsulation frame directly, the chip generates heat and radiates outwards through the conduction of the source or emitter through the encapsulation frame base; and the welding areas of the frame and the source electrode or the emitter electrode and the grid electrode of the power chip are bulges.
Referring to fig. 2, the copper bar is formed by extrusion, wherein the left part is used for manufacturing a heat dissipation base of a packaging frame, the right part is used for manufacturing a frame electric connection pin part, and the middle protruding part is used for manufacturing a source electrode or an emitter electrode and a welding area of a grid electrode.
The manufacturing method of the power semiconductor device comprises the following steps:
the source electrode or the emitter electrode and the grid electrode of the power chip are attached to the packaging frame in an aligned mode and used for welding the source electrode or the emitter electrode and the protruding portion of the grid electrode, soldering lugs or solder are prefabricated between the chip and the frame, the frame and the chip are welded through heating, and physical connection and electric connection are achieved; the main purpose of the frame projection is to ensure the minimum physical distance between the drain or collector on the back of the chip and the source or emitter of the device frame and ensure the voltage breakdown resistance of the device; the raised frame can ensure that overflowing solder flows to the frame at the lower part of the raised frame, and the short circuit phenomenon between electrodes caused by the transverse extension of the solder is avoided.
Due to the tin-sparse characteristic of the chip source electrode or emitter electrode and the passivation protective layer around the grid electrode, the tin-affinity characteristic of the frame copper material and the gravity action of the solder, the solder overflowing in the welding process of the device flows to the lower frame of the chip as shown in fig. 4(b), 4(c) and 4(d), and short circuit generated between electrodes of the power device in the welding process can be effectively avoided.
The protruding areas of the source electrode or the emitter electrode and the grid electrode of the frame are manufactured by punching and molding after the frame is extruded into a strip-shaped copper strip, and other modes such as chemical corrosion, mechanical cutting and the like can also process the required frame, but the cost is too high, so that the frame is not only used for researching and developing new products and trial-manufacturing samples, but also lacks of practical application value.
Firstly, manufacturing a strip copper material of a packaging frame in an extrusion mode, wherein the strip copper material is correspondingly welded with a source electrode or an emitting electrode of a power chip and a region of a grid electrode to be protruded; the height of the bump depends on multiple factors such as the application voltage requirement of the power device, the chip area (i.e. current or power consumption) requirement, the frame forming and punching process, and the copper material cost.
Specifically, the method comprises the following steps: the higher the breakdown voltage requirements of the source electrode or the emitter electrode and the drain electrode or the collector electrode are, the larger the projection height requirements are; the larger the chip area (or power), the more solder may overflow during soldering, and the larger the bump height requirement; the larger the height of the bulge is, the more copper material is consumed, which will cause cost rise; meanwhile, the larger the height of the protrusion is, the more difficult the mechanical punching is, the more the production difficulty is increased, and even the space between the frame source electrode and the grid electrode is increased, the actual welding area of the source electrode is reduced, and the corresponding increase of the packaging thermal resistance is caused; therefore, the height of the frame protrusion needs to be determined by comprehensively considering the above multiple factors, and the height of the protrusion is generally 0.1-1 mm.
In the manufacturing process of the packaging frame, a welding source electrode or an emitting electrode and a grid electrode protruding area are reserved, and other parts such as the parts shown in the figures 3(a) and 3(b) are removed in a mechanical punching mode, so that the minimum insulation distance between a chip drain electrode or a chip collector electrode and the packaging frame source electrode or the emitting electrode is ensured; the other parts (such as the right electrode lead part, the left bolt fixing hole position and the like) are punched and bent to form a packaging frame, and the surface treatment of the packaging frame is consistent with the conventional semiconductor device packaging method.
The power semiconductor device of the scheme can be a silicon-based, silicon carbide, gallium nitride or other compound semiconductor MOS, IGBT and other high-power devices; the packaging form can be a standard packaging form commonly applied TO TO-220, TO-263, TO-247 and the like, a module or other custom non-standard packaging structures.
According to the technical scheme, the overall production process is similar to the plastic package process of a common power semiconductor device, and the difference is as follows:
when the frame is extruded and formed, the source electrode or the emitting electrode and the grid electrode of the welding chip are protruded, and the protrusion height is determined according to multiple factors such as the application voltage requirement of a power device, the chip area (power consumption of the power device), the frame forming stamping process, the copper material cost and the like. The higher the breakdown voltage requirements of the source electrode or the emitter electrode and the drain electrode or the collector electrode are, the larger the projection height requirements are; the larger the chip area is, the more the solder overflowing in the welding process is, and the larger the requirement on the bump height is; the height of the bulge is large, the consumption of copper materials is high, the cost is increased, and the larger the height of the bulge is, the more difficult the mechanical punching is; therefore, the frame protrusion height needs to be determined by comprehensively considering various factors.
In order to avoid the short circuit phenomenon between chip electrodes caused by solder, the raised parts of the peripheral frame of the chip are removed in the frame forming process by means of processing modes such as punching and the like in the frame manufacturing process;
the front surface of the chip is provided with a source electrode or an emitter electrode and a grid electrode metal area which are used for electric connection, and the metal area is attached to a corresponding welding convex area of the frame, which is different from the condition that a drain electrode or a collector electrode of a common semiconductor device is welded to a frame base;
in the process of loading the chip, a chip turnover processing step is added, the back of a common semiconductor device is welded to the frame, and the common semiconductor device is only required to be taken out and then placed on the frame; the manufacturing method of the technology is to attach the front surface of the chip to the frame, and the operation step of turning over the chip is needed to be added;
different plating treatments are required to be carried out on the source electrode and the grid electrode metal layer on the front surface of the chip, so that the source electrode, the grid electrode and the frame can be conveniently welded; the source electrode and the grid electrode of the common plastic package semiconductor device are electrically connected through routing, the front surface of the chip is generally made of metal aluminum, the source electrode and the grid electrode are welded after being inverted, and the front surface of the chip needs to be electroplated with copper, a silver or silver alloy layer, a gold or gold alloy layer or other coatings suitable for being welded with a copper frame. And the drain metal layer selects a proper metal material according to the specific process requirements of jumper wires or aluminum strips.
Other manufacturing techniques and requirements such as wire bonding, aluminum tape bonding, or jumper wire connection of the chip and the frame lead, frame surface treatment, plastic molding and the like are consistent with those of the manufacture of common power semiconductor devices.
Advantageous effects
1. The scheme of the invention is very remarkable for the performance improvement of a semiconductor power device, and taking N-channel MOS as an example, as the emitting electrodes are usually connected with low potential, even part of application places are grounded, the high-frequency radiation of the shell of the power device can be reduced; in the application of grounding the source electrode, the emitter of the device is directly connected with a radiator and is grounded, and the parasitic capacitance effect of the radiator is eliminated; the practical effects of improving the heat dissipation performance, the current carrying capacity, the switching frequency characteristic and the like of the power semiconductor device can be achieved.
2. The scheme of the invention is convenient for welding the frame and the chip, avoids welding short circuit between the source electrode or the emitter electrode and the grid electrode, between the source electrode or the emitter electrode and the drain electrode or the collector electrode, and between the grid electrode and the drain electrode or the collector electrode caused by overflowing solder, reduces the production difficulty and improves the yield;
3. the scheme of the invention increases the physical distance between the drain electrode or the collector electrode of the chip and the source electrode or the emitter electrode of the packaging base, improves the voltage breakdown resistance of the power device, and meets the application of the flip-chip technology of the power device in the fields of high-voltage MOS, IGBT and the like.
4. The power semiconductor device produced by the scheme of the invention has the same appearance and the same pin arrangement as the common packaged power semiconductor device, but the thermal resistance is reduced by more than half, and the heat dissipation performance is obviously improved.
Drawings
FIG. 1 is a schematic diagram of a chip structure according to the present invention;
FIG. 2 is a schematic view of the extruded copper bar structure of the present invention;
FIG. 3(a) is a schematic structural diagram of a copper frame of a power semiconductor device according to the present invention;
FIG. 3(b) is an enlarged view of a portion of the frame structure of the present invention;
FIG. 4(a) is a schematic diagram of a die attach, bonding process of the present invention;
FIG. 4(b), FIG. 4(c), FIG. 4(d) are enlarged detail views of the source bonding area and the gate bonding area, respectively, according to the present invention;
fig. 5 is a structural diagram of a plastic-sealed finished product according to an embodiment of the invention.
In fig. 1-5, MOS is taken as an example to illustrate:
1-power chip, 11-power chip source electrode metal, 111-power chip source electrode solder layer, 12-power chip drain electrode metal, 13-power chip grid electrode metal, 131-power chip grid electrode solder layer and 14-power chip passivation layer protection area;
2-copper frame, 21-copper frame source, or source lead, 211-copper frame and chip source metal pad, 22-copper frame drain, or drain lead, 23-copper frame gate, or gate lead, 231-copper frame and chip gate metal pad. The left part of the 2L-copper frame is used for manufacturing a device packaging base and is responsible for transmitting the heat generated by the power chip to the radiator; the convex surface of the middle part of the 2M-copper frame is used for manufacturing a convex welding platform for welding the source electrode and the grid electrode of the chip; and the right part of the 2R-copper frame is used for manufacturing electrode pins of the device.
Detailed Description
The technical solution is specifically described below with reference to the accompanying drawings by taking a power MOS device as an example.
Designing and manufacturing a power chip as shown in figure 1, designing and manufacturing a power semiconductor device chip 1 according to the application parameter requirements of a power device; the power chip 1 comprises a source electrode 11, a grid electrode 13, a passivation protective layer 14 and a drain electrode 12, wherein the source electrode 11 and the grid electrode 13 are arranged on the front surface of the chip;
the power chip source electrode 11 is directly welded to the packaging frame 2, is attached to the protruding packaging copper frame and the chip source electrode metal welding area 211, forms source electrode connection after welding, and the chip 1 generates heat and conducts the heat through the source electrode 11 and the packaging frame 2 to radiate the heat outwards;
the drain electrode 12 of the power chip is welded to the packaging frame 2 through a routing wire or a CLIP jumper wire and is connected with a drain electrode pin 22 of the packaging copper frame;
the power chip grid 13 is directly welded to the packaging frame 2, is attached to the protruding packaging copper frame and the chip grid metal welding area 231, and forms grid connection after welding;
the power chip of the embodiment is an MOS device with a high-voltage planar structure, the external dimension is 4.5mm x 3.1mm, the thickness is 150um, the designed breakdown voltage is 650V, and the designed current is 10A;
the specific frame manufacturing method comprises the following steps:
in the embodiment, a standard TO-220 iron package is adopted, metal copper is extruded into a copper bar as shown in fig. 2, and the left part 2L of the copper bar is used for manufacturing a heat dissipation base of a power device, so that the connection between the device and a heat sink is born in practical application, and the heat generated by the power chip 1 is conducted TO the heat sink; the right part 2R is used for manufacturing electrode pins, namely a source electrode pin 21, a drain electrode pin 22 and a grid electrode pin 23, and the power devices and the application circuits are electrically connected in a one-to-one correspondence mode in practical application; the upward protruding part of the middle area 2M is used for processing a copper frame and chip source metal welding area 211 and a copper frame and chip gate metal welding area 231, and the copper frame and chip gate metal welding area 231 are respectively welded with the source electrode 11 and the gate electrode 13 of the chip correspondingly, so that the source electrode and the gate electrode of the power device are connected.
As shown in fig. 3, the copper strip extruded and formed according to fig. 2 is mechanically punched and bent to form a formal packaging copper frame 2; the right portion 2R is punched and bent to form a device source lead 21, a drain lead 22, and a gate lead 23.
As shown in fig. 3(a) and 3(b), for the frame convex portion, other convex regions on the periphery of the chip 1 and the intermediate regions between the source or emitter 11 and the gate 13 are removed by mechanical punching except for the remaining source or emitter 11 pad 211 and the gate pad 231.
Regarding the height of the frame projection: the higher the source-drain breakdown voltage requirement, the greater its bump height requirement in order to meet a sufficient minimum physical distance between the drain and the source; the larger the power is, the larger the required chip area is, the more the solder overflows in the welding process is, the more the short circuit between the electrodes is easily caused, and therefore, in order to avoid the short circuit of the electrodes as much as possible, the larger the requirement on the projection height is; on the other hand, the height of the bulge is large, the consumption of copper materials is high, and the cost rises more; in addition, the larger the height of the bump is, the thicker the thickness of the frame is, the more difficult the mechanical punching is, the more the production difficulty is increased, even the space between the source electrode and the grid electrode of the frame needs to be increased, the actual welding area of the source electrode is reduced, and the corresponding increase of the packaging thermal resistance is caused; therefore, the height of the frame bump is determined by comprehensively considering the above multiple factors, the height of the frame bump is 0.3mm, and the distance between the frame source and the frame gate is 0.6 mm.
After the chip design and manufacture and the special frame preparation are completed, the packaging and testing operations similar to those of the common power semiconductor device are followed, and the specific steps are briefly described as follows:
1. tin coating: printing solder paste on the corresponding parts of the copper frame source 21 and the grid 23, or placing soldering lugs or solder in advance;
2. core feeding: as shown in fig. 4(a), unlike a general power semiconductor device manufacturing method; turning over the power chip 1 and correspondingly attaching the power chip to the copper frame 2; as shown in fig. 4(a), the source 11 and the gate 13 on the front surface of the chip 1 are aligned and attached to the source 211 and the gate 231 in the frame protrusion area; the front mounting process only needs to place the chip on the frame without a turn-over process because the back of the chip, namely the drain electrode, is welded on the packaging frame.
3. And (3) drain electrode jumper: placing an electric connection sheet and a proper amount of solder paste between the chip drain electrode 12 and the frame drain electrode 22 pin;
4. heating and welding: as shown in fig. 4(a), after the source electrode 11 and the gate electrode 13 of the power chip 1 and the source electrode land 211 and the gate electrode land 231 of the frame are bonded in alignment, the bonded chip and the frame are heated and soldered to bond the chip 1 and the frame 2 together; simultaneously forming electrical connections between the chip 1 and the frame 2, the chip source 11 and the frame 21, the chip gate 13 and the frame 23, and the chip drain 12 and the frame 22;
the chip drain 12 and the frame 22 may be electrically connected by wire bonding after the source and gate bonding is completed.
As shown in fig. 4(b), 4(c) and 4(d) illustrating enlarged detail of the soldering, solder overflowing between the chip 1 and the frame 2 during soldering flows to the lower copper frame 2 due to the tin-phobic property of the passivation layer 14 of the chip 1, the tin-philic property of the copper metal of the copper frame 2, and the gravity of the solder, rather than laterally extending across the passivation layer 14 to short the source electrode 11 and the gate electrode 13, and further, not laterally extending across the passivation layer 14 and upwardly to short the source electrode 11 and the drain electrode 12 or between the gate electrode 13 and the drain electrode 12.
5. Cleaning welding residues: similar to the packaging process of a common power device, welding residues are cleaned and cleaned after heating welding, and the reliability and the service life of the device are improved.
6. Plastic package molding: as shown in fig. 5, this case is a standard TO-220 iron package, and is not a final product after processes such as chip mounting and welding, and needs TO be protected by plastic package. The power semiconductor device product manufactured by the technical scheme shown in fig. 5 has the same shape and the same pin arrangement as the common packaged power semiconductor device.
7. And (3) testing: and testing and screening the prepared products according to the technical requirements, and removing unqualified products to finish the formal products required by the invention.

Claims (9)

1. A power semiconductor device is characterized in that a source electrode or an emitter electrode of a power chip is directly welded to a packaging frame, and the power chip conducts heat to the outside through the source electrode or the emitter electrode and the packaging frame to dissipate heat;
the packaging frame is provided with a bulge in a region welded with the source electrode or the emitter electrode of the power chip and the grid electrode lead-out metal layer.
2. The power semiconductor device as claimed in claim 1, wherein the package frame is formed by extruding copper material into a strip-shaped copper material, and the strip-shaped copper material corresponds to a bump of a region where a source or an emitter of the power chip and a gate are bonded.
3. The power semiconductor device of claim 1, wherein the raised region bump height is determined by the power semiconductor device application voltage requirements, chip area requirements, frame forming die cut process, and copper material cost.
4. The power semiconductor device of claim 1, wherein said power chip is a silicon-based or compound semiconductor MOS, IGBT high power device.
5. The power semiconductor device according to claim 4, wherein the compound is silicon carbide or gallium nitride.
6. The power semiconductor device of claim 1, wherein said package is in the form of a standard package commonly used for TO-220, TO-263, TO-247, and a module, or other custom non-standard package structure.
7. The method for manufacturing a power semiconductor device according to claim 1, wherein the source or emitter and gate bump regions are reserved for a process of extruding the frame into a strip-shaped copper strip, and the excess bump regions are removed by punching at a later stage to form a shape corresponding to the source or emitter and gate bonding metal regions of the power chip.
8. The manufacturing method of claim 7, wherein the front surface of the power chip is attached to the frame, and the metal layers of the source electrode and the gate electrode on the front surface of the power chip need to be plated to facilitate the welding of the source electrode and the gate electrode of the power chip with the copper frame.
9. The method of claim 8 wherein the additional plating of the power chip front side source and gate metals is copper, silver or silver alloy, gold or gold alloy, or other metal layers that facilitate soldering to the copper frame.
CN202111606361.7A 2021-12-26 2021-12-26 Power semiconductor device and manufacturing method Withdrawn CN114420663A (en)

Priority Applications (2)

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CN202111606361.7A CN114420663A (en) 2021-12-26 2021-12-26 Power semiconductor device and manufacturing method
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CN114937605A (en) * 2022-05-31 2022-08-23 浙江禾芯集成电路有限公司 Packaging method of packaging structure of vertical MOSFET chip

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937605A (en) * 2022-05-31 2022-08-23 浙江禾芯集成电路有限公司 Packaging method of packaging structure of vertical MOSFET chip

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