CN114428426A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN114428426A CN114428426A CN202210171718.1A CN202210171718A CN114428426A CN 114428426 A CN114428426 A CN 114428426A CN 202210171718 A CN202210171718 A CN 202210171718A CN 114428426 A CN114428426 A CN 114428426A
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- 239000000758 substrate Substances 0.000 title claims abstract description 133
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 239000012780 transparent material Substances 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 188
- 238000002161 passivation Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 229920000178 Acrylic resin Polymers 0.000 claims description 4
- 239000004925 Acrylic resin Substances 0.000 claims description 4
- 239000004793 Polystyrene Substances 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 claims description 4
- 229920000515 polycarbonate Polymers 0.000 claims description 4
- 239000004417 polycarbonate Substances 0.000 claims description 4
- 229920002223 polystyrene Polymers 0.000 claims description 4
- -1 polytetrafluoroethylene Polymers 0.000 claims description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 claims description 4
- 239000004810 polytetrafluoroethylene Substances 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- 239000011787 zinc oxide Substances 0.000 claims description 4
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 claims description 3
- 229910000423 chromium oxide Inorganic materials 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 abstract description 14
- 239000010408 film Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 238000002834 transmittance Methods 0.000 abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910010272 inorganic material Inorganic materials 0.000 description 3
- 239000011147 inorganic material Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
- G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Geometry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the application provides an array substrate and a display panel; the array substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprises a common electrode made of transparent materials and a pixel electrode arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate, wherein in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode; according to the array substrate, the common electrode in each sub-pixel unit is made of the transparent material, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is located in the common electrode, so that the common electrode forming the storage capacitor completely covers the area, far away from the thin film transistor, of the array substrate, the grid metal film layer wiring design adopted by the common electrode is replaced, the aperture opening ratio of the sub-pixel units is improved, and the transmittance of the array substrate is further improved.
Description
Technical Field
The application relates to the field of display, in particular to an array substrate and a display panel.
Background
In terminal product innovation field, transparent screen possesses a place in fields such as outdoor advertisement, glass curtain wall with its brand-new show mode, frivolous appearance design and high-end science and technology atmosphere, has brought unprecedented visual experience and brand-new application experience for everyone. Liquid Crystal Display (LCD), Light-Emitting Diode (LED) transparent screens, and Organic Light-Emitting Diode (Organic LED) transparent screens are used, and are rapidly becoming new pets of advertisers and new trends of new media development. However, the transparent display screen has a low aperture ratio of the back plate due to the problem of metal wiring of the driving circuit, which results in low display transparency and low overall display brightness, and thus, the appearance of people is poor.
Therefore, an array substrate and a display panel are needed to solve the above technical problems.
Disclosure of Invention
The embodiment of the application provides an array substrate and a display panel, which can solve the technical problem that the aperture opening ratio of a backboard of a current transparent display screen is low.
The embodiment of the application provides an array substrate, which comprises a plurality of sub-pixel units; each sub-pixel unit comprises a common electrode made of transparent materials and a pixel electrode arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
in a top view direction of the array substrate, an orthographic projection of the pixel electrode on the common electrode is located in the common electrode.
Optionally, in some embodiments of the present application, the common electrodes in two adjacent sub-pixel units are continuous and electrically connected.
Optionally, in some embodiments of the present application, each of the sub-pixel units includes a gate layer and a source drain layer disposed on the gate layer;
the common electrode is arranged with the grid layer and the source drain layer.
Optionally, in some embodiments of the present application, the array substrate further includes an organic insulating layer disposed on the source drain layer, the common electrode disposed on the organic insulating layer, a passivation layer disposed on the common electrode, and the pixel electrode disposed on the passivation layer;
wherein the dielectric constant of the passivation layer is greater than the dielectric constant of the organic insulating layer.
Optionally, in some embodiments of the present application, the material of the passivation layer is at least one of silicon nitride, silicon oxide, and silicon oxynitride, and the material of the organic insulating layer is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate, and polystyrene.
Optionally, in some embodiments of the present application, a ratio of the thickness of the organic insulating layer to the thickness of the passivation layer is greater than or equal to 2.
Optionally, in some embodiments of the present application, the materials of the common electrode and the pixel electrode each include at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
Optionally, in some embodiments of the present application, the array substrate further includes a gate insulating layer disposed on the substrate and covering the gate layer, an active layer disposed on the gate insulating layer and corresponding to the gate layer, and the source drain layer disposed on the gate insulating layer and electrically connected to the active layer.
Optionally, in some embodiments of the present application, the array substrate further includes a light shielding layer disposed on the substrate, a buffer layer disposed on the substrate and covering the light shielding layer, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a gate insulating layer disposed on the gate insulating layer, a gate layer disposed on the buffer layer and completely covering the active layer, the gate insulating layer, an interlayer insulating layer of the gate layer, and a source drain layer disposed on the interlayer insulating layer.
Correspondingly, the embodiment of the application also provides a display panel, which comprises an array substrate, an opposite substrate and a liquid crystal layer arranged between the array substrate and the opposite substrate, wherein the array substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprises a common electrode made of a transparent material and a pixel electrode arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
in a top view direction of the array substrate, an orthographic projection of the pixel electrode on the common electrode is located in the common electrode.
The embodiment of the application provides an array substrate and a display panel; the array substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprises a common electrode made of a transparent material and a pixel electrode arranged on one side of the common electrode, the common electrode and the pixel electrode form a storage capacitor of the array substrate, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is positioned in the common electrode; according to the array substrate, the common electrode in each sub-pixel unit is made of a transparent material, and in the top view direction of the array substrate, the orthographic projection of the pixel electrode on the common electrode is located in the common electrode, so that the common electrode forming the storage capacitor completely covers the area, far away from the thin film transistor, of the array substrate, the grid metal film layer routing design adopted by the common electrode is replaced, the aperture opening ratio of the sub-pixel units is improved, and the transmittance of the array substrate is further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a first cross-sectional structure of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic plan view illustrating a common electrode in an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic cross-sectional view of a second cross-sectional structure of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The technical problem that the aperture opening ratio of the back plate of the current transparent display screen is low can be solved.
The technical solution of the present application will now be described with reference to specific embodiments.
Referring to fig. 1 to 3, an array substrate 10 is provided in an embodiment of the present application, where the array substrate 10 includes a plurality of sub-pixel units 20; each sub-pixel unit 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed on one side of the common electrode 108, and the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10;
in a top view direction of the array substrate 10, an orthogonal projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
The array substrate 10 provided by the embodiment of the application is through making each common electrode 108 in the sub-pixel unit 20 of transparent material, and in the top view direction of the array substrate 10, the pixel electrode 110 is in the orthographic projection on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 which forms a storage capacitor completely covers the area far away from the thin film transistor on the array substrate 10, the gate metal film layer routing design adopted by the common electrode 108 is replaced, the aperture ratio of the sub-pixel unit 20 is further improved, and the transmittance of the array substrate 10 is further improved.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Fig. 1 is a schematic view of a first cross-sectional structure of an array substrate 10 according to an embodiment of the present disclosure; the array substrate 10 includes a plurality of thin film transistors, and each of the thin film transistors is of a back channel etching type structure.
Specifically, the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed on one side of the common electrode 108, and the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10;
in a top view direction of the array substrate 10, an orthogonal projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
In the embodiment of the present application, the array substrate 10 includes a substrate 101, a gate layer 102 disposed on the substrate 101, a gate insulating layer 103 disposed on the substrate 101 and completely covering the gate layer 102, an active layer 104 disposed on the gate insulating layer 103, a source drain layer 105 disposed on the gate insulating layer 103 and covering part of the active layer 104, a first inorganic insulating layer 106 disposed on the gate insulating layer 103 and covering part of the source drain layer 105 and part of the active layer 104, an organic insulating layer 107 disposed on the first inorganic insulating layer 106, a common electrode 108 disposed on the organic insulating layer 107, a passivation layer 109 disposed on the organic insulating layer 107 and completely covering the common electrode 108, and a pixel electrode 110 disposed on the passivation layer 109;
wherein, in a top view direction of the array substrate 10, an orthographic projection of the active layer 104 on the substrate 101 is located in the gate layer 102.
In the embodiment of the present application, the source/drain layer 105 includes a source 1051 and a drain 1052 separated from the source 1051, the source 1051 is electrically connected to one end of the active layer, and the drain 1052 is further electrically connected to the other end of the active layer 104.
Specifically, the passivation layer 109 has an opening 1091, and the depth of the opening 1091 is greater than the thickness of the passivation layer 109; the pixel electrode 110 completely covers the opening 1091, and is directly electrically connected to the drain 1052 of the source/drain layer 105 at the bottom of the opening 1091.
In the embodiment of the present application, the substrate 101 may be a glass substrate or a polyimide film, and the substrate 101 may also be formed of one or more polyimide films. The material of the gate layer 102 may be a metal material with excellent conductivity, such as molybdenum, copper, and aluminum; the material of the gate insulating layer 103 may be one or more of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon dioxide, or the like, so as to perform an insulating protection function. The material of the active layer 104 may be a metal oxide semiconductor material such as indium gallium zinc oxide or indium zinc oxide. The material of the source drain layer 105 may be a metal material with excellent conductivity, such as molybdenum, copper, and aluminum.
In the embodiment of the present invention, the material of the first inorganic insulating layer 106 may be one or more of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride, which are used for isolating water and oxygen and playing a role in insulating and protecting other functional film layers; the material of the organic insulating layer 107 is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate, and polystyrene.
In the embodiment of the present application, the material of the passivation layer 109 is at least one of silicon nitride, silicon oxide and silicon oxynitride, and the material of the organic insulating layer 107 is at least one of acrylic resin, polytetrafluoroethylene, polycarbonate and polystyrene; the materials of the common electrode 108 and the pixel electrode 110 each include at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
In the embodiment of the present application, the common electrode 108 is disposed in different layers with the gate layer 102 and the source/drain layer 105. Further, the common electrode 108 is disposed on the organic insulating layer 107; this arrangement makes it possible to make the thickness of the insulating material (the passivation layer 109 in the embodiment of the present application) present in the storage capacitor formed by the common electrode 108 and the pixel electrode 110 within a reasonable range.
In the embodiment of the present application, the dielectric constant of the passivation layer 109 is greater than that of the organic insulating layer 107; this arrangement can increase the storage capacity of the storage capacitor.
In the embodiment of the present application, a ratio of the thickness of the organic insulating layer 107 to the thickness of the passivation layer 109 is greater than or equal to 2. The passivation layer 109 is preferably 2000 angstroms, and the organic insulating layer 107 is preferably 5000 angstroms in thickness.
Further, since the common electrode 108 is disposed on the organic insulating layer 107, the organic insulating layer 107 may serve as a planarization layer to planarize a film layer of the common electrode 108.
Furthermore, since the ratio of the thickness of the organic insulating layer 107 to the thickness of the passivation layer 109 is greater than or equal to 2, the distance between the pixel electrode 110 and the data line 22 disposed in the same layer as the source/drain layer 105 is increased, and the influence of the parasitic capacitance (Cpd) generated between the pixel electrode 110 and the data line 22 on signal transmission is reduced; meanwhile, the thickness distance between the common electrode 108 and the scanning line 21 arranged on the same layer of the gate layer 102 is increased, and the influence of parasitic capacitance (Cpg) generated between the common electrode 108 and the scanning line 21 on signal transmission is reduced.
As shown in fig. 2, a schematic plan view of a common electrode 108 in the array substrate 10 according to the embodiment of the present disclosure is provided; specifically, the array substrate 10 includes a plurality of scan lines 21 arranged along a first direction D1 and a plurality of data lines 22 arranged along a second direction D2, and the first direction D1 intersects with the second direction D2. The sub-pixel unit 20 is formed by the intersection area of the plurality of scanning lines 21 and the plurality of data lines 22;
wherein, the common electrodes 108 in two adjacent sub-pixel units 20 are continuous and electrically connected.
In this embodiment, the common electrode 108 is disposed in a second region adjacent to the first region 23, where the first region 23 is a region corresponding to a plurality of thin film transistors on the array substrate 10, and the second region is a region away from the plurality of thin film transistors on the array substrate 10. In the second region, the common electrode 108 completely covers the scan lines 21 arranged in the first direction D1 and the data lines 22 arranged in the second direction D2.
The common electrode 108 is made of a transparent material, and the design of routing a metal film layer where the gate layer 102 is located can be replaced by a full-surface connection design, so that the aperture ratio of the sub-pixel unit 20 can be effectively increased, and the transmittance of the array substrate 10 can be further increased.
Aiming at the technical problem that the aperture opening ratio of the back plate of the current transparent display screen is low, the embodiment of the application provides an array substrate 10; the array substrate 10 comprises a plurality of sub-pixel units 20, each sub-pixel unit 20 comprises a plurality of thin film transistors with a back channel etching type structure, a common electrode 108 made of a transparent material and a pixel electrode 110 arranged on one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, wherein in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is positioned in the common electrode 108; in the array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers an area, far away from the thin film transistor, on the array substrate 10, and a gate metal film routing design adopted by the common electrode 108 is replaced, thereby improving the aperture ratio of the sub-pixel unit 20 and further improving the transmittance of the array substrate 10.
Example two
Fig. 3 is a schematic view of a second cross-sectional structure of the array substrate 10 according to the embodiment of the present disclosure; the structure of the array substrate 10 in the second embodiment of the present application is the same as or similar to the structure of the array substrate 10 in the first embodiment of the present application, but the difference is that a plurality of thin film transistors are disposed in the array substrate 10, and the thin film transistors are in a top gate structure. The top gate structure can greatly improve the problem of parasitic capacitance caused by the overlapped accumulation of the source drain layer 105 and the gate layer 102 in the vertical direction.
Specifically, the array substrate 10 includes the substrate 101, a light-shielding layer 111 disposed on the substrate 101, a buffer layer 112 disposed on the substrate 101 and completely covering the light-shielding layer 111, the active layer 104 disposed on the buffer layer 112, the gate insulating layer 103 disposed on the active layer 104, the gate layer 102 disposed on the gate insulating layer 103, an interlayer insulating layer 113 disposed on the buffer layer 112 and completely covering the active layer 104, the gate insulating layer 103, and the gate layer 102, the source/drain electrode layer 105 disposed on the interlayer insulating layer 113, the first inorganic insulating layer 106 disposed on the interlayer insulating layer 113 and covering the source/drain electrode layer 105, the organic insulating layer 107 disposed on the first inorganic insulating layer 106, the common electrode 108 disposed on the organic insulating layer 107, and a gate electrode disposed on the gate insulating layer 103, The passivation layer 109 disposed on the organic insulating layer 107 and covering the common electrode 108 and the pixel electrode 110 disposed on the passivation layer 109;
in a top view direction of the array substrate 10, an orthogonal projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
In the embodiment of the present invention, the material of the buffer layer 112 may be one or more of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or silicon dioxide, which plays a role of isolating water and oxygen. The material of the light-shielding layer 111 may be a metal material having excellent conductivity, such as molybdenum, copper, and aluminum.
Specifically, in the top view direction of the array substrate 10, an orthographic projection of the active layer 104 on the substrate 101 is located in the light shielding layer 111. This prevents external light from adversely affecting the active layer 104.
In the embodiment of the present application, the array substrate 10 includes a first via 1131, a second via 1132, and a third via 1133; the source 1051 of the source drain layer 105 is electrically connected to the light shielding layer 111 through a first via 1131, the source 1051 of the source drain layer 105 is also electrically connected to one end of the active layer 104 through a second via 1132, and the drain 1052 of the source drain layer 105 is electrically connected to the other end of the active layer 104 through a third via 1133.
Further, the array substrate 10 further includes a fourth via 1092, the fourth via 1092 penetrates through the passivation layer 109, the organic insulating layer 107 and a portion of the first inorganic insulating layer 106 and exposes the drain electrode 1052 of the source and drain electrode layer 105, and the pixel electrode 110 completely fills the fourth via 1092 and is electrically connected to the drain electrode 1052 of the source and drain electrode layer 105.
Aiming at the technical problem that the aperture opening ratio of the back plate of the current transparent display screen is low, the embodiment of the application provides an array substrate 10; the array substrate 10 comprises a plurality of sub-pixel units 20, each sub-pixel unit 20 comprises a plurality of thin film transistors with a top gate structure, a common electrode 108 made of a transparent material and a pixel electrode 110 arranged on one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, wherein in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108; in the array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers an area, far away from the thin film transistor, on the array substrate 10, and a gate metal film routing design adopted by the common electrode 108 is replaced, thereby improving the aperture ratio of the sub-pixel unit 20 and further improving the transmittance of the array substrate 10.
Correspondingly, the embodiment of the application also provides a display panel, which comprises an array substrate 10, an opposite substrate and a liquid crystal layer arranged between the array substrate 10 and the opposite substrate;
the array substrate 10 includes a plurality of sub-pixel units 20, each sub-pixel unit 20 includes a common electrode 108 made of a transparent material and a pixel electrode 110 disposed on one side of the common electrode 108, and the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10;
in a top view direction of the array substrate 10, an orthogonal projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108.
Particularly, the display panel is applied to a transparent display, a mobile terminal and outdoor large-screen display.
The embodiment of the application provides an array substrate 10 and a display panel; the array substrate 10 comprises a plurality of sub-pixel units 20, each sub-pixel unit 20 comprises a common electrode 108 made of a transparent material and a pixel electrode 110 arranged on one side of the common electrode 108, the common electrode 108 and the pixel electrode 110 form a storage capacitor of the array substrate 10, wherein in a top view direction of the array substrate 10, an orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108; in the array substrate 10, the common electrode 108 in each sub-pixel unit 20 is made of a transparent material, and in the top view direction of the array substrate 10, the orthographic projection of the pixel electrode 110 on the common electrode 108 is located in the common electrode 108, so that the common electrode 108 forming the storage capacitor completely covers an area, far away from the thin film transistor, on the array substrate 10, and a gate metal film routing design adopted by the common electrode 108 is replaced, thereby improving the aperture ratio of the sub-pixel unit 20 and further improving the transmittance of the array substrate 10.
The array substrate 10 and the display panel provided in the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate is characterized by comprising a plurality of sub-pixel units; wherein each of the sub-pixel units comprises:
a common electrode made of a transparent material; and
the pixel electrode is arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
in a top view direction of the array substrate, an orthographic projection of the pixel electrode on the common electrode is located in the common electrode.
2. The array substrate of claim 1, wherein the common electrodes in two adjacent sub-pixel units are continuous and electrically connected.
3. The array substrate of claim 1, wherein each of the sub-pixel units comprises a gate layer and a source drain layer disposed on the gate layer;
the common electrode is arranged with the grid layer and the source drain layer.
4. The array substrate of claim 3, further comprising:
the organic insulating layer is arranged on the source drain layer;
the common electrode is arranged on the organic insulating layer;
a passivation layer disposed on the common electrode;
the pixel electrode is arranged on the passivation layer;
wherein a dielectric constant of the passivation layer is greater than a dielectric constant of the organic insulating layer.
5. The array substrate of claim 4, wherein the passivation layer is made of at least one of silicon nitride, silicon oxide and silicon oxynitride, and the organic insulating layer is made of at least one of acrylic resin, polytetrafluoroethylene, polycarbonate and polystyrene.
6. The array substrate of claim 4, wherein a ratio of a thickness of the organic insulating layer to a thickness of the passivation layer is greater than or equal to 2.
7. The array substrate of claim 4, wherein the material of the common electrode and the pixel electrode comprises at least one of indium tin oxide, indium oxide, tin dioxide, zinc oxide, chromium oxide, and indium zinc oxide.
8. The array substrate of claim 4, further comprising:
a gate insulating layer disposed on the substrate and covering the gate layer;
an active layer disposed on the gate insulating layer and corresponding to the gate layer; and
the source drain layer is arranged on the grid insulation layer and is electrically connected with the active layer.
9. The array substrate of claim 4, further comprising:
a light-shielding layer disposed on the substrate;
a buffer layer disposed on the substrate and covering the light-shielding layer;
an active layer disposed on the buffer layer;
a gate insulating layer disposed on the active layer;
a gate electrode layer disposed on the gate insulating layer;
an interlayer insulating layer disposed on the buffer layer and completely covering the active layer, the gate insulating layer, and the gate electrode layer; and
and the source drain layer is arranged on the interlayer insulating layer.
10. A display panel comprising an array substrate, an opposite substrate and a liquid crystal layer disposed between the array substrate and the opposite substrate, wherein the array substrate comprises a plurality of sub-pixel units, each of the sub-pixel units comprising:
a common electrode made of a transparent material; and
the pixel electrode is arranged on one side of the common electrode, and the common electrode and the pixel electrode form a storage capacitor of the array substrate;
in a top view direction of the array substrate, an orthographic projection of the pixel electrode on the common electrode is located in the common electrode.
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| CN202210171718.1A CN114428426B (en) | 2022-02-24 | 2022-02-24 | Array substrate and display panel |
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| CN202210171718.1A CN114428426B (en) | 2022-02-24 | 2022-02-24 | Array substrate and display panel |
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| CN103278986A (en) * | 2013-04-01 | 2013-09-04 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104166278A (en) * | 2013-05-16 | 2014-11-26 | 瀚宇彩晶股份有限公司 | Pixel array substrate |
| US20150311232A1 (en) * | 2013-08-30 | 2015-10-29 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and display device |
| US20160240557A1 (en) * | 2013-05-24 | 2016-08-18 | Hefei Boe Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof, and display device including the array substrate |
| CN106855670A (en) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103278986A (en) * | 2013-04-01 | 2013-09-04 | 京东方科技集团股份有限公司 | Array substrate, display device and manufacturing method of array substrate |
| CN104166278A (en) * | 2013-05-16 | 2014-11-26 | 瀚宇彩晶股份有限公司 | Pixel array substrate |
| US20160240557A1 (en) * | 2013-05-24 | 2016-08-18 | Hefei Boe Optoelectronics Technology Co., Ltd. | Array substrate and manufacturing method thereof, and display device including the array substrate |
| US20150311232A1 (en) * | 2013-08-30 | 2015-10-29 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and display device |
| CN106855670A (en) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | Array base palte, display panel and display device |
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