CN114335187B - PIP capacitor structure, manufacturing method thereof and semiconductor device - Google Patents
PIP capacitor structure, manufacturing method thereof and semiconductor device Download PDFInfo
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- CN114335187B CN114335187B CN202111667018.3A CN202111667018A CN114335187B CN 114335187 B CN114335187 B CN 114335187B CN 202111667018 A CN202111667018 A CN 202111667018A CN 114335187 B CN114335187 B CN 114335187B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 230000005641 tunneling Effects 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims description 253
- 239000000463 material Substances 0.000 claims description 34
- 230000002093 peripheral effect Effects 0.000 claims description 25
- 238000002955 isolation Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 18
- 238000005498 polishing Methods 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000000227 grinding Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 239000000243 solution Substances 0.000 description 13
- 239000002253 acid Substances 0.000 description 11
- 239000012535 impurity Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- -1 gaAs Chemical class 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
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Abstract
The application provides a PIP capacitor structure, a manufacturing method thereof and a semiconductor device, wherein the PIP capacitor structure comprises: a substrate; a tunneling oxide layer formed on the substrate; a floating gate layer formed on the tunneling oxide layer; a dielectric layer formed on the floating gate layer; the control gate layer is formed on the dielectric layer, at least one window is formed on the dielectric layer and the control gate layer, and part of the floating gate layer is exposed from the window; at least one height adjustment structure; the height adjustment structure penetrates through the floating gate layer, the tunneling oxide layer and part of the substrate. The PIP capacitor structure, the manufacturing method thereof and the semiconductor device provided by the application can improve the breakdown resistance and the service life of the PIP capacitor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a PIP capacitor structure, a manufacturing method thereof and a semiconductor device.
Background
The capacitor has wide application in integrated circuits, and can play a plurality of roles of coupling, filtering, compensation and the like, and the lower voltage of the capacitor can be increased to high voltage in a chip through the charge pump circuit so as to meet the electrical requirements of products. Whereas the PIP (Poly-Insulator-Poly) capacitor structure is a commonly used capacitor structure, it is used in various chips. In general, the PIP capacitor structure may be fabricated from a stacked gate structure of a floating gate transistor. The stacked gate structure comprises a tunneling oxide layer, a floating gate layer formed on the tunneling oxide layer, a dielectric layer formed on the floating gate layer and a control gate layer formed on the dielectric layer. The stacked gate structure of the PIP capacitor structure is formed with a window, a part of the floating gate layer is exposed from the window, a contact layer is formed on the floating gate layer exposed from the window, the contact layer of the PIP capacitor structure is generally formed by metal silicide (doped with Co element, etc.), and the PIP capacitor structure leads out the floating gate layer through a contact structure (contact) connected with the contact layer. A time-dependent dielectric Breakdown (TDDB) test is typically performed on the PIP capacitor structure to calculate the Breakdown voltage of the PIP capacitor structure, and when the TDDB test is successful, the PIP capacitor structure has a better Breakdown resistance, and accordingly, the PIP capacitor structure has a longer service life. However, when the floating gate layer is relatively thinWhen the contact layer is in contact with the tunneling oxide layer, co in the contact layer is easy to diffuse to the interface of the tunneling oxide layer, so that the TDDB test fails, and accordingly, the breakdown resistance of the PIP capacitor structure is weak, and the service life is not long.
Disclosure of Invention
Therefore, the PIP capacitor structure with better breakdown resistance and longer service life and the manufacturing method thereof are provided.
The invention provides a semiconductor device comprising the PIP capacitor structure.
In order to solve the problems, the technical scheme provided by the invention is as follows:
A PIP capacitor structure comprising:
A substrate;
a tunneling oxide layer formed on the substrate;
a floating gate layer formed on the tunneling oxide layer;
A dielectric layer formed on the floating gate layer;
a control gate layer formed on the dielectric layer; the medium layer and the control gate layer are provided with at least one window, and part of the floating gate layer is exposed out of the window; and
At least one height adjustment structure; the height adjustment structure penetrates through the floating gate layer, the tunneling oxide layer and part of the substrate.
In an alternative embodiment of the present application, the polishing rate of the height adjustment structure is smaller than the polishing rate of the floating gate layer.
In an alternative embodiment of the present application, the material of the height adjustment structure is silicon oxide.
In an alternative embodiment of the application, the height adjustment structure is located on at least one side of the fenestration.
In an alternative embodiment of the present application, the PIP capacitor structure includes a plurality of the height adjustment structures, and the plurality of height adjustment structures are arranged around the window in rows and/or columns.
In an optional embodiment of the application, the number of the windows is more than or equal to 2, and the windows are symmetrically arranged. In an alternative embodiment of the present application, the floating gate layer has a height greater than
In an alternative embodiment of the present application, the height adjustment structure has a feature size of
In an alternative embodiment of the present application, the substrate includes a central region and a peripheral region, and the PIP capacitor structure is located in the peripheral region of the substrate.
In an alternative embodiment of the present application, the PIP capacitor structure further includes:
a first doped region, a second doped region, and a third doped region formed on the substrate; the first doped region and the second doped region are respectively a source region and a drain region of the PIP capacitor structure, and the third doped region is a lead-out region of the substrate;
A first contact structure; one end of the first contact structure is electrically connected with the floating gate layer, and the other end of the first contact structure is used for inputting voltage;
a second contact structure; one end of the second contact structure is electrically connected with the control gate layer, and the other end of the second contact structure is grounded;
a third contact structure; one end of the third contact structure is electrically connected with the first doped region and/or the second doped region, and the other end of the third contact structure is grounded;
A fourth contact structure; one end of the fourth contact structure is electrically connected with the third doped region, and the other end of the fourth contact structure is grounded; and
An interlayer dielectric layer formed on the substrate and covering the control gate layer; and one ends of the first contact structure, the second contact structure, the third contact structure and the fourth contact structure, which are far away from the substrate, are respectively exposed from the interlayer dielectric layer.
The application also provides a semiconductor device comprising at least one PIP capacitor structure as described above.
In an alternative embodiment of the present application, the semiconductor device further includes a peripheral circuit and a floating gate memory; the substrate of the semiconductor device further comprises a central region and a peripheral region, the peripheral circuit is positioned in the peripheral region of the substrate, and the floating gate memory is positioned in the central region of the substrate; the PIP capacitance structure is located within a peripheral region of the substrate.
In an alternative embodiment of the present application, the semiconductor device further includes at least one isolation structure, and the isolation structure is located on at least one side of the PIP capacitor structure.
In an alternative embodiment of the present application, the feature size of the isolation structure is greater than or equal to the feature size of the height adjustment structure.
The application also provides a manufacturing method of the PIP capacitor structure, which comprises the following steps:
Providing a substrate;
forming a height adjustment structure on the substrate;
Sequentially depositing a tunneling oxide layer material and a floating gate material on the substrate to form an initial tunneling oxide layer and a first initial floating gate layer, wherein the first initial floating gate layer covers the height adjustment structure; and
Flattening the first initial floating gate layer by taking the height adjusting structure as an grinding stop layer to obtain a second initial floating gate layer;
Sequentially depositing an initial dielectric layer and an initial control gate layer on the second initial floating gate layer to obtain an initial stacked gate structure comprising the initial tunneling oxide layer, the second initial floating gate layer, the initial dielectric layer and the initial control gate layer;
Patterning the initial stacked gate structure to obtain a stacked gate structure comprising a control gate layer, a dielectric layer, a floating gate layer and a tunneling oxide layer; and
At least one window is formed on the dielectric layer and the control gate layer, and part of the floating gate layer is exposed from the window; the height adjustment structure is located on at least one side of the fenestration.
In an alternative embodiment of the present application, the polishing rate of the height adjustment structure is smaller than the polishing rate of the floating gate layer.
In an alternative embodiment of the present application,
The manufacturing method of the height adjusting structure comprises the following steps:
Forming a sacrificial layer on the substrate;
patterning the sacrificial layer and the substrate to form a first trench penetrating the sacrificial layer and a portion of the substrate;
filling a first material in the first groove to form a height adjusting structure; and
And removing the sacrificial layer.
According to the PIP capacitor structure, the manufacturing method thereof and the semiconductor device provided by the invention, at least one height adjusting structure is formed, so that when the floating gate layer of the PIP capacitor is flattened, one end, far away from the substrate, of the height adjusting structure can be used as a grinding stop surface, the thickness loss of the floating gate layer can be reduced, and the breakdown resistance of the PIP capacitor structure and the service life of the PIP capacitor structure are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a top view of a PIP capacitor structure and isolation device provided by the present invention.
Fig. 2 is a cross-sectional view along III-III of the PIP capacitor structure and isolation device shown in fig. 1.
Fig. 3 is a flow chart of a method for fabricating a PIP capacitor structure according to a preferred embodiment of the present invention.
Fig. 4 is a cross-sectional view of a substrate and a sacrificial layer formed on the substrate according to a preferred embodiment of the present invention.
Fig. 5 is a cross-sectional view of the sacrificial layer and the substrate of fig. 4 after forming a first trench and a second trench.
Fig. 6 is a cross-sectional view of the first trench shown in fig. 5 filled with a first material and the second trench filled with a second material, respectively forming a height adjustment structure and an isolation structure, and removing the sacrificial layer.
Fig. 7 is a cross-sectional view of the tunnel oxide and floating gate materials deposited on the height adjustment structure and isolation structure shown in fig. 6, resulting in an initial tunnel oxide layer and a first initial floating gate layer.
Fig. 8 is a cross-sectional view of the first initial floating gate layer shown in fig. 7 after planarization and subsequent deposition of an initial dielectric layer and an initial control gate layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The present invention may repeat reference numerals and/or letters in the various examples, and is for the purpose of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The semiconductor device of the present invention and the method of manufacturing the same will be described in detail below with reference to specific embodiments.
Referring to fig. 1 to 2, a semiconductor device according to a preferred embodiment of the present invention includes a substrate 100, and at least one PIP capacitor structure 200, at least one floating gate memory (not shown), and peripheral circuits (not shown) formed on the substrate 100. The substrate 100 includes a central region (not shown) and a peripheral region (not shown), the region where the peripheral circuit is located is defined as a peripheral region, and the region where the floating gate memory is located is defined as a central region. The PIP capacitor structure 200 is located within the peripheral region of the semiconductor device. Wherein, the PIP capacitor structure 200 is disposed in the peripheral area of the substrate 100, rather than in the central area of the substrate 100, so that the loss of the floating gate layer of the PIP capacitor structure 200 when the floating gate memory is manufactured by dry etching and/or wet etching in the central area can be avoided, and the thickness of the floating gate layer of the PIP capacitor structure 200 is increased to a certain extent, so as to improve the breakdown resistance and the service life of the PIP capacitor structure 200.
In some embodiments, two adjacent PIP capacitor structures 200, between the PIP capacitor structure 200 and the peripheral circuit, between the PIP capacitor structure 200 and the floating gate memory, between the peripheral circuit and the floating gate memory, etc., may all be isolated by at least one isolation structure 320.
The substrate 100 may be a substrate known in the art, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, and the material of the substrate 100 may include silicon, germanium, silicon carbide, gallium arsenide, indium gallium or other group iii-v compounds (e.g., gaAs, gaAsP, alInAs, alGaAs, gaInAs, gaInP or GaInAsP, etc.), or a combination thereof.
Wherein each of the PIP capacitor structures 200 includes the substrate 100, a stacked gate structure 210 formed on the substrate 100, and at least one height adjustment structure 310.
The substrate 100 has a first doped region 91, a second doped region 92, and a third doped region 93 formed thereon. The first doped region 91 and the second doped region 92 are a source region and a drain region of the PIP capacitor structure 200, respectively, and the third doped region 93 is an extraction region of the substrate 100. The first doped region 91 and the second doped region 92 are located between the isolation structure 320 and the stacked gate structure 210, and the third doped region 93 is located at a side of the isolation structure 320 away from the first doped region 91 and the second doped region 92. The first doped region 91, the second doped region 92, and the third doped region 93 are formed by implanting impurity ions into the substrate 100.
The first doped region 91, the second doped region 92, and the third doped region 93 may be doped with N-type impurity ions or P-type impurity ions. The N-type impurity ions comprise one or more of phosphorus ions, arsenic ions, antimony ions and the like, and the P-type impurity ions comprise one or more of boron ions, indium ions, gallium ions and the like. In an alternative embodiment of the present application, the first doped region 91 and the second doped region 92 are doped with N-type impurity ions, and the third doped region 93 is doped with P-type impurity ions.
The stacked gate structure 210 includes a tunnel oxide layer 40 formed on the substrate 100, a floating gate layer 50 formed on the tunnel oxide layer 40, a dielectric layer 60 formed on the floating gate layer 50, and a control gate layer 70 formed on the dielectric layer 60.
The floating gate layer 50 includes a first surface 511 parallel to the substrate 100 and in contact with the tunnel oxide layer 40, and a second surface 512 opposite the first surface 511. Defining the vertical distance from the first surface 511 to the second surface 512 as the height of the floating gate layer 50, the height of the floating gate layer 50 is greater thanPreferably, the floating gate layer 50 has a height of
In an alternative embodiment of the present application, the dielectric layer 60 is an ONO dielectric layer (oxide-nitride-oxide). Of course, the material of the dielectric layer 60 is not limited to the ONO dielectric layer, but may be another dielectric layer.
The dielectric layer 60 and the control gate layer 70 have at least one window 80 thereon, a portion of the floating gate layer 50 is exposed from the window 80, and the height adjusting structure 310 is located on at least one side of the window 80.
In an alternative embodiment of the present application, two or more windows 80 are provided on the dielectric layer 60 and the control gate layer 70, and a plurality of windows 80 are symmetrically disposed, which is beneficial to ensuring the stability of the process. Specifically, the two windows 80 are disposed on opposite sides of the PIP capacitor structure, and may be vertically symmetrical, laterally symmetrical, or diagonally symmetrical; three fenestrations 80 may be provided at three corners of the regular triangle; four fenestrations 80 may be provided at four corners or four sides of a square or rectangle.
The height adjusting structure 310 is used for adjusting and controlling the height of the floating gate layer 50 during the process of forming the floating gate layer, so as to prevent the loss of the height of the floating gate layer caused by excessive grinding during the process of leveling the floating gate layer 50.
Specifically, the height adjustment structure 310 penetrates the floating gate layer 50, the tunnel oxide layer 40, and a portion of the substrate 100. In an alternative embodiment of the present application, the surface of the end of the height adjustment structure 310 away from the substrate 100 is flush with the surface of the floating gate layer 50 away from the tunnel oxide layer 40.
In an alternative embodiment of the present application, the feature size of the height adjustment structure 310 is less than or equal to the feature size of the isolation structure.
In another alternative embodiment of the present application, the feature size of the height adjustment structure 310 is much smaller than the feature size of the isolation structure 320. Specifically, the height adjustment structure 310 has a characteristic dimension ofThe isolation structures 320 have a feature size greater than
In an alternative embodiment of the present application, the polishing rate of the height adjustment structure 310 is smaller than the polishing rate of the floating gate layer 50, so that when the floating gate layer is planarized, the end of the height adjustment structure 310 away from the substrate may be used as a polishing stop surface to reduce the thickness loss of the floating gate layer, thereby improving the breakdown resistance of the PIP capacitor structure 200 and improving the service life of the PIP capacitor structure 200. In addition, the height adjustment structure 310 may indirectly cause the thickness of the floating gate memory (not shown) located in the central region to be increased, that is, the volume of the floating gate to be increased, thereby increasing the amount of electrons storable in the floating gate of the floating gate memory, which is beneficial to increasing the service life of the floating gate memory.
In an alternative embodiment of the present application, the material of the height adjustment structure 310 is silicon oxide. In other embodiments, other materials may be used, where the polishing rate is less than the polishing rate of the floating gate layer material, and the polishing stop layer functions.
In an alternative embodiment of the present application, each of the PIP capacitor structures 200 may further include a plurality of the height adjustment structures 310. A plurality of the height adjustment structures 310 are arranged in rows and/or columns around the window 80.
In an alternative embodiment of the present application, the protruding height of the isolation structure 320 protruding out of the substrate 100 is less than or equal to the protruding height of the height adjustment structure 310 protruding out of the substrate 100.
Each PIP capacitor structure 200 further includes a contact layer 61, where the contact layer 61 is located on the second surface 512 of the floating gate layer 50 exposed from the window 80, so as to serve as a connection terminal for electrically connecting the floating gate layer 50 with the outside.
In an alternative embodiment of the present application, the material of the contact layer 61 is metal silicide and Co is doped in the metal silicide.
In other embodiments, the material of the contact layer 61 is not limited to Co-doped metal silicide, but may be other materials capable of manufacturing the contact layer 61.
Wherein when the thickness of the floating gate layer 50 is smaller thanDuring this process, co is easily diffused from the contact layer 61 into the tunnel oxide layer 40, the tunnel oxide layer 40 of the PIP capacitor structure 200 is easily broken down, and the PIP capacitor structure 200 has a short service life. Thus, the height of the floating gate layer is set to be larger thanCo diffusion from the contact layer 61 into the tunnel oxide layer 40 can be prevented, and the breakdown resistance and lifetime of the PIP capacitor structure can be increased.
In the present application, the height of the floating gate layer 50Preferably, the floating gate layer 50 has a height of
In an alternative embodiment of the present application, the PIP capacitor structure 200 further includes at least one of a first contact structure 62, a second contact structure 63, a third contact structure 64, and a fourth contact structure 65. Specifically, one end of the first contact structure 62 is electrically connected to the floating gate layer 50 through the contact layer 61, and the other end is used for inputting a voltage. One end of the second contact structure 63 is electrically connected to the control gate layer 70, and the other end is grounded. One end of the third contact structure 64 is electrically connected to the first doped region 91 and/or the second doped region 92, and the other end is grounded; one end of the fourth contact structure 65 is electrically connected to the third doped region 93, and the other end is grounded.
In an alternative embodiment of the present application, the second contact structure 63, the third contact structure 64 and the fourth contact structure 65 are also electrically connected to the control gate layer 70, the first doped region 91, the second doped region 92 and the third doped region 93 through contact layers (not shown), respectively.
In an alternative embodiment of the present application, the PIP capacitor structure 200 further includes an interlayer dielectric layer 400, and the interlayer dielectric layer 400 is formed on the substrate 100 and covers the control gate layer 70; the ends of the first contact structure 62, the second contact structure 63, the third contact structure 64, and the fourth contact structure 65, which are far away from the substrate 100, are exposed from the interlayer dielectric layer 400.
In an alternative embodiment of the present application, the capacitor path formed in the PIP capacitor structure includes: the first capacitor formed by the floating gate layer 50, the dielectric layer 60 and the control gate layer 70, and the second capacitor formed by the floating gate layer 50, the tunnel oxide layer 40 and the liner layer 100 are connected in parallel.
Referring to fig. 3, the present application further provides a method for fabricating a PIP capacitor structure 200, and the main steps of the method are described below with reference to fig. 1 to 2 and fig. 4 to 8.
In step S1, referring to fig. 1, a substrate 100 is provided, and the substrate 100 includes a central region (not shown) and a peripheral region (not shown) located around the central region.
In step S2, referring to fig. 4-6, a height adjustment structure 310 is formed on the substrate 100.
Specifically, the method for manufacturing the height adjustment structure 310 includes: first, referring to fig. 4, a sacrificial layer 20 is formed in the peripheral region of the substrate 100; next, referring to fig. 5, the sacrificial layer 20 and the substrate 100 are patterned to form a first trench 110 penetrating the sacrificial layer 20 and a portion of the substrate 100; referring to fig. 6 again, the first trench 110 is filled with a first material and the sacrificial layer is removed to form a height adjustment structure 310.
In a subsequent process, the sacrificial layer 20 will be removed. The material of the sacrificial layer 20 may be selected according to the specific process implementation, in this embodiment, the material of the sacrificial layer 20 may be silicon nitride (Si 3N4), and the thickness of the sacrificial layer 20 may be determined according to the thickness of the floating gate layer that is formed as required.
In step S2, a second trench 120 is also formed through the sacrificial layer 20 and through a portion of the substrate 100.
The first trench 110 and the second trench 120 may be formed by a wet etching and/or a dry etching process.
In an alternative embodiment of the present application, the feature size of the second trench 120 is greater than or equal to the feature size of the first trench 110 in a cross section perpendicular to the substrate 100.
Optionally, the first trench 110 has a feature size ofThe feature size of the second trench 120 is larger thanWherein, step S2 further comprises the steps of: a second material is filled in the second trench 120 to form an isolation structure 320.
The materials of the first material and the second material may be the same or different.
In an alternative embodiment of the present application, the material of the first material and the second material may be silicon oxide. In other embodiments, other materials are also possible.
In an alternative embodiment of the present application, the feature size of the isolation structure 320 is greater than or equal to the feature size of the height adjustment structure 310 in a cross-section perpendicular to the substrate 100.
In step S3, referring to fig. 7, a tunnel oxide layer material and a floating gate material are sequentially deposited on the substrate 100 to form an initial tunnel oxide layer 41 and a first initial floating gate layer 51.
In an alternative embodiment of the present application, the sacrificial layer 20 is etched by an acid solution to remove the sacrificial layer 20. The etch rate of the acid solution to the sacrificial layer 20 is greater than the etch rate of the acid solution to the first and second materials to the acid.
In this embodiment, the acid solution is a phosphoric acid solution. In other embodiments, the acid solution is a mixed solution of phosphoric acid and hydrofluoric acid, and the kind of the acid solution may be selected according to the material of the sacrificial layer 20.
Since the acid solution etches the height adjusting structure 310 and the isolation structure 320 to a certain extent, but the etching rate of the acid solution to the height adjusting structure 310 and the isolation structure 320 is smaller than the etching rate of the acid solution to the sacrificial layer 20, when the sacrificial layer 20 is completely etched, the height adjusting structure 310 remains, so that the height of the remaining height adjusting structure 310 protruding out of the substrate 100 determines the height of the first initial floating gate layer 51 to a certain extent, and by selecting a proper acid solution and component proportion thereof and controlling the condition setting of the process parameters, the thickness of the floating gate layer can be further increased to improve the breakdown resistance of the PIP capacitor structure 200, thereby improving the service life of the PIP capacitor structure 200.
In other embodiments of the present application, the sacrificial layer 20 may be removed by other processes, and in particular, may be dry etching.
Step S4, please refer to fig. 8, wherein the height adjustment structure 310 is used as a polish stop layer to planarize the first initial floating gate layer 51 to obtain a second initial floating gate layer 52; and forming an initial dielectric layer 61 on the second initial floating gate layer 52, and forming an initial control gate layer 71 on the initial dielectric layer 61 to obtain an initial stacked gate structure 220 including the initial tunneling oxide layer 41, the second initial floating gate layer 52, the initial dielectric layer 61, and the initial control gate layer 71.
In this embodiment, a portion of the first initial floating gate layer 51 may be removed by a chemical mechanical polishing (CHEMICAL MECHANICAL polish, CMP) method to planarize the first initial floating gate layer 51.
In an alternative embodiment of the present application, the second initial floating gate layer 52 includes a first surface 511 parallel to the substrate 100 and contacting the initial tunnel oxide layer 41, and a second surface 512 opposite to the first surface 511, and a vertical distance from the first surface 511 to the second surface 512 is defined as a height of the second initial floating gate layer 52. In the present application, the height of the second initial floating gate layer 52 can be up toThus, the thickness of the floating gate layer is prevented from being thinner (smaller than) The resulting Co in the silicide diffuses into tunnel oxide layer 40, thereby improving the dielectric layer and tunnel oxide layer breakdown resistance of the PIP capacitor structure.
In this embodiment, the height adjustment structure 310 may also indirectly cause the thickness of the floating gate memory located in the central region of the semiconductor device to increase, that is, the volume of the floating gate to increase, thereby increasing the amount of electrons storable in the floating gate of the floating gate memory, which is beneficial to increasing the service life of the floating gate memory.
Step S5, please refer to fig. 2, of patterning the initial stacked gate structure 220 to obtain the stacked gate structure 210 composed of the control gate layer 70, the dielectric layer 60, the floating gate layer 50 and the tunnel oxide layer 40; and forming a window 80 on the dielectric layer 60 and the control gate layer 70, wherein the height adjustment structure 310 is located on at least one side of the window 80.
At least one contact layer 61 is further formed on the floating gate layer 50 exposed from the window 80.
The process flow also comprises the following steps: forming a first doped region 91, a second doped region 92 and a third doped region 93 in the corresponding regions on the substrate 100 by ion implantation; the first doped region 91, the second doped region 92, and the third doped region 93 are a source region, a drain region, and an extraction region of the substrate 100 of the PIP capacitor structure, respectively.
After step S5, the method further comprises the steps of: an interlayer dielectric layer 400 covering the control gate layer 70 is formed on the substrate 100, openings are formed in the interlayer dielectric layer 400 at positions corresponding to the control gate layer 70, the first doped region 91, the second doped region 92, the third doped region 93 and the floating gate layer 50 exposed from the window 80, and conductive materials are filled or deposited in the openings to correspondingly form the second contact structure 63, the third contact structure 64, the fourth contact structure 65 and the first contact structure 62, thereby obtaining the PIP capacitor structure 200. Wherein one end of the first contact structure 62 is electrically connected to the floating gate layer 50 through the contact layer 61, and the other end inputs a voltage. One end of the second contact structure 63 is electrically connected to the control gate layer 70, and the other end is grounded. One end of the third contact structure 64 is electrically connected to the first doped region 91 or the second doped region 92, and the other end is grounded; one end of the fourth contact structure 65 is electrically connected to the third doped region 93, and the other end is grounded. The end surfaces of the first contact structure 62, the second contact structure 63, the third contact structure 64 and the fourth contact structure 65, which are far away from the substrate 100, are exposed from the interlayer dielectric layer 400.
According to the PIP capacitor structure, the manufacturing method thereof and the semiconductor device provided by the invention, 1) at least one height adjustment structure is formed, and the grinding rate of the height adjustment structure is smaller than that of the floating gate layer, so that when the floating gate layer is flattened, one end, far away from the substrate, of the height adjustment structure can be used as a grinding stop surface, the thickness loss of the floating gate layer can be reduced, and the breakdown resistance of the PIP capacitor structure and the service life of the PIP capacitor structure are improved. 2) The height adjusting structure can indirectly cause the thickness of the floating gate memory in the central region to be increased, namely the volume of the floating gate is increased, so that the electron quantity storable by the floating gate in the floating gate memory is increased, and the service life of the floating gate memory is prolonged. 3) The PIP capacitor structure is arranged in the peripheral area of the substrate instead of the central area of the substrate, so that the loss of the floating gate layer of the PIP capacitor structure when the floating gate memory is manufactured by dry etching and/or wet etching in the central area can be avoided, and the thickness of the floating gate layer of the PIP capacitor structure is increased to a certain extent, so that the breakdown resistance and the service life of the PIP capacitor structure are further improved.
In summary, although the present invention has been described in terms of the preferred embodiments, the preferred embodiments are not limited to the above embodiments, and various modifications and changes can be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is defined by the appended claims.
Claims (17)
1. A PIP capacitor structure comprising:
A substrate;
a tunneling oxide layer formed on the substrate;
a floating gate layer formed on the tunneling oxide layer;
A dielectric layer formed on the floating gate layer;
a control gate layer formed on the dielectric layer; the medium layer and the control gate layer are provided with at least one window, and part of the floating gate layer is exposed out of the window; and
At least one height adjustment structure; the height adjusting structure penetrates through the floating gate layer, the tunneling oxide layer and part of the substrate;
The PIP capacitor structure further comprises:
A first doped region, a second doped region, and a third doped region formed on the substrate; the third doped region is an extraction region of the substrate;
one end of the first contact structure is electrically connected with the floating gate layer, and the other end of the first contact structure is used for inputting voltage;
One end of the second contact structure is electrically connected with the control gate layer, and the other end of the second contact structure is grounded;
a third contact structure, one end of which is electrically connected with the first doped region and/or the second doped region, and the other end of which is grounded; and
And one end of the fourth contact structure is electrically connected with the third doped region, and the other end of the fourth contact structure is grounded.
2. The PIP capacitor structure of claim 1, wherein a polishing rate of the height adjustment structure is less than a polishing rate of the floating gate layer.
3. The PIP capacitor structure of claim 1 wherein the material of the height adjustment structure is silicon oxide.
4. The PIP capacitor structure of claim 1 wherein the height adjustment structure is located on at least one side of the fenestration.
5. The PIP capacitor structure of claim 4, wherein the PIP capacitor structure includes a plurality of the height adjustment structures, the plurality of height adjustment structures being arranged in rows and/or columns around the fenestration.
6. The PIP capacitor structure of claim 1 wherein the number of windows is greater than or equal to 2 and the windows are symmetrically arranged.
7. The PIP capacitor structure of claim 1 wherein the floating gate layer has a height greater than
8. The PIP capacitor structure of claim 1 wherein said height adjustment structure has a feature size of
9. The PIP capacitor structure of claim 1, wherein the substrate includes a central region and a peripheral region, the PIP capacitor structure being located in the peripheral region of the substrate.
10. The PIP capacitor structure of any one of claims 1-9, wherein the first doped region and the second doped region are a source region and a drain region, respectively, of the PIP capacitor structure;
The PIP capacitor structure further comprises:
An interlayer dielectric layer formed on the substrate and covering the control gate layer; and one ends of the first contact structure, the second contact structure, the third contact structure and the fourth contact structure, which are far away from the substrate, are respectively exposed from the interlayer dielectric layer.
11. A semiconductor device comprising at least one PIP capacitor structure as claimed in any one of claims 1-10.
12. The semiconductor device of claim 11, further comprising peripheral circuitry and a floating gate memory; the substrate of the semiconductor device comprises a central area and a peripheral area, the peripheral circuit is positioned in the peripheral area of the substrate, and the floating gate memory is positioned in the central area of the substrate; the PIP capacitance structure is located within a peripheral region of the substrate.
13. The semiconductor device of claim 11, further comprising at least one isolation structure located on at least one side of the PIP capacitor structure.
14. The semiconductor device of claim 13, wherein a feature size of the isolation structure is greater than or equal to a feature size of the height adjustment structure.
15. A method for fabricating a PIP capacitor structure, comprising the steps of:
Providing a substrate;
forming a height adjustment structure on the substrate;
Sequentially depositing a tunneling oxide layer material and a floating gate material on the substrate to form an initial tunneling oxide layer and a first initial floating gate layer, wherein the first initial floating gate layer covers the height adjustment structure; and
Flattening the first initial floating gate layer by taking the height adjusting structure as an grinding stop layer to obtain a second initial floating gate layer;
Sequentially depositing an initial dielectric layer and an initial control gate layer on the second initial floating gate layer to obtain an initial stacked gate structure comprising the initial tunneling oxide layer, the second initial floating gate layer, the initial dielectric layer and the initial control gate layer;
patterning the initial stacked gate structure to obtain a stacked gate structure comprising a control gate layer, a dielectric layer, a floating gate layer and a tunneling oxide layer;
At least one window is formed on the dielectric layer and the control gate layer, and part of the floating gate layer is exposed from the window;
forming a first doped region, a second doped region and a third doped region in corresponding regions on the substrate; the third doped region is an extraction region of the substrate; and
Forming a first contact structure, a second contact structure, a third contact structure and a fourth contact structure;
One end of the first contact structure is electrically connected with the floating gate layer, and the other end of the first contact structure is used for inputting voltage; one end of the second contact structure is electrically connected with the control gate layer, and the other end of the second contact structure is grounded; one end of the third contact structure is electrically connected with the first doped region and/or the second doped region, and the other end of the third contact structure is grounded; one end of the fourth contact structure is electrically connected with the third doped region, and the other end of the fourth contact structure is grounded.
16. The method of claim 15, wherein the polishing rate of the height adjustment structure is less than the polishing rate of the floating gate layer.
17. The method of fabricating a PIP capacitor structure of claim 15, wherein the method of fabricating a height adjustment structure comprises:
Forming a sacrificial layer on the substrate;
patterning the sacrificial layer and the substrate to form a first trench penetrating the sacrificial layer and a portion of the substrate;
filling a first material in the first groove to form a height adjusting structure; and
And removing the sacrificial layer.
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| CN107978592A (en) * | 2016-10-24 | 2018-05-01 | 北京兆易创新科技股份有限公司 | Multi-layer capacity and its manufacture method |
| CN109065717A (en) * | 2018-08-06 | 2018-12-21 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of PIP capacitor |
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| US7642616B2 (en) * | 2007-05-17 | 2010-01-05 | Micron Technology, Inc. | Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device |
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| CN107978592A (en) * | 2016-10-24 | 2018-05-01 | 北京兆易创新科技股份有限公司 | Multi-layer capacity and its manufacture method |
| CN109065717A (en) * | 2018-08-06 | 2018-12-21 | 上海华虹宏力半导体制造有限公司 | A kind of forming method of PIP capacitor |
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