CN114242774A - Electrostatic protection device - Google Patents
Electrostatic protection device Download PDFInfo
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- CN114242774A CN114242774A CN202111472322.2A CN202111472322A CN114242774A CN 114242774 A CN114242774 A CN 114242774A CN 202111472322 A CN202111472322 A CN 202111472322A CN 114242774 A CN114242774 A CN 114242774A
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- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 230000003071 parasitic effect Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- 210000000746 body region Anatomy 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 3
- 229910052760 oxygen Inorganic materials 0.000 claims 3
- 239000001301 oxygen Substances 0.000 claims 3
- 239000007943 implant Substances 0.000 claims 1
- 238000000605 extraction Methods 0.000 description 7
- 230000003068 static effect Effects 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
- H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The invention discloses an electrostatic protection device, which is formed by LDMOS, wherein the LDMOS comprises: a first hvw region having a second conductivity type doping and a second hvw region having a first conductivity type doping; the grid structure covers the surface of the selected area of the first high-voltage well region and extends to the upper part of the surface of the second high-voltage well region; the source region is formed in the surface region of the first high-voltage well region outside the first side face of the grid structure; a first diffusion region with heavily doped second conductivity type is further formed in the surface region of the first high-voltage well region between the second side face of the source region and the first side face of the gate structure; a drain region is formed in the second high-voltage well region outside the second side surface of the gate structure; the first diffusion region is a floating structure; the parasitic triode is formed by a source region, a first high-voltage well region including a first diffusion region, a second high-voltage well region and a drain region, wherein the first diffusion region is used for increasing the width and the concentration of a base region of the parasitic triode. The invention can improve the holding voltage after the LDMOS snapback.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an electrostatic discharge (ESD) protection device.
Background
As shown in fig. 1, it is an applied circuit diagram of the electrostatic protection device; the electrostatic protection device 102 is disposed between the input/output pad 101 and the ground, and when static electricity occurs in the input/output pad 101, the electrostatic protection device 102 is triggered and discharges the static electricity, thereby protecting the internal circuit 103.
Conventional high voltage ESD devices are typically LDMOS devices. Fig. 2 is a schematic cross-sectional view of a conventional electrostatic protection device; the circuit 102 shown in fig. 2 adopts a high-voltage LDMOS structure, a body region 202 composed of a high-voltage well region of a second conductivity type and a drift region 203 composed of a high-voltage well region of a first conductivity type are formed on a semiconductor substrate such as a silicon substrate 201, and a gate dielectric layer such as a gate oxide layer 204 and a polysilicon gate 205 covers the surface of the body region 202 and extends to the surface of the drift region 203. A source region 206 formed in the body region 202 and composed of a heavily doped region of a first conductivity type is self-aligned with a first side of the polysilicon gate 205, a heavily doped region of a second conductivity type formed in the body region 202 is formed as a body lead-out region 208, and a field oxide layer 209b is isolated between the source region 206 and the body lead-out region 208. A drain region 207 formed by a heavily doped region of the first conductivity type is formed in the drift region 203, and a field oxide layer 209a is spaced apart from the drain region 207 and the polysilicon gate 205. The source region 206, the body lead-out region 208 and the polysilicon gate 205 are all connected to the source, the resistor R101 is connected between the polysilicon gate 205 and the source, and the drain region 207 is connected to the drain.
The LDMOS shown in fig. 2 can be a P-type LDMOS, in which case the first conductivity type is P-type and the second conductivity type is N-type; the source is connected with the static end, and the drain is grounded.
The LDMOS shown in fig. 2 can also be an N-type LDMOS, in which case the first conductivity type is N-type and the second conductivity type is P-type; the source is grounded, and the drain is connected with the electrostatic end.
Typically, the ESD capability of the LDMOS itself is weak. In order to improve ESD capability and design flexibility, some deformation is usually made based on the LDMOS, for example, the drain of the P-type LDMOS is inserted into an N + region to form a parasitic Silicon Controlled Rectifier (SCR) structure, which can greatly improve ESD protection capability. However, the holding voltage (Vh) of the pure SCR structure after snapback (snapback) does not exceed 10V, and there is a large risk of latch-up (latchup) when the high-voltage port is applied, that is, when the power supply voltage of the high-voltage port is greater than the holding voltage of the SCR, latch-up is easy to occur.
Disclosure of Invention
The invention aims to provide an electrostatic protection device which can be formed by adopting LDMOS (laterally diffused metal oxide semiconductor) and can improve the holding voltage after the LDMOS snaps back, thereby reducing the risk of latch-up in the application of a high-voltage port.
In order to solve the above technical problem, the electrostatic protection device provided by the present invention is formed of an LDMOS, which includes:
the first high-voltage well region is doped with the second conduction type, and the second high-voltage well region is doped with the first conduction type; the first hvw well region and the second hvw well region are both formed in a semiconductor substrate.
A gate structure overlies a surface of a selected region of the first hvw region and extends above a surface of the second hvw region, the surface of the first hvw region that is covered by the gate structure for forming a conductive channel.
A heavily doped source region of a first conductivity type is formed in a surface region of the first hvw region outside the first side of the gate structure.
And a first diffusion region with heavily doped second conductivity type is also formed in the surface region of the first high-voltage well region between the second side surface of the source region and the first side surface of the gate structure.
And a body lead-out region with heavily doped second conductivity type is also formed in the surface region of the first high-voltage well region outside the first side surface of the source region.
A drain region heavily doped with the first conductivity type is formed in the second hvw region outside the second side of the gate structure.
The source region, the body region lead-out region and the gate structure are all connected to a source electrode composed of a front metal layer.
The drain region is connected to a drain electrode composed of a front metal layer.
The first diffusion region is a floating structure.
The source region, the first high-voltage well region including the first diffusion region, the second high-voltage well region and the drain region form a parasitic triode, the first high-voltage well region serves as a base region of the parasitic triode, the first diffusion region is used for increasing the width and concentration of the base region, so that the Beta coefficient of the parasitic triode is reduced, and therefore the maintaining voltage of the LDMOS after snapback is improved.
In a further improvement, the LDMOS includes an N-type LDMOS, in the N-type LDMOS, the first conductivity type is an N-type, the second conductivity type is a P-type, the source is connected to ground, and the drain is connected to an electrostatic terminal.
In a further improvement, the LDMOS includes a P-type LDMOS, in the P-type LDMOS, the first conductivity type is P-type, the second conductivity type is N-type, the source is connected to the electrostatic terminal, and the drain is connected to ground.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the semiconductor substrate is doped N-type or P-type.
In a further improvement, a first epitaxial layer is further formed on the surface of the semiconductor substrate, and the first hvw region and the second hvw region are both formed in the first epitaxial layer.
In a further improvement, the first epitaxial layer is doped N-type or P-type.
In a further refinement, the second side of the first hvw region and the first side of the second hvw region are in contact or not.
In a further improvement, a buried layer is further formed at the bottom of the first hvw region and the second hvw region, and the buried layer is doped N-type or P-type.
In a further improvement, a drift region field oxide is further formed in the second hvw region, and the second side of the gate structure extends to a surface of the drift region field oxide.
The gate structure is further improved by superposing a gate dielectric layer and a polysilicon gate.
In a further improvement, a second field oxide is formed between the body extraction region and the source region.
A further refinement is that the first side of the first diffusion region and the second side of the source region are in contact or not.
In a further refinement, the second side of the first diffusion region and the first side of the gate structure are self-aligned or spaced apart.
In a further improvement, a second implanted region doped with a second conductivity type is further formed in the first hvw region, the second implanted region wraps the first diffusion region, the doping concentration of the second implanted region is greater than that of the first hvw region, the doping concentration of the first diffusion region is greater than that of the second implanted region, and the second implanted region further increases the width and concentration of the base region.
In a further refinement, the second implanted region also extends into a bottom region of the gate structure.
In a further improvement, in a top view, the gate structure, the first diffusion region, the source region, the body region extraction region, and the drain region are all in a strip structure.
In the LDMOS serving as an electrostatic protection device, a first diffusion region formed in a first high-voltage well region, namely a body region, is arranged between a source region and a grid structure, the doping type of the first diffusion region is the same as that of the first high-voltage well region, the first high-voltage well region is used as a base region in a parasitic triode formed by a source region, a first high-voltage well region, a second high-voltage well region and a drain region of the LDMOS, and the insertion of the first diffusion region not only increases the width of the base region, but also increases the doping concentration of the second conduction type of the base region, and in the triode, the larger the width of the base region and the higher the doping concentration, the lower the Beta factor, i.e. the Beta factor, which is the amplification factor formed by the ratio of the collector current and the base current, the lower the Beta factor will increase the holding voltage after the LDMOS snapback, thereby reducing the risk of latch-up in high voltage port applications.
The invention can realize the increase of the holding voltage after the LDMOS snapback by additionally inserting the first diffusion region between the source region and the grid structure, the first diffusion region can be realized by changing the layout, the adjustment of the area and the concentration of the first diffusion region is easy to realize, and the adjustment of the holding voltage after the LDMOS snapback is easy to realize by adjusting the area and the concentration of the first diffusion region; for example, by increasing the area or concentration of the first diffusion region, the sustain voltage after the LDMOS snapback can be increased.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a circuit diagram of an application of an electrostatic protection device;
FIG. 2 is a schematic cross-sectional view of a conventional electrostatic protection device;
fig. 3 is a schematic cross-sectional view of an electrostatic protection device according to a first embodiment of the present invention;
fig. 4 is a layout of an electrostatic protection device according to the first embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of an electrostatic protection device according to a second embodiment of the present invention.
Detailed Description
Fig. 3 is a schematic cross-sectional view of an electrostatic protection device according to a first embodiment of the present invention; as shown in fig. 4, it is a layout of the electrostatic protection device according to the first embodiment of the present invention; the electrostatic protection device of the embodiment of the invention is formed by an LDMOS, and the LDMOS comprises:
a first hvw region 302 having a second conductivity type doping, a second hvw region 303 having a first conductivity type doping; the first hvw region 302 and the second hvw region 303 are both formed in a semiconductor substrate 301.
In the first embodiment of the present invention, the semiconductor substrate 301 includes a silicon substrate.
The semiconductor substrate 301 is doped P-type. In other embodiments can also be: the semiconductor substrate 301 is doped N-type.
In some embodiments, it can also be: a first epitaxial layer is further formed on the surface of the semiconductor substrate 301, and the first hvw region 302 and the second hvw region 303 are both formed in the first epitaxial layer.
The first epitaxial layer is doped in an N type or a P type.
In some embodiments, it can also be: a buried layer is further formed at the bottom of the first hvw region 302 and the second hvw region 303, and the buried layer is doped N-type or P-type.
The second side of the first hvw region 302 contacts the first side of the second hvw region 303. In other embodiments, this can also be: the second side of the first hvw region 302 and the first side of the second hvw region 303 are not touching.
As shown in fig. 3, the body region is formed using the first hvw region 302, and the drift region is formed using the second hvw region 303.
A gate structure overlies a surface of a selected region of the first hvw region 302 and extends above a surface of the second hvw region 303, the surface of the first hvw region 302 that is covered by the gate structure being used to form a conductive channel. A source region 306 heavily doped with a first conductivity type is formed in a surface area of the first hvw region 302 outside the first side of the gate structure.
In the first embodiment of the present invention, a drift region field oxide 310a is further formed in the second hvw region 303, and the second side of the gate structure extends to the surface of the drift region field oxide 310 a.
The gate structure is formed by stacking a gate dielectric layer 304 and a polysilicon gate 305.
A second field oxide 310b is formed between the body extraction region 308 and the source region 306.
A first diffusion region 309 heavily doped with a second conductivity type is also formed in a surface region of the first hvw region 302 between a second side of the source region 306 and a first side of the gate structure.
In the first embodiment of the present invention, a first side of the first diffusion region 309 is in contact with a second side of the source region 306. In other embodiments can also be: a first side of the first diffusion region 309 and a second side of the source region 306 are not in contact.
In the first embodiment of the present invention, the second side of the first diffusion region 309 and the first side of the polysilicon gate 305 of the gate structure are self-aligned. In other embodiments can also be: the second side of the first diffusion region 309 and the first side of the gate structure have a space.
A body extraction region 308 of a second conductivity type heavily doped is also formed in a surface region of the first hvw region 302 outside the first side of the source region 306.
A drain region 307 of a heavily doped first conductivity type is formed in the second hvw region 303 outside the second side of the gate structure. A field oxide 310c is formed outside a second side of the drain region 307.
The source region 306, the body extraction region 308 and the gate structure are all connected to a source consisting of a front side metal layer. As shown in fig. 4, the source region 306, the body region extraction region 308 and the top of the polysilicon gate 305 of the gate structure are all connected to the source electrode through corresponding contact holes 311. Resistor R201 is connected between polysilicon gate 305 and the source.
The drain region 307 is connected to a drain electrode composed of a front metal layer. The top of the drain region 307 is connected to the drain electrode through a corresponding contact hole 311.
The first diffusion region 309 is a floating structure.
In the first embodiment of the present invention, as shown in fig. 4, in a top view, the gate structure, the first diffusion region 309, the source region 306, the body region extraction region 308, and the drain region 307 are all in a stripe structure.
A parasitic triode is formed by the source region 306, the first high-voltage well region 302 including the first diffusion region 309, the second high-voltage well region 303 and the drain region 307, the first high-voltage well region 302 is used as a base region of the parasitic triode, and the first diffusion region 309 is used for increasing the width and the concentration of the base region, so that the Beta coefficient of the parasitic triode is reduced, and the sustain voltage after the LDMOS snaps back is improved.
In a first embodiment of the present invention, the LDMOS includes an N-type LDMOS, wherein the first conductivity type of the N-type LDMOS is N-type, the second conductivity type of the N-type LDMOS is P-type, the source is connected to ground, and the drain is connected to an electrostatic terminal.
Can also be: the LDMOS comprises a P-type LDMOS, wherein a first conduction type is P-type, a second conduction type is N-type, a source electrode is connected with an electrostatic end, and a drain electrode is connected with the ground.
First embodiment of the present invention in the LDMOS as an electrostatic protection device, a first diffusion region 309 formed in the first hvw region 302, i.e., the body region, is provided between the source region 306 and the gate structure, the doping type of the first diffusion region 309 is the same as that of the first hvw region 302, the first high-voltage well region 302 is used as a base region in a parasitic triode formed by the source region 306, the first high-voltage well region 302, the second high-voltage well region 303 and the drain region 307 of the LDMOS, and the insertion of the first diffusion region 309 not only increases the width of the base region, but also increases the doping concentration of the second conduction type of the base region, and in the triode, the larger the width of the base region and the higher the doping concentration, the lower the Beta factor, i.e. the Beta factor, which is the amplification factor formed by the ratio of the collector current and the base current, the lower the Beta factor will increase the holding voltage after the LDMOS snapback, thereby reducing the risk of latch-up in high voltage port applications.
In the first embodiment of the present invention, the increase of the sustain voltage after the snapback of the LDMOS can be realized by additionally inserting the first diffusion region 309 between the source region 306 and the gate structure, the first diffusion region 309 can be realized by changing the layout, the adjustment of the area and the concentration of the first diffusion region 309 is easily realized, and the adjustment of the sustain voltage after the snapback of the LDMOS is easily realized by adjusting the area and the concentration of the first diffusion region 309; for example, by increasing the area or concentration of the first diffusion region 309, the sustain voltage after the LDMOS snapback can be increased.
Fig. 5 is a schematic cross-sectional view of an electrostatic protection device according to a second embodiment of the present invention; the electrostatic protection device according to the second embodiment of the present invention is different from the electrostatic protection device according to the first embodiment of the present invention in that the electrostatic protection device according to the second embodiment of the present invention further includes the following features:
a second implantation region 401 doped with a second conductivity type is further formed in the first hvw region 302, the second implantation region 401 wraps the first diffusion region 309, the doping concentration of the second implantation region 401 is greater than that of the first hvw region 302, the doping concentration of the first diffusion region 309 is greater than that of the second implantation region 401, and the second implantation region 401 further increases the width and concentration of the base region.
The second implanted region 401 also extends into the bottom region of the gate structure.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111472322.2A CN114242774B (en) | 2021-12-06 | 2021-12-06 | ESD protection devices |
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| CN202111472322.2A CN114242774B (en) | 2021-12-06 | 2021-12-06 | ESD protection devices |
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| CN114242774A true CN114242774A (en) | 2022-03-25 |
| CN114242774B CN114242774B (en) | 2025-05-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024179208A1 (en) * | 2023-02-28 | 2024-09-06 | 杰华特微电子股份有限公司 | Electrostatic discharge semiconductor device and manufacturing method therefor, and integrated circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350081A (en) * | 1993-06-14 | 1994-12-22 | Nec Corp | Input-output protection circuit |
| US20110101425A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | Semiconductor device with increased snapback voltage |
| CN104282665A (en) * | 2013-07-12 | 2015-01-14 | 上海华虹宏力半导体制造有限公司 | High-voltage static protection structure |
| CN104425480A (en) * | 2013-08-19 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| CN105244349A (en) * | 2015-10-27 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection circuit |
-
2021
- 2021-12-06 CN CN202111472322.2A patent/CN114242774B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06350081A (en) * | 1993-06-14 | 1994-12-22 | Nec Corp | Input-output protection circuit |
| US20110101425A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | Semiconductor device with increased snapback voltage |
| CN104282665A (en) * | 2013-07-12 | 2015-01-14 | 上海华虹宏力半导体制造有限公司 | High-voltage static protection structure |
| CN104425480A (en) * | 2013-08-19 | 2015-03-18 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| CN105244349A (en) * | 2015-10-27 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Electrostatic protection circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024179208A1 (en) * | 2023-02-28 | 2024-09-06 | 杰华特微电子股份有限公司 | Electrostatic discharge semiconductor device and manufacturing method therefor, and integrated circuit |
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