CN108962890B - Integrated semiconductor device - Google Patents
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- CN108962890B CN108962890B CN201810842306.XA CN201810842306A CN108962890B CN 108962890 B CN108962890 B CN 108962890B CN 201810842306 A CN201810842306 A CN 201810842306A CN 108962890 B CN108962890 B CN 108962890B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 230000005669 field effect Effects 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 26
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an integrated semiconductor device, which comprises a substrate, a first drift region, a first well region, a second drift region, a second well region, a third drift region, a drain electrode, a first insulating layer, a first grid source part, a second grid source part and a second insulating layer, wherein the first drift region is formed on the substrate; the first grid source part comprises a first grid and a first source electrode, the first source electrode is formed on the second well region, one end of the first grid is formed on the first insulating layer, and the other end of the first grid is formed on the second well region; the second gate-source portion includes a second gate formed on the second insulating layer and a second source formed on the third drift region. The method can solve the problem that the lateral double-diffusion metal oxide field effect transistor and the junction field effect transistor in the integrated device occupy large volume.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to an integrated semiconductor device.
Background
Currently, field effect transistors are increasingly used in the electronic field, especially Junction Field Effect Transistors (JFETs) and lateral double-diffused metal oxide field effect transistors (LDMOS). The junction field effect transistor is a three-terminal active device with an amplifying function, which is composed of a p-n junction grid (G), a source (S) and a drain (D), and the working principle of the junction field effect transistor is that the output current is controlled by changing the conductivity of a channel through voltage; the transverse double-diffused metal oxide field effect transistor is a power device which is composed of a p-n junction grid (G), a source electrode (S) and a drain electrode (D) and has the functions of high voltage resistance, power control and the like, and exists in an AC-DC circuit in the form of a switching tube.
In an integrated circuit, an ultra-high voltage lateral double-diffused metal oxide semiconductor field effect transistor and a junction field effect transistor are generally required to be integrated into the same device to be used as a switching tube and a starting tube, but the size of the integrated device is large, and the integrated device greatly occupies the position space of the integrated circuit.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an integrated semiconductor device which can solve the problem that a lateral double-diffused metal oxide field effect transistor and a junction field effect transistor in the integrated device occupy large volume.
The purpose of the invention is realized by adopting the following technical scheme:
an integrated semiconductor device is integrated with a transverse double-diffused metal oxide semiconductor field effect transistor and a junction field effect transistor, and comprises a substrate, a first drift region formed on the substrate, a first well region, a second drift region, a second well region and a third drift region which are sequentially formed on the first drift region, a drain electrode formed on the first well region, a first insulating layer formed on the second drift region, a first gate source part formed on the second well region and the second drift region, and a second gate source part and a second insulating layer formed on the third drift region; one end of the first insulating layer is connected with the first well region, and one end of the second insulating layer is connected with the second well region;
the first gate-source part comprises a first gate and a first source, the first source is formed on the second well region, one end of the first gate is formed on the first insulating layer, and the other end of the first gate is formed on the second well region;
the second gate-source portion includes a second gate electrode formed on the second insulating layer and a second source electrode formed on the third drift region;
the substrate, the first drift region, the first well region, the second drift region, the second well region, the first insulating layer, the first gate-source portion, and the drain electrode form the lateral double-diffused metal oxide field effect transistor, and the substrate, the first drift region, the first well region, the third drift region, the second insulating layer, the second gate-source portion, and the drain electrode form the junction field effect transistor.
Preferably, the integrated semiconductor device further includes a first body portion formed on the second well region for electrical connection with the substrate, the first body portion being connected to the second insulating layer.
Preferably, the integrated semiconductor device further includes a doped layer adjacent to the first drift region, and one end of the doped layer extends to a lower end of the third drift region.
Preferably, the integrated semiconductor device further includes a third well region formed on the doping layer, and a second body portion formed on the third well region for electrically connecting to the substrate, and the third well region is connected to the third drift region.
Preferably, the substrate is a P-type substrate, the first well region is an N-type well region, the second well region is a P-type well region, and the third well region is a P-type well region.
Preferably, the first gate includes first polysilicon, and the first polysilicon is formed on the second drift region and the second well region.
Preferably, the second gate includes second polysilicon, and the second polysilicon is formed on the third drift region and the second well region.
Preferably, the first insulating layer and the second insulating layer are both made of silicon dioxide.
Preferably, the length of the second drift region is 60um-70 um.
Preferably, the integrated semiconductor device further includes an insulating dielectric layer formed on the first insulating layer and the second insulating layer for encapsulation.
Compared with the prior art, the invention has the beneficial effects that:
the integrated semiconductor device simultaneously comprises a first grid source part, a second grid source part, a drift region and a drain electrode which are corresponding to the first grid source part and the second grid source part, and two groups of grid electrodes, source electrodes, well regions, common drift regions and common drain electrodes, so that the grid electrodes, the source electrodes, the well regions, the drift regions and the drain electrodes of the first grid source part and the second grid source part can form assemblies with functions of a transverse double-diffusion metal oxide field effect transistor and a junction field effect transistor, and the integrated semiconductor device can simultaneously have the functions of the transverse double-diffusion metal oxide field effect transistor and the junction field effect transistor; and the first grid and the first source electrode, and the second grid and the second source electrode can share the first well region, the substrate, the drain electrode and the first drift region, and redundant well regions, drain electrodes and drift regions are not needed, so that the volume of the integrated semiconductor device is reduced.
Drawings
Fig. 1 is a cross-sectional view of an integrated semiconductor device of the present invention.
In the figure: 1. an integrated semiconductor device; 10. a substrate; 20. a first drift region; 21. a first well region; 211. a drain electrode; 22. a second drift region; 221. a first insulating layer; 23. a second well region; 231. a first body portion; 24. a third drift region; 241. a second insulating layer; 30. doping layer; 31. a third well region; 311. a second body portion; 40. a first gate-source section; 41. a first gate electrode; 411. a first polycrystalline silicon; 42. a second source electrode; 50. a second gate-source section; 51. a second gate electrode; 511. a second polycrystalline silicon; 52. a second source electrode; 60. and an insulating dielectric layer.
Detailed Description
The invention will be further described with reference to the accompanying drawings and the detailed description below:
as shown in fig. 1, an integrated semiconductor device 1 integrated with a lateral double-diffused metal oxide semiconductor field effect transistor and a junction field effect transistor according to the present invention includes a substrate 10, a first drift region 20 formed on the substrate 10, a first well region 21, a second drift region 22, a second well region 23, and a third drift region 24 sequentially formed on the first drift region 10, a drain 211 formed on the first well region 21, a first insulating layer 221 formed on the second drift region 22, a first gate-source portion 40 formed on the second well region 23 and the second drift region 22, and a second gate-source portion 50 and a second insulating layer 241 formed on the third drift region 24; wherein the first gate-source portion 40 includes a first gate 41 and a first source 42, the first source 42 is formed on the second well region 23, one end of the first gate 41 is formed on the first insulating layer 221, and the other end of the first gate 41 is formed on the second well region 23; the second gate-source portion 50 includes a second gate 51 and a second source 52, the second gate 51 is formed on the second insulating layer 241, and the second source 52 is formed on the third drift region 24; the substrate 10, the first drift region 20, the first well region 21, the second drift region 22, the second well region 23, the first insulating layer 221, the first gate source portion 40, and the drain 211 together form the lateral double-diffused metal oxide semiconductor field effect transistor, and the substrate 10, the first drift region 20, the first well region 21, the third drift region 24, the second insulating layer 241, the second gate source portion 50, and the drain 211 together form the junction field effect transistor.
In the above embodiments, each drift region can withstand a high voltage of 500V or more, each drift region can be depleted into a capacitor-like component when connected to a high voltage, and the longer the length of the drift region, the higher the withstand voltage, and the first well region 21 and the second well region 23 are located on both sides of the second drift region 22, the length of the second drift region 22 may be set to 60um-70um, most preferably 65um, this allows the voltage between the first well region 21 and the second well region 23 to be 500V-800V, the high voltage of 500V-800V can be applied between the drain 211 disposed on the first well region 21 and the first source 42 disposed on the second well region 23, of course, the breakdown voltage between the first well region 21 and the second well region 23 can be adjusted by adjusting the length of the second drift region 22, so as to improve the breakdown voltage between the first well region 21 and the second well region 23, thereby increasing the flexibility of circuit design. The integrated semiconductor device 1 simultaneously comprises a first grid 41, a second grid 51, a first source 42, a second source 52, a first well region 21, a second well region 23 and drift regions and drain electrodes 211 which are corresponding to the first grid, the second source and the second well region, and a common drift region and drain electrode 24, so that the grids, the sources, the well regions, the drift regions and the drain electrodes of the first grid source part 40 and the second grid source part 50 can form assemblies with functions of a transverse double-diffused metal oxide field effect transistor (LDMOS) and a Junction Field Effect Transistor (JFET), and the integrated semiconductor device can simultaneously have the functions of the transverse double-diffused metal oxide field effect transistor and the junction field effect transistor; the first gate 41 and the first source 42, and the second gate 51 and the second source 52 can share the substrate 10, the first drift region 20, the first well region 21, and the drain 211, and no redundant well region, drain 211, and drift region need to be provided, so that the volume of the integrated semiconductor device 1 is reduced, the integration level is improved, and the cost and difficulty of circuit design are reduced.
Preferably, as shown in fig. 1, the integrated semiconductor device 1 further includes a first body portion 231 formed on the second well region 23 for electrically connecting to the substrate 10, wherein the first body portion 231 is connected to the second insulating layer 241, and the first body portion 231 is electrically connected to the substrate 10 through a conductor, so that when the substrate 10 is grounded, the potential of the first body portion 231 is set to zero, and the first body portion 231 is generally electrically connected to the first source 42, so that the first source 42 is grounded and the potential is set to zero.
Preferably, the integrated semiconductor device 1 further includes a doped layer 30 adjacent to the first drift region 10, a third well region 31 formed on the doped layer 30, and a second body portion 311 formed on the third well region 31 and electrically connected to the substrate 10, wherein one end of the doped layer 30 extends to a lower end of the third drift region 24, and the third well region 31 is connected to the third drift region 24. Similarly, the structure can make the second body portion 311 electrically connected with the doped layer 30 and the substrate 10 as a whole, so that when the substrate 10 is grounded, the potential of the second body portion 311 is set to zero, and usually the second body portion 311 is electrically connected with the second source 52, so that the second source 52 is grounded and the potential is set to zero; the structure also facilitates that the doping layer 30 presses the upper end of the third drift region 24, so that the junction depth of the channel region of the third drift region 24 becomes shallow, the channel region of the third drift region 24 is easier to pinch off, and the pinch-off voltage between the second source 52 and the second gate 51 at the upper end of the third drift region 24 is lower. In addition, a user can flexibly adjust the doping concentration of the doping layer 30 from the aspect of process or layout design, and flexibly change the junction depth of the channel region of the third drift region 31, thereby adjusting the pinch-off voltage between the second source 52 and the second gate 51 at the upper end of the third drift region 31. Since the resistance of the doped layer 30 is generally lower than that of the substrate 10 and the doped layer 30 can be buried in the substrate 10, the doped layer 30 can lower the resistance of the substrate 10 to reduce the voltage applied to the substrate 10, thereby preventing the substrate 10 from breaking down due to an excessively high voltage, and thus the resistance of the substrate 10 can be adjusted by setting the concentration of the doped layer 30.
Preferably, the substrate 10 is a P-type substrate, the first well region 21 is an N-type well region, the second well region 23 is a P-type well region, and the third well region 31 is a P-type well region, wherein a PN junction can be formed between the P-type well region and the N-type well region, thereby facilitating the formation of an electric field and a current. It is understood that the substrate 10 may also be an N-type substrate, the first well region 21 may be a P-type well region, the second well region 23 may be an N-type well region, and the third well region 31 may be an N-type well region.
Preferably, the first insulating layer 221 and the second insulating layer 241 are both made of silicon dioxide. The first insulating layer 221 prevents a short circuit between the first gate electrode 41 and the first well region 23, and the second insulating layer 241 prevents a short circuit between the second well region 23 and the second gate electrode 51. The insulating dielectric layer 60 for packaging is formed on the first insulating layer 221 and the second insulating layer 241, which makes the present integrated semiconductor device 1 easy to mount and not easy to short-circuit, wherein the leads of the respective source, gate and drain 24 should protrude from the insulating dielectric layer 60.
Preferably, the first gate 41 includes a first polysilicon 411, and the first polysilicon 411 is formed on the second drift region 22 and the second well region 23. The second gate 51 includes a second polysilicon 511, and the second polysilicon 511 is formed on the third drift region 24 and the second well region 31. In this structure, since the first polysilicon 43 is likely to generate holes or electrons under the stimulation of a voltage, the structure facilitates the formation of a conductive channel in the second well region 23 under between the first gate 41 and the first source 42, thereby forming a gate-source current.
In the present integrated semiconductor device 1, the first gate 41 is a gate of a lateral double-diffused metal oxide field effect transistor, the first source 42 is a source of the lateral double-diffused metal oxide field effect transistor, and the first body 231 is a body of the lateral double-diffused metal oxide field effect transistor, wherein the substrate 10, the first drift region 20, the first well region 21, the second drift region 22, the second well region 23, the first insulating layer 221, the first gate source 40, and the drain 211 together form the lateral double-diffused metal oxide field effect transistor, so that the present integrated semiconductor device 1 has a function of the lateral double-diffused metal oxide field effect transistor; the second gate 51 is a gate of a junction field effect transistor, the second source 52 is a source of the junction field effect transistor, and the second body 311 is a body of the junction field effect transistor, wherein the substrate 10, the first drift region 20, the first well region 21, the third drift region 24, the second insulating layer 241, the second gate-source 50, and the drain 211 together form the junction field effect transistor, so that the integrated semiconductor device 1 has a function of the junction field effect transistor; in the structure, the first drift region 20 can be used as a deep drift region of a junction field effect transistor and a lateral double-diffused metal oxide field effect transistor at the same time, and the first drift region 20 is bridged with the third drift region 24, so that the first drift region 20 and the third drift region 24 can bear the voltage in the Y-axis direction, a current channel can be formed conveniently, and the current of the junction field effect transistor component can be further ensured; the second drift region 22 is arranged between the first well region 21 and the second well region 23, and the second drift region 22 can bear the withstand voltage in the X-axis direction, so that the function of transverse current of the transverse double-diffusion metal oxide field effect transistor can be met; in addition, the third drift region 24 is typically 10-20um in length and is separated from the drain 211, so that the potential of the third drift region 24 is less affected by the bias voltage of the drain 211, thereby enabling better performance of the jfet device. In addition, the lateral double diffused metal oxide semiconductor field effect transistor is optimally an ultra high voltage lateral double diffused metal oxide semiconductor field effect transistor (NLDMOS)
In summary, the integrated semiconductor device 1 integrates the lateral double-diffused metal oxide semiconductor field effect transistor and the junction field effect transistor together, and obtains a device which has the functions of the lateral double-diffused metal oxide semiconductor field effect transistor and the junction field effect transistor and is high-voltage resistant by arranging the corresponding drift region; in addition, the integrated semiconductor device 1 does not need to be provided with redundant well regions, drain electrodes 211 and drift regions, so that the volume is reduced, and the manufacturing cost is greatly reduced; in addition, the compatibility between the two devices can be improved due to the fusion of the transverse double-diffused metal oxide semiconductor (LDMOS) device and the junction field effect transistor device, and therefore the practicability is improved.
Various other modifications and changes may be made by those skilled in the art based on the above-described technical solutions and concepts, and all such modifications and changes should fall within the scope of the claims of the present invention.
Claims (7)
1. An integrated semiconductor device, characterized by: the integrated semiconductor device comprises a substrate, a first drift region formed on the substrate, a first well region, a second drift region, a second well region and a third drift region which are sequentially formed on the first drift region, a drain electrode formed on the first well region, a first insulating layer formed on the second drift region, a first grid source part formed on the second well region and the second drift region, and a second grid source part and a second insulating layer formed on the third drift region; one end of the first insulating layer is connected with the first well region, and one end of the second insulating layer is connected with the second well region;
the first gate-source part comprises a first gate and a first source, the first source is formed on the second well region, one end of the first gate is formed on the first insulating layer, and the other end of the first gate is formed on the second well region;
the second gate-source portion includes a second gate electrode formed on the second insulating layer and a second source electrode formed on the third drift region;
the substrate, the first drift region, the first well region, the second drift region, the second well region, the first insulating layer, the first gate-source portion, and the drain electrode together form the lateral double-diffused metal oxide semiconductor field effect transistor, and the substrate, the first drift region, the first well region, the third drift region, the second insulating layer, the second gate-source portion, and the drain electrode together form the junction field effect transistor;
the integrated semiconductor device further comprises a first body portion formed on the second well region for electrical connection with the substrate, the first body portion being connected with the second insulating layer; the integrated semiconductor device further comprises a doped layer adjacent to the first drift region, and one end of the doped layer extends to the lower end of the third drift region; the integrated semiconductor device further comprises a third well region formed on the doping layer, and a second body portion formed on the third well region and electrically connected to the substrate, wherein the third well region is connected to the third drift region.
2. The integrated semiconductor device of claim 1, wherein: the substrate is a P-type substrate, the first well region is an N-type well region, the second well region is a P-type well region, and the third well region is a P-type well region.
3. The integrated semiconductor device of claim 1, wherein: the integrated semiconductor device further includes a first polysilicon formed over the second drift region and the second well region.
4. The integrated semiconductor device of claim 1, wherein: the integrated semiconductor device further includes a second polysilicon formed over the third drift region and the second well region.
5. The integrated semiconductor device of claim 1, wherein: the first insulating layer and the second insulating layer are both made of silicon dioxide.
6. The integrated semiconductor device of claim 1, wherein: the length of the second drift region is 60um-70 um.
7. The integrated semiconductor device of claim 1, wherein: the integrated semiconductor device further includes an insulating dielectric layer formed on the first insulating layer and the second insulating layer for packaging.
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| CN201810842306.XA CN108962890B (en) | 2018-07-27 | 2018-07-27 | Integrated semiconductor device |
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| CN108962890B true CN108962890B (en) | 2021-07-30 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105679820A (en) * | 2016-03-16 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Jfet and manufacturing method thereof |
| CN105810680A (en) * | 2016-03-15 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Jfet and manufacturing method thereof |
| CN106206320A (en) * | 2016-08-16 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | The manufacture method of LDMOS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
| US9460926B2 (en) * | 2014-06-30 | 2016-10-04 | Alpha And Omega Semiconductor Incorporated | Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810680A (en) * | 2016-03-15 | 2016-07-27 | 上海华虹宏力半导体制造有限公司 | Jfet and manufacturing method thereof |
| CN105679820A (en) * | 2016-03-16 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Jfet and manufacturing method thereof |
| CN106206320A (en) * | 2016-08-16 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | The manufacture method of LDMOS |
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Effective date of registration: 20220114 Address after: 223700 Eastern District of Siyang County Economic Development Zone, Suqian, Jiangsu (phase two) Patentee after: JIANGSU POPPULA SEMICONDUCTOR CO.,LTD. Address before: 518000 building 902, block 8, sijiyu garden, Liantang street, Luohu District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN NANSHUO MINGTAI TECHNOLOGY Co.,Ltd. |