CN103955357A - Timing method for dynamic binary translation instruction set simulator - Google Patents
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Abstract
The invention relates to a timing method for a dynamic binary translation instruction set simulator. According to the method, through effectively dividing basic blocks, the occupied instruction cycles when the basic blocks execute every time can be confirmed in the stage of dynamic translation, so that the simulator can be accurately timed. The timing process comprises the following steps: (1) a jump instruction, a branch instruction and a memory access instruction are used as the dividing basis of the basic blocks; (2) the cycles of translated instructions and the size of memory latency of a memory area in which the translated instructions are located are calculated in the process of the dynamic translation, so that the occupied instruction cycles when the basic blocks execute every time can be confirmed in the stage of dynamic translation; (3) when the simulator executes code translation, the basic blocks are used as a unit to judge the response time of real-time events. Through the adoption of the method, the real-time events can be responded in time, the strong real-time requirement of aerospace embedded software can be satisfied, and at the same time, since the response time of the real-time events does not need to be judged by instructions, the timing overhead is smaller.
Description
Technical field
The present invention relates to a kind of binary translation instruction set simulator clocking method, belong to field of embedded software.
Background technology
Instruction set simulator is at software view, the cpu instruction collection to object computer, interruptable controller, peripheral hardware etc. carry out total system simulation, thereby makes software not making the computing machine that runs on different architecture under any amendment prerequisite.
And for the instruction set simulator that moves space flight embedded software, because software has very high requirement to real-time, so not only require the correctly execution result of dummy instruction of simulator, also requirement can provide instruction clocking capability, and accuracy of timekeeping can meet the requirement of software to real-time.
This clocking capability of instruction set simulator is in the process of carrying out at dummy instruction, and when being carried out instruction and carried out on physical computer by statistical simulation, the clock periodicity of needs is realized.The clocking method of the instruction set simulator of tradition based on interpretation technique is to explain after an instruction of execution, then calculates clock periodicity and the delay memory periodicity that this instruction need to expend, and then adds up and calculates total instruction simulation execution time.
Because the instruction simulation efficiency of explanation type instruction set simulator is very low, the mode of command calculations clock period expense in the process of instruction simulation accounts for smallerly one by one, can realize in this way accurate timing so adopt.But for the instruction set simulator that adopts binary translation technology, due in dynamic translation process taking fundamental block as unit, directly a kind of instruction dynamic translation of architecture is become to the instruction of another architecture, if still adopt this instruction timing mode, timing expense can significantly increase, even can exceed the shared expense of dummy instruction function, this will seriously reduce the effect of dynamic translation, and then affects the performance of binary translation simulator.
For this compiled-simulator taking fundamental block as translation unit, conventional timing mode has two kinds: a kind of is according to the instruction cycles of evaluation and simulation execution working time of host computer, the advantage of this mode is that in simulation implementation, timing accounts for expense hardly, instruction simulation efficiency height very, but because the error of estimation is very large, so for the stronger embedded software of real-time, this method is difficult to be suitable for.
Another kind is the total number of instructions of carrying out as unit statistical simulation taking the fundamental block of branch or jump instruction division, carrys out with this instruction cycles that evaluation and simulation is carried out.Although the accuracy of timekeeping that a kind of rear method is compared a kind of front method has had large increase, but the dividing mode of this fundamental block is not considered some instruction and is had multiple performance periods, and the flush bonding processor of the different frameworks different delay memory characteristic issues that may have, for example:
In the time comprising internal storage access instruction in fundamental block, the memory address of accessing due to these internal storage access instructions may change, thus spent instruction cycles while cannot Accurate Prediction fundamental block at every turn execution, as one section of TSC695F program below:
START:
(1)set0x1,％g2
(2)mov％g2,％g3
(3)nop
(4)ld[％g1],％f0
(5)set0x12000000,％g2
(6)st％g2,[％g2+％g1]
(7)add％i6,％l4,％i6
(8)sub％i6,0x60,％i6
(9)sub％i6,0x60,％o6
(10)jmp?START
(11)nop
(12)nop
According to traditional division methods, statement (1)～(11) can be divided into (because one of the call order tape here postpones groove, so Sub_clause 11 statement is also included) in a fundamental block.
According to TSC695F handbook, in this fundamental block, ld, jmp instruction cycle are 2, the st instruction cycle is 3, other instruction cycles are 1, suppose that this section of code place region of memory delay parameter is 2, the reading and writing parameter in ld and st instruction institute's access memory region is respectively X and Y, and total instruction cycles T that the instruction cycles N of this fundamental block and execution thereof once need is:
N＝(1+1+1+2+1+3+1+1+1+2+1)+(2*11)
T＝N+X+Y
For the embedded real-time software of space flight, owing to comprising some needs event of triggering in real time in operational process, as move to certain moment D, need to process event E.This just requires simulator to move to before a fundamental block first to judge, the time of supposing the dry run of current simulator is S, before execution fundamental block, need to first judge whether (S+T) is less than or equal to D, only have ready conditions and while meeting, could carry out the interpreter code of fundamental block, otherwise will cause event E to process in time.
But owing to having comprised ld and st instruction in this fundamental block, and the region of memory of accessing may change in the time of operation, so the value of T is a unknown number, this will cause simulator to be difficult to judge in advance the response opportunity of real-time event before carrying out fundamental block interpreter code.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, for the hard real-time demand of space flight embedded software, to adopting the binary translation instruction set simulator taking fundamental block as translation unit, a kind of binary translation instruction set simulator clocking method is provided, require in dynamic translation process, consider the delay memory characteristic of the polycyclic and the place region of memory that are translated instruction, and the clock cycle delay situation producing when internal storage access, make the clocking capability of simulator can meet the requirement of space flight embedded software to real-time, while having solved dynamic translation fundamental block, every instruction simulation all carries out timing judgement after carrying out, and has a strong impact on the problem of dynamic translation instruction simulation efficiency simultaneously.
Technical solution of the present invention is:
A kind of binary translation instruction set simulator clocking method, comprises that step is as follows:
(1) the time quantum SimTim that initialization is simulated the execution time for record simulator is 0, defines the count number X of the periodicity summation for representing all instructions in fundamental block, defines real-time event generation moment Counter, described Counter represents from current time, carry out after Counter clock period, simulator starts execution needs real-time event E to be processed;
(2) definition translation code cache district TC and definition buffer area LC, described buffer area LC, for preserving the read-write delay parameter of recent visit region of memory, can obtain the read-write delay parameter in access memory district of institute fast by inquiring about this buffer area;
(3) the delay memory amount of the instruction delay periodicity that definition is used for preserving different region of memorys also arranges delay memory amount according to the value of waiting status configuration register;
(4) value that simulator PC register is set is target program start address;
(5) query caching district TC, judges whether the instruction of simulator PC register indication address is translated, enters step (13), otherwise enter step (6) if be translated;
(6) dynamic translation fundamental block, dynamic translation fundamental block concrete steps are as follows:
A) record the value S of current time time quantum SimTim, and count number X is set to 0, the translating address of initialization directive simultaneously addr is the value of PC register;
B) according to present instruction translating address addr to the instruction fetching in fundamental block, simultaneously query caching district LC obtains read-write delay parameter, and the value of this delay parameter is added in time quantum SimTim;
C) fetching instruction is carried out to dynamic translation, and the periodicity t of this instruction is added in X to i.e.: X=X+t;
D) judge whether current fetching instruction is redirect or branch instruction, if enter step e), if not judge whether present instruction is internal storage access instruction, if internal storage access instruction enters step e), if not present instruction translating address addr is updated to its successor address and enters step a);
E) record the value TS of current time time quantum SimTim;
F) calculate once shared instruction cycles NTC=(TS – S)+X of fundamental block every execution, wherein (TS – S) be the instruction cycles of instruction fetching needs in fundamental block;
G) value of SimTim is reverted to S;
7) judge that real-time event moment Counter occurs and whether is more than or equal to fundamental block instruction cycle NTC, enter step (9) if be more than or equal to, otherwise enter step (8);
8) re-execute step (6), translate the fundamental block that an instruction cycles is Counter and enter step (9);
9) record the value PS of current time time quantum SimTim, carry out the dynamic translation code of fundamental block, the value of measuring SimTim after carrying out update time is SimTim=SimTim+NTC, upgrades Counter=Counter – (SimTim-PS) simultaneously;
10) upgrade PC value according to the execution result of fundamental block;
11) judge Counter whether be less than or equal to 0 or simulator whether be stopped operation, if exit fundamental block carry out; Otherwise, enter rapid (5).
The present invention's beneficial effect is compared with prior art:
(1) the present invention is by analyzing the polycyclic of delay memory and instruction, and simulator can provide the accurate instruction simulation time.
(2) the present invention divides on the basis of fundamental block with branch, jump instruction existing, increase the division principle using internal storage access instruction as end mark, only allow internal storage access instruction to appear at the ending of fundamental block, the needed clock periodicity of the each execution of fundamental block can be determined in the dynamic translation stage.
(3) the present invention sets up buffer memory and deposits the delay parameter of different region of memorys, utilizes the principle of locality of program operation, can in the time of internal storage access, obtain fast the delay memory parameter in this region.
(4) the present invention judges the response opportunity of real-time event taking fundamental block as unit, does not need the judgement of instruction one by one.
(5) the present invention can respond in time to real-time event, can meet the hard real-time demand of space flight embedded software.
Brief description of the drawings
Fig. 1 is the timing course process flow diagram in instruction set simulator implementation in the present invention.
Fig. 2 is the process flow diagram that calculates fundamental block instruction execution cycle in the present invention in the time of dynamic translation fundamental block.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described in detail.
As shown in Figure 1, 2, a kind of binary translation instruction set simulator of the present invention clocking method, comprises that step is as follows:
(1) the time quantum SimTim that initialization is simulated the execution time for record simulator is 0, defines the count number X of the periodicity summation for representing all instructions in fundamental block, defines real-time event generation moment Counter, described Counter represents from current time, carry out after Counter clock period, simulator starts execution needs real-time event E to be processed, the initial value of Counter arranges according to concrete applied environment, and its value also may change in simulator operational process;
(2) definition translation code cache district TC and definition buffer area LC, described buffer area LC, for preserving the read-write delay parameter of recent visit region of memory, can obtain the read-write delay parameter in access memory district of institute fast by inquiring about this buffer area;
(3) the delay memory amount of the instruction delay periodicity that definition is used for preserving different region of memorys also arranges delay memory amount according to the value of waiting status configuration register;
(4) value that simulator PC register is set is target program start address;
(5) query caching district TC, judges whether the instruction of simulator PC register indication address is translated, enters step (13), otherwise enter step (6) if be translated;
(6) dynamic translation fundamental block, dynamic translation fundamental block concrete steps are as follows:
A) record the value S of current time time quantum SimTim, and count number X is set to 0, the translating address of initialization directive simultaneously addr is the value of PC register;
B) according to present instruction translating address addr to the instruction fetching in fundamental block, simultaneously query caching district LC obtains read-write delay parameter, and the value of this delay parameter is added in time quantum SimTim;
C) fetching instruction is carried out to dynamic translation, and the periodicity t of this instruction is added in X to i.e.: X=X+t;
D) judge whether current fetching instruction is redirect or branch instruction, if enter step e), if not judge whether present instruction is internal storage access instruction, if internal storage access instruction enters step e), if not present instruction translating address addr is updated to its successor address and enters step a);
E) record the value TS of current time time quantum SimTim;
F) calculate once shared instruction cycles NTC=(TS – S)+X of fundamental block every execution, wherein (TS – S) be the instruction cycles of instruction fetching needs in fundamental block;
G) value of SimTim is reverted to S;
7) judge that real-time event moment Counter occurs and whether is more than or equal to fundamental block instruction cycle NTC, enter step (9) if be more than or equal to, otherwise enter step (8);
8) re-execute step (6), translate the fundamental block that an instruction cycles is Counter and enter step (9);
9) record the value PS of current time time quantum SimTim, carry out the dynamic translation code of fundamental block, the value of measuring SimTim after carrying out update time is SimTim=SimTim+NTC, upgrades Counter=Counter – (SimTim-PS) simultaneously;
10) upgrade PC value according to the execution result of fundamental block;
11) judge Counter whether be less than or equal to 0 or simulator whether be stopped operation, if exit fundamental block carry out; Otherwise, enter rapid (5).
Further illustrate principle of work of the present invention and the course of work with a specific embodiment below:
The invention provides a kind of binary translation instruction set simulator clocking method, here in conjunction with that section of code given above, suppose that they are positioned at the reference position of program, memory address is 0x02000000, the TSC695F processor that is 40bit for PROM, provides the implementation step of instruction set simulator clocking capability below:
According to processor chips handbook, in TSC695F, LDSB, LDSBA, LDSH, LDSHA, LDUB, LDUBA, LDUH, LDUHA, LD, LDA, LDF, LDFSR, LDC, LDCSR, JMPL, RETT instruction cycle are 2, LDD, LDDA, LDDF, LDDC, STB, STBA, STH, STHA, ST, STA, STF, STFSR, STC, STCSR instruction cycle are 3, STD, STDA, STDF, STDFQ, STDC, STDCQ, LDSTUB, LDSTUBA, SWAP, SWAPA, Ticc instruction cycle are 4, and other instruction cycles are 1.Be below described in Fig. 2 fundamental block translation process for the implementation step of this section of code:
1, definition translation code cache district TC, definition buffer area LC, according to waiting status register (WSCNFR) definition delay memory global variable ws_io3rw, ws_io2rw, ws_io1rw, ws_io0rw, ws_exrw_r, ws_exrw_w, ws_prw, ws_prr, ws_raw and the ws_rar of TSC695F, each region of memory in corresponding WSCNFR respectively, wherein ws_exrw_r and ws_exrw_w represent that the read-write in exchange memory region postpones:
The delay memory amount of the instruction delay periodicity that 2, definition is used for preserving different region of memorys, and according to the value in the each region of WSCNFR register, determine the value of above-mentioned variable.In the present embodiment, the value of supposing WSCNFR is set as 0, and the value of ws_io3rw, ws_io2rw, ws_io1rw, ws_io0rw, ws_exrw_r, ws_exrw_w, ws_prw, ws_prr, ws_raw and ws_rar is respectively 3,3,3,3,3,4,3,2,2,1.
3, record the value of current simulated time amount SimTim, S=SimTim, due to the reference position of this section of code in program, now the value of SimTim is 0, i.e. S=0.
4, count initialized amount X=0.
5, translation statement (1): corresponding memory address is 0x02000000, SimTim=0 before fetching, inquiry LC, the read latency value of obtaining this region is 1, now LC buffer memory is empty, after renewal LC buffer memory, obtains deferred message, SimTim=1 after fetching, because set instruction cycles is 1, so X=X+1=1.
6, translation statement (2): corresponding memory address is 0x02000004, this region memory delay parameter in LC, SimTim=1 before fetching, SimTim=2 after fetching, because mov instruction cycles is 1, so X=X+1=2.
7, translation statement (3): corresponding memory address is 0x02000008, this region memory delay parameter in LC, SimTim=2 before fetching, SimTim=3 after fetching, because nop instruction cycles is 1, so X=X+1=3.
8, translation statement (4): corresponding memory address is 0x0200000C, this region memory delay parameter in LC, SimTim=3 before fetching, SimTim=4 after fetching, because ld instruction cycles is 2, so X=X+2=5.
9,, because statement (4) is rdma read instruction, so statement (1)～(4) form a fundamental block, record the value of current time time quantum SimTim, TS=SimTim, i.e. TS=4.
10、NTC＝(TS–S)+X＝4+5＝9。
11, utilize the SimTim value S preserving before this, recover the value of SimTim, the value of recovering SimTim is 0, eliminates the impact because of instruction fetching, simulator counting being produced in dynamic translation process.
12, repeat above-mentioned translation process, because statement (6) is for writing internal memory instruction, so statement (5)～(6) form a fundamental block, its NTC is 6.
13, repeat above-mentioned translation process, because statement (10) is for jump instruction and with a delayed branch, so statement (7)～(11) form a fundamental block, its NTC is 11.
In this section of code, owing to having comprised two internal storage access instructions, so the impact of instruction cycle is had to uncertainty when this section of code carried out.In order to demonstrate the implementation of simulator, when setting program starts to carry out here, the value of register %g1 is 0, and the address of 4 access memory of statement is 0, and in Boot PROM region, it is 2 that corresponding read access postpones; Statement (6) institute's access memory address is 0x12000000, and in I/O Area2 region, it is 3 that corresponding write access postpones.
Suppose and carry out after 72 clock period, Counter is 72 o'clock, and real-time event E occurs, be below described in Fig. 1 timing course for the implementation step of this section of code:
1, initialization SimTim=0, Counter=72, PC=0x02000000.
2, inquiry TC, not yet translate PC indication position, the fundamental block that translation statement (1)～(4) form, its NTC value is 9.
3, due to Counter>9, measure the value of SimTim writing time, PS=SimTim, be PS=0, carry out interpreter code, and SimTim=SimTim+2+9=11, Counter=Counter – (SimTim-PS)=61, wherein 2 is the delay that statement (4) access memory produces, lower same.
4, upgrading PC is 0x02000010, because Counter is greater than 0, continues to carry out.
5, inquiry TC, not yet translate PC indication position, the fundamental block that translation statement (5)～(6) form, its NTC value is 6.
6, due to Counter>6, measure the value of SimTim writing time, PS=SimTim, be PS=11, carry out interpreter code, and SimTim=SimTim+3+6=20, Counter=Counter – (SimTim-PS)=52, wherein 3 is the delay that statement (6) access memory produces, lower same.
7, upgrading PC is 0x02000018, because Counter is greater than 0, continues to carry out.
8, inquiry TC, not yet translate PC indication position, the fundamental block interpreter code that translation statement (7)～(11) form, its NTC value is 11.
9, due to Counter>11, measure the value of SimTim writing time, PS=SimTim, i.e. PS=20, carries out interpreter code, and SimTim=SimTim+11=31, Counter=Counter – (SimTim-PS)=41.
10, upgrading PC is 0x02000000, because Counter is greater than 0, continues to carry out.
11, inquiry TC, translate PC indication position, the fundamental block interpreter code that perform statement (1)～(4) form, due to Counter>9, measure the value of SimTim writing time, PS=SimTim, be PS=31, carry out interpreter code, and SimTim=SimTim+2+9=42, Counter=Counter – (SimTim-PS)=30.
12, upgrading PC is 0x02000010, because Counter is greater than 0, continues to carry out.
13, inquiry TC, translate PC indication position, the fundamental block interpreter code that perform statement (5)～(6) form, due to Counter>6, measure the value of SimTim writing time, PS=SimTim, be PS=42, directly carry out interpreter code, and SimTim=SimTim+3+6=51, Counter=Counter – (SimTim-PS)=21.
14, upgrading PC is 0x02000018, because Counter is greater than 0, continues to carry out.
15, inquiry TC, translate PC indication position, the fundamental block interpreter code that perform statement (7)～(11) form, due to Counter>11, measure the value of SimTim writing time, PS=SimTim, be PS=51, directly carry out interpreter code, and SimTim=SimTim+11=62, Counter=Counter – (SimTim-PS)=10.
16, upgrading PC is 0x02000000, because Counter is greater than 0, continues to carry out.
17, inquiry TC, translate PC indication position, the fundamental block interpreter code that perform statement (1)～(4) form, due to Counter>9, measure the value of SimTim writing time, PS=SimTim, be PS=62, directly carry out interpreter code, and SimTim=SimTim+2+9=73, Counter=Counter – (SimTim-PS)=-1.
18, because the value of Counter is no longer greater than 0, stop carrying out interpreter code, process real-time event E.
In this example, if taking individual instructions as timing granularity, program loop is carried out after twice, while again carrying out to statement (4), and SimTim=68, Counter=4, at this moment the execution moment of event E not yet arrives, although after statement (4) execution, SimTim will become 73, but due to the atomicity that instruction in simulator is carried out, so still will waiting until after statement (4) simulation is carried out, could process event E.Therefore, can find out this method taking fundamental block as timing granularity from this example, and there is same live effect taking individual instructions as the method for timing granularity.
In this example, if event E occurs in the time that simulator is carried out 74 clock period, when program loop is carried out twice, and again carry out after the fundamental block interpreter code of a statement (1)～(4) formation, Counter becomes 1, at this moment form the performance period of fundamental block, so simulator can directly not carried out interpreter code, therefore can not cause event E not process in time because Counter has been less than statement (5)～(6).
The content not being described in detail in instructions of the present invention belongs to those skilled in the art's known technology.
Claims (1)
1. a binary translation instruction set simulator clocking method, is characterized in that step is as follows:
(1) the time quantum SimTim that initialization is simulated the execution time for record simulator is 0, defines the count number X of the periodicity summation for representing all instructions in fundamental block, defines real-time event generation moment Counter, described Counter represents from current time, carry out after Counter clock period, simulator starts execution needs real-time event E to be processed;
(2) definition translation code cache district TC and definition buffer area LC, described buffer area LC, for preserving the read-write delay parameter of recent visit region of memory, can obtain the read-write delay parameter in access memory district of institute fast by inquiring about this buffer area;
(3) the delay memory amount of the instruction delay periodicity that definition is used for preserving different region of memorys also arranges delay memory amount according to the value of waiting status configuration register;
(4) value that simulator PC register is set is target program start address;
(5) query caching district TC, judges whether the instruction of simulator PC register indication address is translated, enters step (13), otherwise enter step (6) if be translated;
(6) dynamic translation fundamental block, dynamic translation fundamental block concrete steps are as follows:
A) record the value S of current time time quantum SimTim, and count number X is set to 0, the translating address of initialization directive simultaneously addr is the value of PC register;
B) according to present instruction translating address addr to the instruction fetching in fundamental block, simultaneously query caching district LC obtains read-write delay parameter, and the value of this delay parameter is added in time quantum SimTim;
C) fetching instruction is carried out to dynamic translation, and the periodicity t of this instruction is added in X to i.e.: X=X+t;
D) judge whether current fetching instruction is redirect or branch instruction, if enter step e), if not judge whether present instruction is internal storage access instruction, if internal storage access instruction enters step e), if not present instruction translating address addr is updated to its successor address and enters step a);
E) record the value TS of current time time quantum SimTim;
F) calculate once shared instruction cycles NTC=(TS – S)+X of fundamental block every execution, wherein (TS – S) be the instruction cycles of instruction fetching needs in fundamental block;
G) value of SimTim is reverted to S;
7) judge that real-time event moment Counter occurs and whether is more than or equal to fundamental block instruction cycle NTC, enter step (9) if be more than or equal to, otherwise enter step (8);
8) re-execute step (6), translate the fundamental block that an instruction cycles is Counter and enter step (9);
9) record the value PS of current time time quantum SimTim, carry out the dynamic translation code of fundamental block, the value of measuring SimTim after carrying out update time is SimTim=SimTim+NTC, upgrades Counter=Counter – (SimTim-PS) simultaneously;
10) upgrade PC value according to the execution result of fundamental block;
11) judge Counter whether be less than or equal to 0 or simulator whether be stopped operation, if exit fundamental block carry out; Otherwise, enter rapid (5).
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|---|---|---|---|---|
| CN106371890A (en) * | 2016-08-29 | 2017-02-01 | 山东乾云启创信息科技股份有限公司 | Simulation method of GPU (ground power unit) |
| KR102253362B1 (en) * | 2020-09-22 | 2021-05-20 | 쿠팡 주식회사 | Electronic apparatus and information providing method using the same |
-
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| 张西超等: "TCG动态二进制翻译技术研究", 《计算机应用与软件》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106371890A (en) * | 2016-08-29 | 2017-02-01 | 山东乾云启创信息科技股份有限公司 | Simulation method of GPU (ground power unit) |
| CN106371890B (en) * | 2016-08-29 | 2019-05-28 | 山东乾云启创信息科技股份有限公司 | A kind of analogy method of GPU |
| KR102253362B1 (en) * | 2020-09-22 | 2021-05-20 | 쿠팡 주식회사 | Electronic apparatus and information providing method using the same |
| US11182297B1 (en) | 2020-09-22 | 2021-11-23 | Coupang Corp. | Electronic apparatus and information providing method using the same |
| KR102366011B1 (en) * | 2020-09-22 | 2022-02-23 | 쿠팡 주식회사 | Electronic apparatus and information providing method using the same |
| US11544195B2 (en) | 2020-09-22 | 2023-01-03 | Coupang Corp. | Electronic apparatus and information providing method using the same |
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