CN103943606B - Detection structure and detection method for defect in semiconductor device - Google Patents
Detection structure and detection method for defect in semiconductor device Download PDFInfo
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- CN103943606B CN103943606B CN201310024232.6A CN201310024232A CN103943606B CN 103943606 B CN103943606 B CN 103943606B CN 201310024232 A CN201310024232 A CN 201310024232A CN 103943606 B CN103943606 B CN 103943606B
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Abstract
The invention relates to a detection structure and detection method for a defect in a semiconductor device. The detection structure comprises the following parts: a semiconductor substrate and a diode disposed in the substrate; a first metal lamination layer which is disposed above the diode so as to apply a voltage on the diode and comprises a first top metal layer and a plurality of metal layers and through holes between the diode and the first top metal layer; and a second metal layer which is arranged at the outer side of the first metal layer in an encircling mode so as to apply a voltage on a gate and comprises a second top metal layer, a plurality of metal layers disposed between the second top metal layer and the substrate, and through holes. The detection structure and method provided by the invention not only can detect a single-layer metal layer but also can detect a multi-layer metal layer. The method is simple and easily implemented, the accuracy is high, and stability of an ultra-low-K material and the performance of the device obtained through preparation are guaranteed.
Description
Technical field
The present invention relates to semiconductor applications, in particular it relates in a kind of semiconductor device defect detection structure
And detection method.
Background technology
With the continuous development of semiconductor technology, the raising of performance of integrated circuits is mainly by constantly reducing integrated circuit
What the size of device was realized with improving its speed.At present, due in high device density, high-performance and low cost is pursued half
Conductor industry has advanced to nanotechnology process node, particularly when dimensions of semiconductor devices drop to 28nm or 20nm even with
When lower, to all many-sides such as manufacture and design very big challenge is brought.
With super large-scale integration（Ultra Large Scale Integrated circuit, ULSI）Size
Constantly reduce, the gate dielectric size in semiconductor device CMOS also constantly reduces, to obtain higher performance, when in grid
Extremely upper plus constant voltage, makes device in accumulated state after a period of time, and gate dielectric will puncture, Jing during this
The time gone through is exactly the life-span under this condition, that is, general described with time correlation dielectric breakdown（time
Dependent dielectric breakdown, TDDB）, the TDDB is the key for weighing the gate dielectric stability
One of factor, the device such as 28nm or 20nm little for size is even following particularly true.
Currently in order to improving the performance of device, ultra low-K material is widely used in advanced technology nodes, but in metal interlevel
Dielectric layer（inter-metal layer dielectric）The middle density that there is high defect, especially in ultra low-K material, institute
State defect easily becomes device precursor defect in the TDDB of pressure stress and in device preparation technology, therefore how to characterize institute
These defects in ultra low-K material are stated, is current to guarantee the stability of the ultra low-K material and prepare the performance of device
The problem for continuing to solve.
In gate control diode in prior art（Gated-diode, GD）It is generally used for characterizing front end of line（Thefont
end ofline,FEOL）The boundary defect of middle gate dielectric, methods described is measured described by the peak value of drain current ID
Interface/defect oxide.
Although gate control diode（Gated-diode, GD）In have a corresponding detection method but can not be for detecting half
The defect that ultra low-K material is present in conductor device, therefore, a kind of detection method to ultra low-K material defect of offer is needed badly, with true
The stability for protecting the ultra low-K material and the performance for preparing device.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain for attempting to determine technical scheme required for protection.
The present invention is in order to overcome the problem that presently, there are, there is provided the detection structure of defect in a kind of semiconductor device, bag
Include：
Semiconductor substrate and the diode in the substrate；
First is metal laminated, positioned at diode top, to apply diode voltage, described first it is metal laminated including
First metal layer at top and some metal levels and through hole between the diode and first metal layer at top；
Second is metal laminated, around being arranged at the described first metal laminated outside, to apply grid voltage, and described second
It is metal laminated including the second metal layer at top, some metal levels between the second metal layer at top and substrate and through hole.
Preferably, described second it is metal laminated between the substrate have interlayer dielectric layer.
Preferably, the described second metal laminated interlayer dielectric layer between the substrate is multilamellar.
Preferably, the interlayer dielectric layer is low-K material.
Preferably, it is described detection structure also include ammeter, positioned at described first it is metal laminated on, to record described two
The electric current of pole pipe, judges whether deposited in the described second metal laminated interlayer dielectric layer between the substrate by the electric current
In defect.
Preferably, the diode is the N traps formed in P type substrate.
Preferably, the Semiconductor substrate ground connection.
Preferably, the structure further includes sealing ring, it surround and is arranged at described first metal laminated, the second metal
Lamination outside.
Present invention also offers a kind of method that defect is detected based on said structure, including：
Diode bias voltage is applied to the diode；
Applying gated sweep voltage metal laminated to described second；
The peak point current of record diode；
Judge to whether there is defect in the metal laminated interlayer dielectric layer between the substrate by the electric current.
Preferably, methods described is used to detect the described second metal laminated multilamellar interlayer between the substrate simultaneously
Dielectric layer whether there is defect.
In the present invention the detection structure is made up of a metal laminated and metal laminated circular diode, by right
The diode applies bias voltage, while to the metal laminated applying gated sweep voltage, and record the peak value of diode
Electric current come detect the substrate and it is metal laminated between and it is metal laminated in the defect that whether there is of dielectric layer, the inspection
Geodesic structure and method not only can detect single metal layer and can detect more metal layers, and methods described is simple, accurate
Really property is high, it is ensured that the stability of the ultra low-K material and the performance for preparing device.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and its description, for explaining the device and principle of the present invention.In the accompanying drawings,
Fig. 1 is to the detection structure in front end of line during existing defects in prior art；
Fig. 2-4 for it is provided by the present invention for detecting semiconductor device in defect structure and defect schematic diagram.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can be able to without the need for one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, for some technical characteristics well known in the art do not enter
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, to illustrate weldering of the present invention
The detection method of dish structure.Obviously, executions of the invention be not limited to that the technical staff of semiconductor applications is familiar with it is special carefully
Section.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have other
Embodiment.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
Intention includes plural form.Additionally, it should be understood that, when in this manual using term "comprising" and/or " including "
When, it indicates there is the feature, entirety, step, operation, element and/or component, but does not preclude the presence or addition of one or many
Individual other features, entirety, step, operation, element, component and/or combinations thereof.
Now, exemplary embodiment of the invention is more fully described with reference to the accompanying drawings.However, these exemplary realities
Applying example can be implemented with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
It is understood by, there is provided these embodiments are in order that disclosure of the invention is thoroughly and complete, and by these exemplary enforcements
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, the thickness in layer and region is exaggerated
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
The invention provides in a kind of semiconductor device defect detection structure, the detection structure includes：
Semiconductor substrate and the diode in the substrate；
First is metal laminated, positioned at diode top, to apply diode voltage, described first it is metal laminated including
First metal layer at top and some metal levels and through hole between the diode and first metal layer at top；
Second is metal laminated, around being arranged at the described first metal laminated outside, to apply grid voltage, and described second
It is metal laminated including the second metal layer at top, some metal levels between the second metal layer at top and substrate and through hole.
Preferably, it is described detection structure also include ammeter, positioned at described first it is metal laminated on, to record described two
The electric current of pole pipe, by the electric current judge it is described it is metal laminated in dielectric medium whether there is defect.
Specifically, in one embodiment of this invention, the substrate can be at least in the following material being previously mentioned
Kind：Silicon, silicon-on-insulator（SOI）, be laminated silicon on insulator（SSOI）, be laminated SiGe on insulator（S-SiGeOI）And absolutely
SiGe on edge body（SiGeOI）Deng.Doped region and/or isolation structure, the isolation junction are could be formed with the substrate
Structure is shallow trench isolation（S TI）Structure or selective oxidation silicon（LOCOS）Isolation structure.The isolation structure in the present invention
Preferably shallow trench isolation.
Additionally different types of ion doping, such as P+ or N+ can be as needed carried out in the substrate, with
Form N traps or p-well.In one embodiment of this invention, substrate is P type substrate, and in the middle part of the substrate N is formed
Trap, to form the diode.
Also include in the detection structure it is metal laminated, it is described metal laminated metal laminated and circular described the including first
The second of one metal laminated setting is metal laminated, wherein, described first, second is metal laminated by metal layer at top and positioned at top
Some metal levels below portion's metal level, the composition of the through hole between some metal levels, wherein, in the same metal level
In, there is metal interlamination medium layer between conductive metal derby（inter-metal layer dielectric）, therefore from vertical
Look up, the metal level of upper and lower different layers constitutes metal throuth hole chain.It is described it is metal laminated above be metal layer at top, with
And the connection metal layer at top and metal laminated top through hole.
Preferably, wherein described second is metal laminated for first is metal laminated, described second is metal laminated
It is mutually isolated between the substrate, centre has interlayer dielectric layer, and described second is metal laminated between the substrate
Interlayer dielectric layer be multilamellar, it is and described first metal laminated by through hole and the substrate electrical connection, with the diode
Upper applying diode voltage.
Specifically, in one embodiment of this invention, as shown in Fig. 2 the substrate be silicon substrate 101, the substrate and
It is described it is metal laminated between be dielectric layer 102, in particular SiO2 is described metal laminated including dielectric layer between the first metal layer
103rd, dielectric layer 104, the 3rd metal interlamination medium layer 105 between second metal layer, wherein the dielectric layer between the first metal layer
There is conducting metal block M1, dielectric layer kind has a through hole V1 between the second metal layer between 103, connect located above the
Conducting metal block M2 in three metal interlamination medium layers, above the conducting metal block M2 for top through hole 106, and lead to
Cross the top through hole 106 to be connected with the metal layer at top 107, in the present invention the top through hole and the top metal
Layer is Al materials.
The diode by described first it is metal laminated be connected with ammeter, for the diode applied voltage,
Measurement electric current, specifically, the metal throuth hole chain above the N traps in the P type substrate and the gate control diode（Gated-
Diode, GD）First end connection, for applying fixed voltage, and measure the electric current of the gate control diode.
Preferably, the Substrate ground, specifically, is initially formed p-well, then in the p-well in the substrate
Form another metal throuth hole chain positioned at the second metal laminated outside, the metal throuth hole chain and second metallic stacked structure
Can be with identical, by the metal layer at top of the metal throuth hole chain so that the Substrate ground.
Described second is metal laminated around the described first metal laminated setting, and wherein each metal laminated can regard as
Metal throuth hole chain on above-below direction, it is metal laminated described second on scan variations grid voltage VG, as shown in Fig. 2
During test, the voltage V of the fixation diodeDiode, the scanning change grid voltage VG, then measure the gate control diode
Electric current, when 102 existing defects of interlayer dielectric layer, obtain current curve as shown at right, change scanning voltage
VGDuring, the IDiodePeak point current occurs, the interlayer dielectric layer 102 can determine whether by the change of the electric current
Existing defects.
Preferably, the structure also include passivation layer, between the top through hole and metal layer at top, for every
Conductive metallic material Al between same layer, preferably, the passivation layer is SiO2, as further preferred, the knot
Structure still further comprises the sealing ring positioned at the metal layer at top and metal laminated surrounding, further improves the property of the device
Can, but the pad structure is not limited to above-mentioned example, can also further include other common parts, and here is no longer
Repeat.
When measuring using detection structure of the present invention, it is not limited only to measure a certain interlayer dielectric layer presence
Defect, can also simultaneously measure multilamellar interlayer dielectric layer with the presence or absence of defect.
When the substrate and it is described second it is metal laminated between interlayer dielectric layer there is defect when, the peak point current is
Interlayer dielectric layer defective currents, are the measurement of defect in the dielectric layer.
When the substrate and it is described second it is metal laminated between interlayer dielectric layer, and the first gold medal in the first metal layer
During the category equal existing defects of interlayer dielectric layer, the peak point current is to be situated between interlayer dielectric layer defective currents and the first metal layer
Matter layer defects electric current sum, is the measurement of defect in dielectric layer between the interlayer dielectric layer and the first metal layer.
When the substrate and it is described second it is metal laminated and it is described 3rd it is metal laminated between interlayer dielectric layer, Yi Ji
Between the second metal layer between the first metal layer in one metal level in dielectric layer, and via layer during the equal existing defects of dielectric layer,
The peak point current is interlayer dielectric layer defective currents and the first, second metal interlamination medium layer defective currents sum, is
The measurement of defect in the interlayer dielectric layer and first, second metal interlamination medium layer.
When specifically, using the structure measurement, it is not limited to above-mentioned one kind, as shown in figure 3, working as the inter-level dielectric
When layer and the equal existing defects of the first interlayer metal level, the voltage V of the diode is equally fixed firstDiode, such as 3V, so
The grid voltage V of scan variations afterwardsG, its electric current is detected, in said case, the peak point current is the interlayer dielectric layer electric current
Dielectric layer electric current IMD1 sums between ILD and the first metal layer, as shown at right, by the size of peak point current, you can sentence
The interlayer dielectric layer that breaks whether there is defect.Equally, as shown in figure 4, when the interlayer dielectric layer and first interlayer gold
During the equal existing defects of category layer, the second interlayer metal level, the voltage V of the gate control diode is equally fixed firstDiode, for example
3V, then applies the scanning voltage V for changingG, its electric current is detected, in said case, the peak point current is the interlayer dielectric
Dielectric layer electric current IMD2 sums between dielectric layer electric current IMD1 and the second metal layer between layer electric current ILD, the first metal layer,
As shown at right, by the size of peak point current, you can judge that the interlayer dielectric layer whether there is defect.
In the present invention the detection structure is made up of a metal laminated and metal laminated circular diode, by right
The diode applies bias voltage, while to the metal laminated applying gated sweep voltage, and record the peak value of diode
Electric current come detect the substrate and it is metal laminated between and it is metal laminated in the defect that whether there is of dielectric layer, the inspection
Geodesic structure and method not only can detect single metal layer and can detect more metal layers, and methods described is simple, accurate
Really property is high, it is ensured that the stability of the ultra low-K material and the performance for preparing device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.Additionally, people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching of the invention can also make more kinds of changes
Type and modification, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention is by attached
Claims and its equivalent scope of category are defined.
Claims (10)
1. in a kind of semiconductor device defect detection structure, including：
Semiconductor substrate and the diode in the substrate；
First is metal laminated, and positioned at diode top, to apply diode voltage, described first is metal laminated including first
Metal layer at top and some metal levels and through hole between the diode and first metal layer at top；
Second is metal laminated, around the described first metal laminated outside is arranged at, to apply grid voltage, second metal
Lamination includes the second metal layer at top, some metal levels between the second metal layer at top and substrate and through hole.
2. in semiconductor device according to claim 1 defect detection structure, it is characterised in that second metal fold
There is interlayer dielectric layer between layer and the substrate.
3. in semiconductor device according to claim 2 defect detection structure, it is characterised in that second metal fold
Interlayer dielectric layer between layer and the substrate is multilamellar.
4. in the semiconductor device according to Claims 2 or 3 defect detection structure, it is characterised in that the interlayer is situated between
Matter layer is low-K material.
5. in the semiconductor device according to Claims 2 or 3 defect detection structure, it is characterised in that detection knot
Structure also include ammeter, positioned at described first it is metal laminated on, to record the electric current of the diode, judged by the electric current
Whether there is defect in the described second metal laminated interlayer dielectric layer between the substrate.
6. in semiconductor device according to claim 1 defect detection structure, it is characterised in that the diode be P
The N traps formed in type substrate.
7. in semiconductor device according to claim 1 defect detection structure, it is characterised in that the Semiconductor substrate
Ground connection.
8. in semiconductor device according to claim 1 defect detection structure, it is characterised in that the semiconductor device
The detection structure of middle defect further includes sealing ring, metal laminated and described second metal laminated around being arranged at described first
Outside.
9. in the semiconductor device described in a kind of one of employing claim 1-8 the detection structure detection defect of defect method,
Including：
Diode bias voltage is applied to the diode；
Applying gated sweep voltage metal laminated to described second；
The peak point current of record diode；
Judge to whether there is defect in the metal laminated interlayer dielectric layer between the substrate by the electric current.
10. in semiconductor device according to claim 9 the detection structure detection defect of defect method, its feature exists
In methods described is used to detect that the described second metal laminated multilamellar interlayer dielectric layer between the substrate whether there is simultaneously
Defect.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104730110A (en) * | 2015-03-24 | 2015-06-24 | 三峡大学 | Interface defect detection method and interface defect detection device of metal-dielectric medium thin-layer bonding or coating structure |
| US10177053B2 (en) * | 2016-03-03 | 2019-01-08 | Microchip Technology Incorporated | Interconnect monitor utilizing both open and short detection |
| US10998274B2 (en) * | 2017-11-30 | 2021-05-04 | Mediatek Inc. | Seal ring structure, semiconductor die, and method for detecting cracks on semiconductor die |
| CN111145824B (en) * | 2019-12-27 | 2021-09-14 | 长江存储科技有限责任公司 | Method and device for testing three-dimensional memory grid laminated defects |
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|---|---|---|---|---|
| US6847096B2 (en) * | 2002-03-25 | 2005-01-25 | Oki Electric Industry Co., Ltd. | Semiconductor wafer having discharge structure to substrate |
| CN101419948A (en) * | 2007-10-24 | 2009-04-29 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
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| US6624031B2 (en) * | 2001-11-20 | 2003-09-23 | International Business Machines Corporation | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6847096B2 (en) * | 2002-03-25 | 2005-01-25 | Oki Electric Industry Co., Ltd. | Semiconductor wafer having discharge structure to substrate |
| CN101419948A (en) * | 2007-10-24 | 2009-04-29 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| CN102194795A (en) * | 2010-03-12 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure of dielectric layer under metal layer |
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