CN103943475A - Method for improving dielectric constant of gate oxide - Google Patents
Method for improving dielectric constant of gate oxide Download PDFInfo
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- CN103943475A CN103943475A CN201410060296.6A CN201410060296A CN103943475A CN 103943475 A CN103943475 A CN 103943475A CN 201410060296 A CN201410060296 A CN 201410060296A CN 103943475 A CN103943475 A CN 103943475A
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- gate oxide
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- sion
- sio
- dielectric constant
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- 238000000034 method Methods 0.000 title claims abstract description 85
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 82
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 125000004433 nitrogen atom Chemical group N* 0.000 claims abstract description 14
- 230000008439 repair process Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000011261 inert gas Substances 0.000 claims abstract description 12
- 229910007991 Si-N Inorganic materials 0.000 claims abstract description 8
- 229910006294 Si—N Inorganic materials 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 6
- 239000007924 injection Substances 0.000 claims abstract description 6
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 6
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 26
- 239000007789 gas Substances 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- 230000035484 reaction time Effects 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 3
- 230000035755 proliferation Effects 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 239000000463 material Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000000137 annealing Methods 0.000 description 7
- 239000000654 additive Substances 0.000 description 6
- 230000000996 additive effect Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- 238000005915 ammonolysis reaction Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OTMSDBZUPAUEDD-UHFFFAOYSA-N Ethane Chemical compound CC OTMSDBZUPAUEDD-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000006902 nitrogenation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a method for improving the dielectric constant of a gate oxide and relates to the field of manufacturing process of a semiconductor MOS device and particularly relates to a method for improving the dielectric constant of the gate oxide. The method includes the following steps: providing a substrate; preparing a SiO2 gate oxide layer on the substrate; performing nitrogen injection on the SiO2 gate oxide layer so that part of oxygen atoms in the SiO2 are replaced by nitrogen atoms and thus an SiON gate oxide layer is formed; in an environment which is higher than 1000 DEG C and surrounded by a pure inert gas, performing nitrogen treatment on the SiON gate oxide layer so as to repair lattice damages and form stable Si-N bonds; and in an environment which is lower than 800 DEG C, performing oxidation treatment on the SiON gate oxide layer so as to repair an SiO2/Si interface. Compared with a traditional high-temperature nitrogen treatment process, the SiON gate oxide layer prepared through the method is stable in nitrogen content and the nitrogen content of the gate oxide can be improved effectively by about 30% so that the prepared gate oxide has a higher dielectric constant and thus an objective of precise cut-out on the dielectric constant of a SiON gate dielectric is realized.
Description
Technical field
The present invention relates to the manufacturing process field for semiconductor MOS device, relate in particular to a kind of method that improves gate oxide dielectric constant.
Background technology
The preparation technology of gate oxide is the key technology in semiconductor fabrication process, directly affects and determined electrology characteristic and the reliability of device.Since semiconductor technology enters 45 nanometer era, gate medium SiO
2thin (being less than very of thickness
), the penetration tunnel mechanism in grid leakage current has played leading role.Along with SiO
2the further reduction of thickness, grid leakage current also can increase with exponential form.The every reduction of grid medium thickness
, grid leakage current will increase by 10 times.On the other hand, grid, SiO
2between gate medium and silicon substrate, there is the concentration gradient of impurity, along with the continuous reduction of grid medium thickness, the impurity such as the boron mixing in grid can be diffused in silicon substrate or be fixed in gate medium from grid, and this can affect the threshold voltage of device, thereby affect the performance of device.Really, increase the effectively diffusion of impurity in suppressor grid leakage current and grid of grid medium thickness, but transistor drive current, the key performances such as time of delay that overturn also can be had a greatly reduced quality.The contradiction that this drive current and electric leakage of the grid require grid medium thickness, for traditional SiO
2gate medium cannot be avoided.Grid capacitance not only depends on the long-pending and grid medium thickness of gate surface, also depends on the dielectric constant of gate medium, is not the unique method that improves grid capacitance therefore reduce grid medium thickness.Even if grid medium thickness remains unchanged, the dielectric coefficient that improves gate medium also can reach the effect that reduces equivalent oxide thickness and increase grid capacitance.In present stage, the method for dielectric coefficient that improves gate medium roughly has two large classes: a class is that the material of the brand-new high-dielectric coefficient of employing is as gate medium, as nitrogen hafnium silicon oxide (HfSiON) etc.The another kind of SiO that still keeps
2as gate medium, pass through SiO
2in oxide-film, mix the dielectric coefficient that nitrogen makes it to become fine and close SiON and improve gate medium.Industry has three kinds of main methods can realize SiO conventionally at present
2in nitrogen adulterate to form SiON, but all because the nitrogen atom concentration mixing in gate medium is high and be mainly distributed in the upper surface of gate medium, therefore temperature, atmosphere and the time interval of follow-up PNA (Post Nitridation Anneal) high-temperature annealing process must strict be controlled, to prevent native oxide layer and organic absorption on the nitrogen impact causing of adulterating; In addition, the high-temperature annealing process of PNA (Post Nitridation Anneal) had both easily caused the volatilization of surface nitrogen atom, can make again nitrogen-atoms obtain energy and continue diffusion, caused part nitrogen-atoms to accumulate in SiO
2/ Si interface, thus the migration velocity of charge carrier in raceway groove is had a negative impact.
Chinese patent (CN 102437143A) discloses a kind of advanced low-k materials, comprises the dielectric material of advanced low-k materials and additive.Additive comprises the compound with Si-X-Si bridge, and wherein X is the carbon number between 1 and 8.Additive can comprise end Si-CH3 group.Comprise that the dielectric material of additive can be used as the interlayer dielectric of semiconductor device (ILD) layer.Can use CVD or sol-gel technology to form the dielectric material that comprises additive.One of described additive is exemplified as two (triethoxy is silica-based) ethane.
By material provided by the invention and semiconductor device, overcome low-k (low-k) formation of material conventionally have as bad mechanical strength, plate bursting layering, the shortcoming of the infringement that etching (as plasma) technique causes.
Chinese patent (CN102544739A) discloses a kind of super material with high-k, comprise at least one super sheet of material, each super sheet of material comprises base material and is attached to the multiple artificial micro-structural on base material, described artificial micro-structural comprises the first metal wire and the second metal wire that are parallel to each other, also comprises that at least one one end is connected with described the first metal wire, the other end is free end and towards the first metal wire branch of the second metal wire; And at least one one end is connected with described the second metal wire, the other end is free end and towards the second metal wire branch of the first metal wire, described the first metal wire branch and described the second metal wire branch are interspersed successively.The dielectric constant with the super material of this artificial micro-structural has obtained significantly improving.
Summary of the invention
In view of the above problems, the present invention can make high-temperature ammonolysis treatment process not only have stable nitrogen content, and can effectively improve gate oxide nitrogen and make prepared gate oxide have higher dielectric constant.
The technical scheme that technical solution problem of the present invention adopts is:
A method that improves gate oxide dielectric constant, comprises the following steps:
Step S1, provide a substrate;
Step S2, in described substrate, prepare a SiO
2gate oxide;
Step S3, to described SiO
2gate oxide carries out the injection of nitrogen, makes SiO
2in partial oxygen atom replaced by nitrogen-atoms, to form SiON gate oxide;
Step S4, higher than 1000 DEG C and follow under the atmosphere of pure inert gas described SiON gate oxide is carried out to nitrogen treatment, stablize Si-N key to repair lattice damage and to form;
Step S5, under the atmosphere lower than 800 DEG C, the described SiON gate oxide after nitrogen treatment is carried out to oxidation processes, to repair SiO
2/ Si interface.
Preferably, in step S2, prepare described SiO by rapid thermal anneal process and/or vertical furnace tube technique
2gate oxide.
Preferably, described rapid thermal anneal process specifically comprises original position steam oxidation method and/or rapid thermal annealing oxidizing process.
Preferably, adopt N
2o and H
2for reacting gas carries out described original position steam oxidation method; Or
Adopt O
2and H
2for reacting gas carries out described original position steam oxidation method.
Preferably, in step S3, form described SiON by decoupled plasma nitridation process and/or remote plasma nitridation technique.
Preferably, in step S3, with NO, N
2o or NH
3for raw material, adopt vertical proliferation equipment to form described SiON.
Preferably, in step S4, the temperature range of described nitrogen treatment is 1000 DEG C-1100 DEG C, and reaction time range is 5sec-120sec.
Preferably, described pure inert gas atmosphere comprises any one in nitrogen or argon gas.
Preferably, in step S5, the temperature range of described oxidation processes is 500 DEG C-800 DEG C, and reaction time range is 5sec-120sec.
Preferably, adopt oxygen to carry out described oxidation processes; Or
Adopt H
2with O
2mist carry out described oxidation processes.
Technical scheme of the present invention is compared with traditional high-temperature ammonolysis treatment process, the SiON gate oxide that adopts the present invention to prepare not only has stable nitrogen content, and can effectively improve gate oxide nitrogen content 30% left and right, thereby make prepared gate oxide there is higher dielectric constant, realized the object that SiON gate medium dielectric coefficient is accurately cut out.
Brief description of the drawings
With reference to appended accompanying drawing, to describe more fully embodiments of the invention.But appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
The processing step schematic diagram of Fig. 1 the inventive method one embodiment;
The structural representation of the step S1 of Fig. 2 the inventive method one embodiment;
The structural representation of the step S2 of Fig. 3 the inventive method one embodiment;
The structural representation of the step S3 of Fig. 4 the inventive method one embodiment;
The structural representation of the step S4 of Fig. 5 the inventive method one embodiment;
The structural representation of the step S5 of Fig. 6 the inventive method one embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, and obviously, described example is only the present invention's part example, instead of whole examples.The example gathering based on the present invention, those of ordinary skill in the art, not making all examples that obtain under creative work prerequisite, belong to the scope of protection of the invention.
It should be noted that, in the situation that not conflicting, the independent assortment mutually of the feature in example and example in the present invention.
The present invention is a kind of method that improves gate oxide dielectric constant, comprises the following steps:
Step S1, provide a substrate;
Step S2, in described substrate, prepare a SiO
2gate oxide;
Step S3, to described SiO
2gate oxide carries out the injection of nitrogen, makes SiO
2in partial oxygen atom replaced by nitrogen-atoms, to form SiON gate oxide;
Step S4, higher than 1000 DEG C and follow under the atmosphere of pure inert gas described SiON gate oxide is carried out to nitrogen treatment, stablize Si-N key to repair lattice damage and to form;
Step S5, under the atmosphere lower than 800 DEG C, the described SiON gate oxide after nitrogen treatment is carried out to oxidation processes, to repair SiO
2/ Si interface.
Below with reference to accompanying drawing, an example of the present invention is done to concrete explaination.
Example of the present invention is as shown in Figure 1 a kind of method that improves gate oxide dielectric constant, comprises the following steps:
Step S1, as shown in Figure 2, provides a substrate 1, and cleans;
Step S2, as shown in Figure 3 prepares a SiO in described substrate 1
2gate oxide 2; Be specially substrate 1 is carried out to thermal oxidation operation and heat treatment operation, there is the SiO of stable and uniform target thickness to prepare one deck
2gate oxide 2; Wherein, described thermal oxidation and heat treatment operation comprise that (Rapid Thermal Process, is called for short: RTP) technique and/or vertical furnace tube (Furnace) technique rapid thermal annealing; Described rapid thermal anneal process further can comprise original position steam oxidation method (In-Situ Steam Generation, be called for short: ISSG) and/or rapid thermal annealing oxidizing process (Rapid Thermal Oxidation, be called for short: RTO);
Step S3, as shown in Figure 4, to described SiO
2gate oxide 2 carries out the injection of nitrogen 3, makes SiO
2in partial oxygen atom replaced by nitrogen-atoms, to form SiON gate oxide 4; Be specially by pecvd nitride technology described SiO
2gate oxide 2 carries out the injection of nitrogen 3, makes SiO
2in partial oxygen atom by nitrogen-atoms replace form Si-N key, thereby by described SiO
2gate oxide 2 is adjusted into the SiON gate oxide 4 with certain nitrogen concentration, and described pecvd nitride technology comprises: 1. (Decoupled Plasma Nitridation, is called for short: DPN) decoupled plasma nitridation; 2. (Remote Plasma Nitridation, is called for short: RPN) remote plasma nitridation; 3. Rapid Thermal Nitrided (RTN); 4. the NO of vertical proliferation equipment, N
2o and NH
3nitrogenation treatment technology, namely vertical furnace tube (Furnace) technique;
Step S4, as shown in Figure 5, higher than 1000 DEG C and follow under the atmosphere of pure inert gas and SiON gate oxide 4 to be carried out to nitrogen 5 change and process, stablize Si-N key to repair lattice damage and to form, form stable nitrogen content and the gate oxide 6 of dielectric constant thereby have; The temperature range of described nitrogen treatment is preferably 1000 DEG C-1100 DEG C (as 1000 DEG C, 1030 DEG C, 1060 DEG C, 1100 DEG C etc.), reaction time range be 5sec-120sec(as 5sec, 40sec, 80sec, 120sec etc.); Pure inert gas in pure inert gas atmosphere is N
2(nitrogen) or Ar(argon gas) etc. inert gas;
Step S5, as shown in Figure 6 carries out oxygen 7 and changes and process change described gate oxide 6 after treatment through nitrogen 5, to repair SiO under the atmosphere lower than 800 DEG C
2/ Si interface, forms new gate oxide 8; Wherein, the temperature range of described oxidation processes is preferably 500 DEG C-800 DEG C (as 500 DEG C, 600 DEG C, 700 DEG C, 800 DEG C etc.), reaction time range be 5sec-120sec(as 5sec, 40sec, 80sec, 120sec etc.); Oxidizing gas in described oxidation processes is O
2or H
2with O
2mist.
Core of the present invention is to process by high-temperature ammonolysis the nitrogen content and the dielectric constant that improve gate oxide with low temperature oxidation technology.The present invention optimizes temperature, the atmosphere of the single high-temperature annealing process of high-temperature annealing process in traditional Si ON gate oxide preparation process.First change treatment process by high temperature and pure inert gas nitrogen 5, stablize Si-N key to repair lattice damage and to form, thereby form stable nitrogen content and dielectric constant; Then under the atmosphere of low temperature, SiON gate oxide 6 is carried out to oxygen 7 and change processing, to repair SiO
2/ Si interface.
The invention solves in preparation technology's flow process of the SiON gate oxide that current semiconductor industry accepts extensively, because the nitrogen atom concentration mixing in gate medium is high and be mainly distributed in the upper surface of gate medium, therefore the temperature to follow-up high-temperature annealing process, atmosphere and the time interval must strict be controlled, to prevent native oxide layer and organic absorption on the nitrogen impact causing of adulterating; In addition, conventional high-temperature annealing process had both easily caused the volatilization of surface nitrogen atom, can make again nitrogen-atoms obtain energy and continue diffusion, caused part nitrogen-atoms to accumulate in SiO
2with the interface of raceway groove, thereby the migration velocity of charge carrier in raceway groove is had a negative impact.
The present invention is different from the preparation method of traditional Si ON gate oxide, the present invention carries out before conventional high-temperature annealing in process at the SiON gate oxide to after described nitrogenize, first change treatment process by high temperature and pure inert gas nitrogen 5, stablize Si-N key to repair lattice damage and to form, thereby form stable nitrogen content and dielectric constant; Then under the atmosphere of low temperature (500 DEG C-800 DEG C), SiON gate oxide 6 is carried out to oxygen 7 and change processing, to repair SiO
2/ Si interface.Experimental results show that, compared with traditional high-temperature ammonolysis treatment process, the SiON gate oxide 2 that adopts the present invention to prepare not only has stable nitrogen content, and can effectively improve gate oxide nitrogen content 30% left and right, thereby make prepared gate oxide there is higher dielectric constant, realized the object that SiON gate medium dielectric coefficient is accurately cut out.
The foregoing is only preferred embodiment of the present invention; not thereby limit embodiments of the present invention and protection range; to those skilled in the art; the scheme that being equal to of should recognizing that all utilizations specification of the present invention and diagramatic content make replaces and apparent variation obtains, all should be included in protection scope of the present invention.
Claims (10)
1. a method that improves gate oxide dielectric constant, is characterized in that, said method comprising the steps of:
Step S1, provide a substrate;
Step S2, in described substrate, prepare a SiO
2gate oxide;
Step S3, to described SiO
2gate oxide carries out the injection of nitrogen, makes SiO
2in partial oxygen atom replaced by nitrogen-atoms, to form SiON gate oxide;
Step S4, higher than 1000 DEG C and follow under the atmosphere of pure inert gas described SiON gate oxide is carried out to nitrogen treatment, stablize Si-N key to repair lattice damage and to form;
Step S5, under the atmosphere lower than 800 DEG C, the described SiON gate oxide after nitrogen treatment is carried out to oxidation processes, to repair SiO
2/ Si interface.
2. the method for claim 1, is characterized in that, in step S2, prepares described SiO by rapid thermal anneal process and/or vertical furnace tube technique
2gate oxide.
3. method as claimed in claim 2, is characterized in that, described rapid thermal anneal process specifically comprises original position steam oxidation method and/or rapid thermal annealing oxidizing process.
4. method as claimed in claim 3, is characterized in that, adopts N
2o and H
2for reacting gas carries out described original position steam oxidation method; Or
Adopt O
2and H
2for reacting gas carries out described original position steam oxidation method.
5. the method for claim 1, is characterized in that, in step S3, forms described SiON by decoupled plasma nitridation process and/or remote plasma nitridation technique.
6. the method for claim 1, is characterized in that, in step S3, with NO, N
2o or NH
3for raw material, adopt vertical proliferation equipment to form described SiON.
7. the method for claim 1, is characterized in that, in step S4, the temperature range of described nitrogen treatment is 1000 DEG C-1100 DEG C, and reaction time range is 5sec-120sec.
8. the method for claim 1, is characterized in that, described pure inert gas atmosphere comprises any one in nitrogen or argon gas.
9. the method for claim 1, is characterized in that, in step S5, the temperature range of described oxidation processes is 500 DEG C-800 DEG C, and reaction time range is 5sec-120sec.
10. the method as described in claim 1 or 9, is characterized in that, adopts oxygen to carry out described oxidation processes; Or
Adopt H
2with O
2mist carry out described oxidation processes.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707550A (en) * | 2021-09-01 | 2021-11-26 | 浙江同芯祺科技有限公司 | IGBT trench gate oxide film forming process |
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2014
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| 张红伟 等: "ISSG及其氮化工艺对栅氧化层性能的改善", 《半导体制造技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113707550A (en) * | 2021-09-01 | 2021-11-26 | 浙江同芯祺科技有限公司 | IGBT trench gate oxide film forming process |
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