CN103886158B - Standard cell design method resistant to single-particle latch-up effect - Google Patents
Standard cell design method resistant to single-particle latch-up effect Download PDFInfo
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- CN103886158B CN103886158B CN201410126616.3A CN201410126616A CN103886158B CN 103886158 B CN103886158 B CN 103886158B CN 201410126616 A CN201410126616 A CN 201410126616A CN 103886158 B CN103886158 B CN 103886158B
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Abstract
A standard cell design method resistant to the single-particle latch-up effect comprises the steps that (1) trap contact protecting regions are arranged in a standard cell layout, namely areas in contact connection with traps in the standard cell layout and stretch to two sides of a transistor active area are arranged into the protecting regions, and multiple contact holes are formed in the trap contact protecting regions; (2) separation distances of the trap contact protecting regions are reduced, and the biggest separation distance (dWC) of the trap contact protecting regions is not more than 4 microns; (3) the separation distance between an NMOS and a PMOS active area is increased, and the separation distance between the NMOS and the PMOS active area is not less than 0.69 micron; (4) the distance between each trap contact protecting region and an MOS transistor source electrode is reduced, the width of a first metal layer, the width of a second metal layer and the width of a third metal layer are respectively 0.4 micron according to the design rule of the SMIC013MMRF technology, and the height of an adopted unit is 4.0 microns equivalent to the pitch widths of 10 metal layers. The method achieves reinforcing of resistance to the single-particle latch-up effect, and is low in cost, easy to implement and high in reliability.
Description
Technical field
The present invention relates to a kind of standard cell design method of anti-single particle latch-up, belong to cmos lsi space
Single particle effect guard technology.
Background technology
Space single event latch-up effect mainly appears in cmos integrated circuit, is due to its internal parasitic n-p-n-p
Structure causes.Under cmos technique, parasitic bolt lock structure is as shown in Figure 1.Under heavy ion bombardment, meeting in trap/substrate p-n junction
Simple grain electron current occurs, causes and in trap, produce voltage drop, thus leading to the parasitic triode in bolt lock structure (npnp) to be opened, shape
Become positive feedback loop, constantly increase electric current, ultimately result in device and be burned out.
The domestic anti-single particle latch design currently for cmos integrated circuit is reinforced mostly towards 0.18um cmos technique
And adopting protection ring reinforcement means, process first limits operating rate and the scale of radioprotective device, secondly protection ring
Structure can cause the larger difficulty of laying out pattern, greatly increases area, the parasitic capacitance of unit, reduces circuit speed.
Content of the invention
The technology of the present invention solution: overcome the deficiencies in the prior art, a kind of standard of anti-single particle latch-up is provided
Unit design method, the method is in the case of not affecting chip design cycle, by for library cells domain height,
The rational parameter designing of the reinforcement measure such as the optimal design-aside of layout and protection band, the reinforcing realizing anti-single particle latch-up sets
Meter, cost is little, easy realization, reliability are high.
The technology of the present invention solution:
The standard block specific design flow process of anti-single particle breech lock is as follows:
(1) combine 0.13um cmos process characteristic, analysis and research space single event latch-up effect is to cmos integrated circuit
Micromechanism of damage, and avoid triggering parasitic bolt lock structure in transistor, reduce the ultimate principle that latch-up probability occurs.
(2) it is directed to the micromechanism of damage that 0.13um cmos integrated circuit is subject to space single event latch-up effects, reinforced
Designing technique research, determines Design Method of Reinforcing.The present invention is for the main method of the domain Design of Reinforcement employing of standard block:
1) adopt trap contact protection band to design, and in protection band beat contact hole more；2) reduce the spacing of protection band as far as possible；3) as far as possible
Increase the spacing of nmos and pmos active area；4) reduce the distance away from mos pipe source electrode for the trap contact protection band.
(3) combine the feature of 0.13um cmos technique anti-single particle breech lock itself, by calculating and modeling simulation analysis,
Determine Design of Reinforcement parameter.The design parameter setting of the adopted reinforcement means of the present invention: 1) the spacing maximum of protection band is less than
4um；2) spacing of nmos and pmos active area is not less than 0.69um.
(4) combine the standard block reinforcement means of anti-single particle breech lock, determine the domain height of radioprotective standard block with
And the design parameter such as metal pitch width.The main design parameters of radioprotective standard unit picture of the present invention: 1) metal pitch width is 0.4 μ
m；2) cell layout height is 4.0 μm, is equivalent to the pitch width of 10 metals, this cell height, can anti-spoke in receiving scheme
Shooter's section.
(5) pass through with reference to the design parameter such as anti-single particle latch-up Design of Reinforcement parameter and cell layout height, right
0.13um cmos technological standardss cell layout is redesigned, and according to layout design rules, laying out pattern wiring is carried out excellent
Change.
(6) the anti-single particle breech lock standard block completing for design is modeled simulation analysis, assesses its functional performance
And the ability of anti-single particle latch-up.
Advantage compared with technology for the present invention is: a kind of anti-single particle latch-up based on 0.13um cmos technique
Standard cell design method, the method is in the case of not affecting chip design cycle, from the physical version of library cells
The Design of Reinforcement of anti-single particle latch-up is realized in figure layer face, realizes that cost is little, reliability is high, can effectively alleviate space single-particle
The impact to cmos integrated circuit for the latch-up, the capability of resistance to radiation of the digital asic of lifting.The advantage being possessed is as follows:
(1) being based on 0.18um cmos technique the exploitation of domestic radioprotective standard cell lib at present more, and this patent is to be based on
0.13um cmos technique realizes the anti-breech lock Design of Reinforcement of standard block, be can support higher based on this technique radiation hardening storehouse
Operating rate and more massive Flouride-resistani acid phesphatase asic design.
(2) layout design of the present invention anti-breech lock standard block is based on 0.13um cmos technique, high by rational domain
Degree setting, optimizes the protection design parameter such as belt distance and transistor pitch, before not affecting unit normal function and performance
Put, carry out less layout design modification, at utmost improve unit latch-up immunity, cost is little, easy realization, reliability
High.
(3) standard block is reinforced based on the anti-breech lock of present invention design, the manual splicing layout of cell layout can be carried out
Wiring, realizes the Full-custom design of radiation-hardened ic, increased the motility of design.
(4) standard block is reinforced based on the anti-breech lock of present invention design, it is possible to use the asic flow process of standard, support anti-spoke
Penetrate the design of asic, reduce the development cost of radiation hardened integrated circuit.
Brief description
Fig. 1 is parasitic bolt lock structure in body silicon cmos technique, and wherein a is the parasitic breech lock knot of body silicon cmos device inside
Composition, b is the equivalent circuit of bolt lock structure；
Fig. 2 is trap contact protection band structure；
Fig. 3 is 0.13um cmos technological standardss cell layout；
Fig. 4 is cell layout after radiation tolerance design；
Fig. 5 is that latch-up current oscillogram occurs；
Fig. 6 is that latch-up current oscillogram does not occur；
Fig. 7 is the standard cell design flow chart of anti-single particle breech lock of the present invention.
Specific embodiment
In conjunction with the analysis of single event latch-up effector mechanism, it is to avoid the ultimate principle of latch-up is:
(1) reduce trap/substrate parasitics resistance.When simple grain electron current (iwell) occurs in trap/substrate p-n junction, reduce trap
Resistance (rwell), is equivalent to and reduces the voltage drop between vertical parasitic pnp transistor emitter base in trap, thus reducing
The risk that triggering parasitic pnp transistor is opened；
(2) destroy the characteristic of parasitic bipolar pipe, reduce the current gain of transistor.Reduce parasitic transistor in bolt lock structure
Gain, be equivalent to the feedback control loop current gain reducing two parasitic transistors, it is to avoid positive feedback loop in bolt lock structure
The continuous increase of electric current.
For the micromechanism of damage to cmos integrated circuit for the space single event latch-up effect, the present invention proposes one kind and is based on
The library cells method for designing of 0.13um cmos technique anti-single particle breech lock, specific design method is as shown in Figure 7:
(1) carry out the design of trap contact protection band in standard unit picture, and in protection band beat contact hole more；
As shown in Fig. 2 realizing structure chart, in standard unit picture for what standard unit picture trap contact protection band designed
Contacting region that is connected and reaching transistor active area both sides with trap is protection band.Protection band structure is equivalent in Fig. 1 breech lock
Parallel resistance is increased, thus effectively reducing trap/substrate endoparasitism resistance value and feedback loop in trap/substrate in structure
Road gain so that the base stage of parasitic pnp pipe with power supply potential closely, it is to avoid the unlatching of vertical parasitic pnp so that just being formed
Feedback circuit, reduces the sensitivity of cmos circuit sel.The protection band simultaneously stretched out in domain is contacted with corresponding trap and is connected,
Can effectively absorb and release and fall into the energy particle being mapped in transistor, thus reduce causing the wind of breech lock because of simple grain electron current
Danger.
Meanwhile, on trap contact protection band, contact holes of beating equally can reduce resistance substrate and trap resistance, black in Fig. 2 more
Square is contact hole.On trap contact protection band, contact hole is more, and its resistance value in parallel is less.Between two contact holes
Small distance is 0.18um.
(2) reduce the spacing of protection band, realize rational parameter setting；
In Fig. 2, dwc is the spacing of protection band, reduces this spacing as far as possible, can effectively absorb the energy inciding within mos pipe
Amount particle, reduces the probability of energy particle trigger latch.But the spacing of protection band is too small, cellar area can be brought again, postpone to increase
Big performance impact, therefore, considers performance and the antiradiation protection ability of unit, is divided with tcad modeling and simulating by calculating
Analysis, on the premise of not affecting Elementary Function performance, the spacing (dwc) of protection band is maximum to be less than 4um.
(3) increase the spacing of nmos and pmos active area, realize rational parameter setting；
In Fig. 2, daa is the spacing of pmos and nmos crystalline substance active area, increases this spacing, and laterally parasitic npn is brilliant to be equivalent to increasing
The base width of body pipe, thus reducing the gain of parasitic triode, reduces the probability that breech lock occurs.But mos pipe active area
Spacing is bigger, cell layout can be caused highly to increase, area increases and postpones the performance impacts such as increase, equally, need comprehensive examining
Consider unit performance and capability of resistance to radiation, by calculating and tcad modeling simulation analysis, the spacing (daa) of nmos and pmos active area
Not less than 0.69um.
(4) reduce the distance away from mos pipe source electrode for the trap contact protection band
Reduce the distance away from source electrode for the trap contact protection band, be equal to reduce the resistance of substrate and trap, for given electric current,
The reduction of resistance value is equivalent to parasitic pnp and the emitter base voltage of npn transistor reduces, and then flows through transistor together
Electric current reduce, cmos circuit occur breech lock positive feedback effect just weakened, thus reducing circuit single event latch-up
Sensitivity.
In conjunction with the standard cell design method of above-mentioned anti-single particle breech lock, to 0.13um cmos technological standardss library unit version
Figure is redesigned, and on the basis of not affecting Elementary Function performance, realizes the Design of Reinforcement of anti-single particle latch-up.
, as shown in figure 3, metal pitch width is 0.41um, unit is high for 0.13um cmos technique unguyed library cells domain
Spend for 3.69um, be equivalent to the pitch width of 9 metals.This cell layout structure design in the case of the single particle radiation of space, easily
There is latch-up.
As shown in Figure 4 using the cell layout after said method reinforcement protection:
The pitch width of the 1st, the 2 and 3 layers of metal being adopted according to the design rule of smic013mmrf technique, the present invention is 0.4
μm.Application in conjunction with above-mentioned anti-single particle breech lock reinforcement means and parameter setting, the cell height that the present invention adopts is 4.0 μm,
Be equivalent to the pitch width of 10 metals 1.This cell height, compares and common high density designs, can also be in receiving scheme
Radioprotective means, this includes the spacing of greater area of trap contact area, broader power lead and larger n/p transistor.
Unit after Design of Reinforcement for the unguyed library cells of 0.13um cmos technique with using said method, enters
Row tcad modeling simulation analysis, predict the ability of its anti-single particle breech lock, and the worst case considering in emulation includes:
Z temperature: room temperature and 125 degrees Celsius of high temperature；
Z running voltage: standard vdd+0.1v, i.e. 1.3v (0.13um)；
The equivalent let:120mev/mg/cm2 of z vertical incidence particle；
Z protection band is smaller than equal to 4um；N/p transistor pitch is more than or equal to 0.69um；
Z particle entrance crystal pipe active area.
Fig. 5 and Fig. 6 shows that what emulation obtained occurs breech lock and the current waveform figure under latched condition does not occur.Fig. 5 is
There is the simulation result of breech lock in the unguyed library cells of 0.13um cmos technique；Fig. 6 is to adopt said method under equal conditions
Design of Reinforcement after the unlatched simulation result of unit.All there are 5 simulation curves, respectively standard block in Fig. 5 and Fig. 6 result
Vdd(power supply) electric current, the electric current of vdd to n trap, vss(ground) electric current, the electric current of vss to p trap and substrate current.
Fig. 5 result shows, after high energy particle incidence, the transistor current of business library standard unit is increased dramatically, and not
Can recover, breech lock occurs；Fig. 6 result shows, after high energy particle incidence, the transistor using said method Design of Reinforcement is occurring
Recover normal after of short duration heavy current pulse again, breech lock does not occur.
Claims (2)
1. a kind of standard cell design method of anti-single particle latch-up it is characterised in that: based on 0.13um cmos technique,
Realize step as follows:
(1) carry out the design of trap contact protection band in standard unit picture, contact with trap in standard unit picture and be connected simultaneously
The region reaching transistor active area both sides is set to protection band, and on trap contact protection band more beat contact hole, trap contacts
In protection band, contact hole is more, and its resistance value in parallel is less；
(2) reduce the spacing of trap contact protection band, the spacing (dwc) of trap contact protection band is maximum to be less than 4um；
(3) increase the spacing of nmos and pmos active area, the spacing (daa) of nmos and pmos active area is not less than 0.69um；
(4) reduce the distance away from mos pipe source electrode for the trap contact protection band, the pitch width of the 1st, 2 and 3 layers of metal of employing is 0.4 μm,
Using cell height be 4.0 μm, be equivalent to the pitch width of 10 metal levels.
2. anti-single particle latch-up according to claim 1 standard cell design method it is characterised in that: described step
Suddenly in (1), the minimum range between 2 contact holes must is fulfilled for the requirement of the design rule of smic013mmrf technique, is not less than
0.18um.
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105652176B (en) * | 2016-03-08 | 2018-06-05 | 上海华虹宏力半导体制造有限公司 | A kind of test method and device of protection ring quantity |
| CN106847332B (en) * | 2016-12-23 | 2020-09-18 | 西安空间无线电技术研究所 | SRAM (static random Access memory) storage unit SEL (self-adaptive selection) reinforcing method with low resource consumption |
| CN107947780A (en) * | 2017-12-15 | 2018-04-20 | 西安龙腾微电子科技发展有限公司 | Double internal lock Self-resetting oscillator structures applied to Flouride-resistani acid phesphatase voltage conversion chip |
| CN111009523B (en) * | 2019-10-08 | 2022-03-22 | 芯创智（北京）微电子有限公司 | Layout structure of substrate isolating ring |
| CN113571510A (en) * | 2021-07-08 | 2021-10-29 | 中国人民解放军国防科技大学 | Layout reinforcing method aiming at SET effect |
| CN118100872B (en) * | 2024-04-26 | 2024-07-02 | 天水天光半导体有限责任公司 | Double J-K positive edge trigger and semiconductor device |
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