CN103826386A - 电子电路及其制造方法以及电子部件 - Google Patents
电子电路及其制造方法以及电子部件 Download PDFInfo
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- CN103826386A CN103826386A CN201310238168.1A CN201310238168A CN103826386A CN 103826386 A CN103826386 A CN 103826386A CN 201310238168 A CN201310238168 A CN 201310238168A CN 103826386 A CN103826386 A CN 103826386A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229920005989 resin Polymers 0.000 claims abstract description 77
- 239000011347 resin Substances 0.000 claims abstract description 77
- 239000004065 semiconductor Substances 0.000 claims description 32
- 238000005538 encapsulation Methods 0.000 claims description 18
- 229920001187 thermosetting polymer Polymers 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 30
- 238000005516 engineering process Methods 0.000 description 10
- UQMRAFJOBWOFNS-UHFFFAOYSA-N butyl 2-(2,4-dichlorophenoxy)acetate Chemical compound CCCCOC(=O)COC1=CC=C(Cl)C=C1Cl UQMRAFJOBWOFNS-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000007789 sealing Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003292 diminished effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 208000034189 Sclerosis Diseases 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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Abstract
本发明目的在于提供安装有外部电极端子间的绝缘距离更小的电子部件的电子电路及其制造方法以及外部电极端子间的绝缘距离更小的电子部件。本发明的电子电路(100)的特征在于,具备印刷基板(2)和焊接在印刷基板(2)上的电子部件(1),电子部件(1)是具有露出到外部的下垫板(11A)和外部电极端子(11)的扁平封装,在印刷基板(2)和电子部件(1)之间设置有间隙(5),在印刷基板(2)上,在俯视图中在所述下垫板(11A)和外部电极端子(11)之间设置有孔(7),在间隙(5)中,在下垫板(11A)和外部电极端子(11)之间的一至少将部分填充有绝缘性树脂(6),绝缘性树脂(6)是从孔(7)注入的。
Description
技术领域
本发明涉及安装有表面安装部件的电子电路及其制造方法以及表面安装部件。
背景技术
以往,在将表面安装部件安装在印刷基板上时,在表面安装部件的外部电极端子间存在电位差的情况下,对应于该电位差,为了绝缘而在外部电极端子间确保适当的绝缘距离。
此外,在利用由空气进行的绝缘不充分的情况下,通过在外部电极端子间注入绝缘性的树脂,从而提高绝缘性(例如,专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2000-244077号公报(第5页、第3图)。
如上所述,在表面安装部件中,不是利用空气而是利用树脂进行外部电极端子间的绝缘,由此,能够将绝缘距离变小,所以,从表面安装部件的小型化的观点出发是优选的。但是,一般地外部电极端子间的间隙狭窄,所以,存在树脂的注入困难的情况。
发明内容
本发明是为了解决以上课题而提出的,目的在于提供安装有外部电极端子间的绝缘距离更小的电子部件的电子电路及其制造方法以及外部电极端子间的绝缘距离更小的电子部件。
本发明提供一种电子电路,其特征在于,具备印刷基板和焊接在印刷基板上的电子部件,电子部件是具有露出到外部的下垫板和外部电极端子的扁平封装,在印刷基板和电子部件之间设置有间隙,在印刷基板上,在俯视图中在所述下垫板和外部电极端子之间设置有孔,在间隙中,在下垫板和外部电极端子之间的至少一部分填充有绝缘性树脂,绝缘性树脂是从孔注入的。
此外,本发明提供一种电子部件,其特征在于,在封装表面具备电位不同的多个外部电极端子,在外部电极端子间沿着封装的表面设置有热硬化性树脂。
此外,本发明提供一种电子电路,具备:电子部件,在封装上表面具备电位不同的多个外部电极端子;印刷基板,与电子部件的封装下表面粘接;引线,将各个外部电极端子和印刷基板电接合,电子部件、引线、电子部件与印刷基板的粘接部以及引线与印刷基板的接合部用绝缘性树脂密封。
根据本发明,通过从设置于印刷基板的孔注入绝缘性树脂,从而绝缘性树脂可靠地填充到下垫板和外部电极端子之间的间隙至少一部分,所以,下垫板和外部电极端子的绝缘性提高。因此,在电子部件中,能够将下垫板和外部电极端子之间的绝缘距离设计得更小,所以,能够实现电子部件的小型化。此外,通过电子部件的小型化,能够实现安装有电子部件的电子电路的小型化。
此外,根据本发明,在电子部件的电位不同的外部电极端子之间,沿着封装表面涂敷有热硬化性树脂,所以,当将电子部件安装于印刷基板时,在电子部件和印刷基板的间隙中,外部电极端子间被热硬化性树脂填充。因此,电位不同的外部电极端子间的绝缘性提高,所以,能够使电位不同的外部电极端子间的绝缘距离变小,能够使电子部件小型化。此外,通过电子部件的小型化,也能够实现安装了电子部件的印刷基板小型化。
此外,根据本发明,在电子部件的封装上表面设置有外部电极端子,由此,若使用绝缘性树脂对电子部件进行密封,则封装上表面所具备的外部电极端子也被进行树脂密封。因此,外部电极端子间的绝缘性提高。即,能够使绝缘距离更小。因此,能够实现电子部件的小型化,能够使安装有电子部件的电子电路小型化。此外,由于外部电极端子设置在电子部件的封装上表面,所以,能够对接合部分的外观进行检查,在制造工序中成品率提高。
附图说明
图1是实施方式1的电子电路的剖面图以及平面图。
图2是实施方式2的电子电路的剖面图。
图3是实施方式3的电子电路的剖面图。
图4是实施方式4的电子部件以及电子电路的剖面图。
图5是实施方式5的电子电路的剖面图。
图6是前提技术的电子电路的剖面图。
具体实施方式
<前提技术>
在对本发明的实施方式进行说明之前,对作为本发明的前提的技术进行说明。在图6(a)以及图6(b)中示出作为前提技术的电子电路的剖面图。
图6(a)是在印刷基板2上安装有电子部件1的电子电路。电子部件1例如是QFN(Quad Flat Non-leaded Package)或SON(Small Outline Non-leaded Package)等扁平封装。
电子部件1所具备的外部电极端子11经由焊料3焊接于印刷基板2所具备的印刷基板侧焊环21。在电子部件1和印刷基板2之间设置有间隙5。
一般地,在将电子部件1安装在印刷基板2上之后,如图6(a)所示那样,利用绝缘性树脂4将电子部件1密封。此时,从绝缘的观点出发,优选在电子部件1和印刷基板2之间的间隙5也注入绝缘性树脂4。但是,在绝缘性树脂4的粘性高的情况下,由于电子部件1和印刷基板2的间隙5狭窄,所以,存在绝缘性树脂4未填充到间隙5中的情况。
在绝缘性树脂4未填充到间隙5中的情况下,需要考虑电子部件1的外部电极端子11间的绝缘来设计外部电极端子11间的绝缘距离L。即,在外部电极端子11间的电位差大的情况下,需要使绝缘距离L变大来设计电子部件1。通过使绝缘距离L变大,从而电子部件1大型化,存在安装有电子部件1的电子电路也大型化的问题。
此外,在图6(b)中示出电子部件1具有露出到外部的下垫板11A的情况的例子。下垫板11A与外部电极端子11同样地焊接于印刷基板侧焊环21。例如,在图6(b)中,考虑在左侧的外部电极端子11和下垫板11A之间存在电位差的情况。在该情况下,在绝缘性树脂4未填充到间隙5中的情况下,为了绝缘而需要考虑这之间的绝缘距离L来设计电子部件1。即,在外部电极端子11和下垫板11A的电位差大的情况下,需要使绝缘距离L变大来设计电子部件1。通过绝缘距离L变大,从而电子部件1大型化,存在安装有电子部件1的电子电路也大型化的问题。
<实施方式1>
<结构>
在图1(a)中示出本实施方式的电子电路100的剖面图。此外,图1(b)是在图1(a)中除去了绝缘性树脂6的电子电路100的剖面图。在本实施方式中,电子部件1与前提技术(图6(b))同样地,例如是QFN或者SON,具有露出到外部的下垫板11A和外部电极端子11。在电子部件1中,作为宽带隙半导体,搭载有例如SiC半导体元件。
印刷基板2具有印刷基板侧焊环21。电子部件1的外部电极端子11以及下垫板11A和印刷基板2的印刷基板侧焊环21隔着焊料3焊接在一起。
在图1(a)、(b)中,考虑在左侧的外部电极端子11和下垫板11A之间存在电位差的情况。在该情况下,如图1(b)所示,在印刷基板2上,在俯视图中,在左侧的外部电极端子11和下垫板11A之间设置有孔7。此外,在电子部件1和印刷基板2之间设置有间隙5。
本实施方式的电子电路100的制造方法具有:将电子部件1焊接在印刷基板2上的工序;在该工序之后,通过设置于印刷基板2的孔7,从印刷基板2背面侧向间隙5注入绝缘性树脂6的工序。其结果是,绝缘性树脂6填充到间隙5中,成为图1(a)的状态。
此外,如图1(a)所示,在注入绝缘性树脂6时,也可以同时用绝缘性树脂6对印刷基板2的背面进行涂覆。
此外,与在前提技术中利用绝缘性树脂4对电子部件1的表面侧进行密封同样地,在本实施方式中,也可以利用绝缘性树脂对电子部件1的表面侧进行密封。
在本实施方式中,在存在电位差的下垫板11A和外部电极端子11间的间隙5中填充有绝缘性树脂6,由此,下垫板11A和外部电极端子11间更加可靠地被绝缘。因此,在电子部件1中,能够将下垫板11A和外部电极端子11间的绝缘距离L设计得比前提技术小。
此外,在本实施方式中,如图1(a)所示,绝缘性树脂6完全填充间隙5。这样,从绝缘的观点出发,最优选间隙5被绝缘性树脂6完全填充,但是,即使在填充了间隙5的一部分的情况下,也能够使下垫板11A和外部电极端子11间的沿面距离变大,所以,能够提高下垫板11A和外部电极端子11间的绝缘性,能够使绝缘距离L变小。
此外,在图1(c)中示出本实施方式的电子电路100的平面图的一例。例如,在左侧的列的外部电极端子11和下垫板11A之间存在电位差的情况下,通过使孔7为狭缝形状,从而能够将绝缘性树脂6效率良好地注入到左侧的列的外部电极端子11和下垫板11A之间。
此外,在本实施方式中,对于电子部件1来说,作为宽带隙半导体元件,搭载了SiC半导体元件,但是,也可以是GaN半导体元件等。
<效果>
本实施方式的电子电路100的特征在于,具有印刷基板2和焊接在印刷基板2上的电子部件1,电子部件1是具有露出到外部的下垫板11A和外部电极端子11的扁平封装,在印刷基板2和电子部件1之间设置有间隙5,在印刷基板2上,在俯视图中,在下垫板11A和外部电极端子11之间设置有孔7,在间隙5中,绝缘性树脂6填充于下垫板11A和外部电极端子11之间的至少一部分,绝缘性树脂6是从孔7注入的。
因此,通过从设置于印刷基板2的孔7注入绝缘性树脂6,从而绝缘性树脂6可靠地填充于下垫板11A和外部电极端子11之间的间隙5的至少一部分,所以,下垫板11A和外部电极端子11之间的绝缘性提高。因此,在电子部件1中,能够将下垫板11A和外部电极端子11间的绝缘距离L设计得比前提技术(图6(b))小,所以,能够实现电子部件1的小型化。此外,通过电子部件1的小型化,能够实现安装有电子部件1的电子电路100的小型化。
此外,本实施方式的电子电路100的特征在于,电子部件1具有宽带隙半导体元件。
因此,一般地,对于宽带隙半导体元件来说,被施加高电压来使用,所以,在下垫板11A和外部电极端子11之间产生大的电位差。因此,通过利用绝缘性树脂6对下垫板11A和与下垫板11A产生大的电位差的外部电极端子11间的间隙5进行填充,从而显著地表现出绝缘性的提高,所以,能够特别有效地减小绝缘距离L。
此外,本实施方式的电子电路100的制造方法具有:将电子部件1焊接到设置有孔7的印刷基板2上的工序;在该工序之后,从孔7注入绝缘性树脂6的工序。
因此,在印刷基板2上设置孔7并且通过孔7将绝缘性树脂6注入到间隙5,由此,能够容易将绝缘树脂6填充到间隙5中。
<实施方式2>
在图2中示出本实施方式的电子电路200的剖面图。在本实施方式的电子电路200中,将实施方式1中的电子电路100容纳在外壳40内部。
在本实施方式中,与实施方式1同样地,假定在下垫板11A和图2左侧的外部电极端子11之间存在电位差。
在外壳40内部以及电子电路100与印刷基板2的间隙5中填充有绝缘性树脂6。在制造本实施方式的电子电路200时,在向外壳40中注入绝缘性树脂6的工序中,同时通过孔7也向电子电路100的间隙5中注入绝缘性树脂6。
本实施方式的电子电路200的特征在于,还具有容纳印刷基板2以及电子部件1的外壳40,绝缘性树脂6是填充到外壳40中的绝缘性树脂。
因此,在向外壳40中填充绝缘性树脂6时,通过孔7也向在外壳40中容纳的电子电路100的间隙5中填充绝缘性树脂6。因此,在将电子电路100容纳在外壳40中的情况下,能够将树脂密封工序简单化。
<实施方式3>
在图3中示出本实施方式的电子电路300的剖面图。本实施方式的电子电路300具有实施方式1的电子电路100和与该电子电路100电连接的半导体模块。在半导体模块中,作为功率半导体元件30I,具有例如SiC半导体元件。
首先,对半导体模块的结构进行说明。半导体模块的外壳由壳体30A和基底板30B构成。在壳体30A中,中继端子30C和功率端子30D被一体化或者被埋入。
在基底板30B上,利用焊料30F接合有在两面形成了布线图形30G的绝缘基板30J。在绝缘基板30J上隔着焊料30F接合有SiC半导体元件(30I)。
电子电路容纳在半导体模块的外壳内。电子电路100的印刷基板2和功率半导体元件30I经由中继端子30C以及引线30H而连接。在电子电路100的印刷基板2上设置有接口端子30E。
此外,功率半导体元件30I和功率端子经由布线图形30G利用引线30H进行连接。
此外,半导体模块的壳体30A内部利用例如硅胶4A进行填充。
此外,本实施方式的电子电路300采用电子电路100被容纳在半导体模块的壳体30A中的结构,但是,如果是电子电路100与半导体模块电连接的结构,则不限于此。
<效果>
本实施方式的电子电路300的特征在于,还具备与印刷基板2电连接的半导体模块,半导体模块包含功率半导体元件30I。
因此,即便在电子电路100所具有的电子部件1的下垫板11A和例如图3左侧的外部电极端子11之间产生半导体模块所具有的功率半导体元件30I的电位差的情况下,由于在间隙5中填充有绝缘性树脂6,所以,与绝缘性树脂6未填充到间隙5中的情况相比,也能够使绝缘距离L较小。因此,能够实现电子部件1的小型化,能够实现具有电子部件1的电子电路100的小型化。即,能够使具有电子电路100的电子电路300小型化。此外,在电子电路100容纳在半导体模块的壳体中的情况下,能够实现半导体模块本身的小型化。
此外,本实施方式的电子电路300的特征在于,功率半导体元件30I包括SiC半导体元件。
因此,一般地,对于SiC半导体元件来说,被施加高电压来使用的情况较多,所以,能够使电子部件1的绝缘距离L更小,能够将电子电路100以及电子电路300进一步小型化。
<实施方式4>
在图4(a)中示出本实施方式的电子部件400的剖面图。此外,在图4(b)中示出安装有本实施方式的电子部件400的印刷基板2的剖面图。
本实施方式的电子部件400是例如QFN或者SON等扁平封装,在电子部件400的封装表面具有外部电极端子11。
在图4(a)中,考虑在左右的外部电极端子11间存在电位差的情况。在左右的外部电极端子11之间,沿着电子部件400的封装的表面涂敷有热硬化性树脂4B。此外,在外部电极端子11表面也以残留与焊料3进行接合的一部分的方式涂敷有热硬化性树脂4B。
将具有以上结构的电子部件400安装在印刷基板2上。在印刷基板2上设置有印刷基板侧焊环21,外部电极端子11和印刷基板侧焊环21利用焊料3焊接在一起。通过焊接时的热处理使热硬化性树脂4B硬化,电子部件400和印刷基板2的间隙被热硬化性树脂4B填充。
这样,左右的外部电极端子11间被热硬化性树脂4B填充,所以,左右的外部电极端子11间的绝缘性提高。即,能够将外部电极端子11间的绝缘距离L变小,能够实现电子部件400的小型化。
此外,在本实施方式中,如实施方式1那样,电子部件1也可以具有露出到外部的下垫板。在外部电极端子11和下垫板之间存在电位差的情况下,在外部电极端子11和下垫板之间沿着电子部件400的封装的表面涂敷热硬化性树脂4B,由此,能够得到与上述的效果相同的效果。
<效果>
本实施方式的电子部件400的特征在于,在封装表面具有电位不同的多个外部电极端子11,在外部电极端子11间,沿着封装的表面设置有热硬化性树脂4B。
因此,由于在电子部件400的电位不同的外部电极端子11间沿着封装表面涂敷有热硬化性树脂4B,所以,在将电子部件400安装到印刷基板2上时,在电子部件400和印刷基板2的间隙中,外部电极端子11间被热硬化性树脂4B填充。因此,电位不同的外部电极端子11间的绝缘性提高,所以,能够使电位不同的外部电极端子11间的绝缘距离L变小,能够将电子部件400小型化。此外,通过电子部件400的小型化,也能够实现安装有电子部件400的印刷基板2的小型化。
<实施方式5>
在图5中示出本实施方式的电子电路500的剖面图。电子电路500具有:电子部件10,在封装上表面具有外部电极端子11;印刷基板2,与电子部件10的封装下表面粘接;引线8,将外部电极端子11和印刷基板2电接合。在印刷基板2表面形成有引线焊盘22。
此外,在图5的电子部件10中,左右的外部电极端子11间的电位不同。
对电子电路500的制造方法进行说明。首先,将电子部件10的未形成有外部电极端子11的一侧的面即封装下表面隔着粘接部9粘接于印刷基板2。在粘接中使用能够耐受电子部件10工作时的发热的粘接剂。
接着,将引线8的一端与外部电极端子11焊接,将引线8的另一端与引线焊盘22焊接,由此,将电子部件10的外部电极端子11和印刷基板2电接合。引线8例如是铜线。
此外,也能够利用引线键合对引线8进行接合。在该情况下,引线8例如是铝线,利用超声波进行接合。
接着,如图5所示,利用绝缘性树脂4对电子电路500的表面侧进行密封。即,利用绝缘性树脂4将电子部件10、引线8、电子部件10和印刷基板2的粘接部9以及引线8和印刷基板2的接合部(即,引线焊盘22)密封。经过以上的制造工序,制造出本实施方式的电子电路500。
在本实施方式的电子电路500中,电压不同的外部电极端子11间被绝缘性树脂4密封,所以,外部电极端子11间的绝缘性提高。因此,能够使外部电极端子11间的绝缘距离L变小。
<效果>
本实施方式的电子电路500的特征在于,具有:电子部件10,在封装上表面具有电位不同的多个外部电极端子11;印刷基板2,与电子部件10的封装下表面粘接;引线8,将各个外部电极端子11和印刷基板2电接合,电子部件10、引线8、电子部件10与印刷基板2的粘接部9以及引线8与印刷基板2的接合部(即,引线焊盘22)被绝缘性树脂4密封。
因此,在电子部件10的封装上表面设置外部电极端子11,由此,在用绝缘性树脂4对电子部件10进行密封时,在封装上表面所具有的外部电极端子11也被进行树脂密封。因此,外部电极端子11间的绝缘性提高。即,与外部电极端子11间的间隙未被绝缘性树脂填充的前提技术(图6(a))相比较,能够使绝缘距离L变小。因此,能够实现电子部件10的小型化,能够将安装有电子部件10的电子电路500小型化。此外,由于外部电极端子11设置在电子部件10的封装上表面,所以,能够检查接合部分的外观,在制造工序中成品率提高。
此外,本实施方式的电子电路500的特征在于,引线8是铜并且利用焊料进行接合。因此,通过利用焊料进行接合,从而能够提高接合的强度。
此外,本实施方式的电子电路500的特征在于,引线8是铝并且利用超声波进行接合。因此,在电子部件10为小型并且外部电极端子11的接合面小的情况下,也能够利用引线键合进行引线8的接合。
此外,本发明能够在该发明的范围内将各实施方式自由组合或者将各实施方式适当地变形、省略。
附图标记说明:
1、10、400 电子部件
2 印刷基板
3、30F 焊料
4、6 绝缘性树脂
4A 硅胶
4B 热硬化性树脂
5 间隙
7 孔
8、30H 引线
9 粘接部
11 外部电极端子
11A 下垫板
21 印刷基板侧焊环
22 引线焊盘
30A 壳体
30B 基底板
30C 中继端子
30D 功率端子
30E 接口端子
30G 布线图形
30I 功率半导体元件
30J 绝缘基板
40 外壳
100、200、300、500 电子电路。
Claims (10)
1.一种电子电路,其特征在于,具备:
印刷基板;以及
电子部件,焊接在所述印刷基板上,
所述电子部件是具有露出到外部的下垫板和外部电极端子的扁平封装,
在所述印刷基板和所述电子部件之间设置有间隙,
在所述印刷基板上,在俯视图中在所述下垫板和所述外部电极端子之间设置有孔,
在所述间隙中,在所述下垫板和所述外部电极端子之间的至少一部分填充有绝缘性树脂,
所述绝缘性树脂是从所述孔注入的。
2.如权利要求1所述的电子电路,其特征在于,
还具备容纳所述印刷基板以及所述电子部件的外壳,
所述绝缘性树脂是填充到所述外壳中的绝缘性树脂。
3.如权利要求1或2所述的电子电路,其特征在于,
所述电子部件具备宽带隙半导体元件。
4.如权利要求1所述的电子电路,其特征在于,
还具备与所述印刷基板电连接的半导体模块,
所述半导体模块包含功率半导体元件。
5.如权利要求4所述的电子电路,其特征在于,
所述功率半导体元件包含SiC半导体元件。
6.一种电子电路的制造方法,所述电子电路具备印刷基板和焊接在所述印刷基板上的电子部件,所述电子部件是具有露出到外部的下垫板和外部电极端子的扁平封装,在所述印刷基板和所述电子部件之间设置有间隙,在所述印刷基板上,在俯视图中在所述下垫板和所述外部电极端子之间设置有孔,在所述间隙中,在所述下垫板和所述外部电极端子之间的至少一部分填充有绝缘性树脂,所述绝缘性树脂是从所述孔注入的,所述电子电路的制造方法的特征在于,具备:
(a)将所述电子部件焊接到设置有所述孔的所述印刷基板上的工序;以及
(b)在所述工序(a)之后,从所述孔注入所述绝缘性树脂的工序。
7.一种电子部件,其特征在于,
在封装表面具备电位不同的多个外部电极端子,
在所述外部电极端子间沿着封装的表面设置有热硬化性树脂。
8.一种电子电路,其特征在于,具备:
电子部件,在封装上表面具备电位不同的多个外部电极端子;
印刷基板,与所述电子部件的封装下表面粘接;以及
引线,将各个所述外部电极端子和所述印刷基板电接合,
所述电子部件、所述引线、所述电子部件与所述印刷基板的粘接部以及所述引线与所述印刷基板的接合部用绝缘性树脂密封。
9.如权利要求8所述的电子电路,其特征在于,
所述引线是铜并且利用焊料进行接合。
10.如权利要求8所述的电子电路,其特征在于,
所述引线是铝并且利用超声波进行接合。
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