CN103765597B

CN103765597B - Thin film transistor (TFT) and preparation method thereof, array base palte, display device and barrier layer

Info

Publication number: CN103765597B
Application number: CN201380002182.XA
Authority: CN
Inventors: 刘翔; 王刚
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2012-11-02
Filing date: 2013-10-30
Publication date: 2016-09-28
Anticipated expiration: 2033-10-30
Also published as: CN103765597A

Abstract

The invention discloses a kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device, in order to improve the electric property of thin film transistor (TFT), improve the image quality of display device display image.The thin film transistor (TFT) that the present invention provides includes: grid, source electrode, drain electrode, semiconductor layer, gate insulator and the first metal barrier being positioned on substrate；Described gate insulator is between described grid and described semiconductor layer；Described first metal barrier is between described source electrode, drain electrode and gate insulator；Wherein, described first metal barrier is arranged with layer with described semiconductor layer, and described first metal barrier stops the phase counterdiffusion of the material forming source electrode and drain electrode and the material forming grid.

Description

Thin film transistor (TFT) and preparation method thereof, array base palte, display device and barrier layer

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of thin film transistor (TFT) and preparation method thereof, battle array Row substrate, display device and barrier layer.

Background technology

In Display Technique field, panel display apparatus, as liquid crystal display (Liquid Crystal Display, LCD) and display of organic electroluminescence (Organic Light Emitting Display, OLED), because of It has the advantages such as light, thin, low-power consumption, high brightness, and high image quality, occupies in flat display field Consequence.The especially panel display apparatus of large scale, high-resolution, and high image quality, such as liquid Brilliant TV, has already taken up leading position in current flat panel display market.

At present, the delay of picture signal becomes restriction large scale, high-resolution and high image quality flat pannel display dress One of key factor put.Specifically, postponing of picture signal is main by the grid on substrate, gate line, Or the signal resistance R such as data wire and relevant capacitor C determine.Along with the continuous increase of sized display, Resolution improves constantly, and the signal frequency that drive circuit applies also improves constantly, and the delay of picture signal is more Come the most serious.Showing the stage at image, gate line is opened, and pixel is charged, due to the delay of picture signal, The charging of some pixel is insufficient, causes the brightness irregularities of image display picture, has a strong impact on the aobvious of image Show quality.Reducing grid, gate line, the resistance of data wire etc. can reduce the delay of picture signal, changes The image quality of kind image.

At present, the method for the resistance reducing gate line and data wire mainly uses the metallic copper that resistance is relatively low (Cu) gate line and data wire are made.But have the disadvantage in that

Copper (Cu) metal ion easily spreads, and is easy to the most at relatively high temperatures be diffused into gate protection In layer, semiconductor layer or passivation layer, have a strong impact on thin film transistor (TFT) (Thin Film Transistor, TFT) performance.Especially in TFT subsequent high temperature heating technique, the activity increasing of copper (Cu) ion Add, insulation barrier can be passed through and penetrate into semiconductor layer, have a strong impact on TFT performance so that image Image quality is worse, even destroys the normal work of TFT.

TFT and manufacture method on existing substrate can cause TFT hydraulic performance decline, and image quality is poor Problem.

Summary of the invention

The embodiment of the present invention provides a kind of thin film transistor (TFT) and preparation method thereof, array base palte, display device And barrier layer, in order to improve the performance of TFT, improve the image quality of image.

For achieving the above object, the thin film transistor (TFT) that the embodiment of the present invention provides, including:

Grid, source electrode, drain electrode, semiconductor layer, gate insulator and the first metal being positioned on substrate Barrier layer；Described gate insulator is between described grid and described semiconductor layer；Described first metal Barrier layer is between described source electrode, drain electrode and gate insulator；Wherein, described first metal barrier Arranging with layer with described semiconductor layer, described first metal barrier stops formation source electrode and the material of drain electrode With the phase counterdiffusion of the material forming grid, improve the performance of TFT, improve the image quality of image.

Such as, it is preferred that the etching also included between described source electrode, drain electrode and described semiconductor layer Barrier layer, has the shadow to semiconductor layer when the TFT of etching barrier layer is possible to prevent etching source and drain electrode Ring.

Such as, it is preferred that described first metal barrier is arranged with the insulation of described semiconductor layer.

Such as, it is preferred that the material of described formation source electrode and drain electrode and formed grid material at least One of relatively low for the resistivity of copper or copper alloy, copper or copper alloy, the delay of picture signal can be reduced, Improve the image quality of image.

Such as, it is preferred that when described TFT is metal-oxide TFT, described semiconductor layer is gold Belong to oxide semiconductor layer.

Such as, it is preferred that described first metal barrier uses the material system identical with described semiconductor layer Forming, the most described metal oxide semiconductor layer has prevention and forms source electrode and the material of drain electrode and shape Becoming the mutual diffusion function of the material of grid, secondly same material forms the first metal barrier and quasiconductor Layer can simplify the structure of TFT, saves fabrication processing.

Such as, it is preferred that described first metal barrier is to have prevention to form source electrode and the material of drain electrode Copper film layer is aoxidized with forming the copper oxide of mutual diffusion function of material of grid, copper nitride or nitrogen.

Such as, it is preferred that described first metal barrier can also use differs with described semiconductor layer Metal oxide semiconductor material be made, owing to metal oxide semiconductor material can stop shape Become the material of source electrode and drain electrode and the phase counterdiffusion of the material forming grid, it is possible to achieve improve the property of TFT Can, improve the image quality of image.

Such as, it is preferred that described thin film transistor (TFT) also includes: the second metal barrier, described second gold medal Genus barrier layer is between described first metal barrier and described source electrode, drain electrode, and described second metal hinders Barrier stops the phase counterdiffusion of the material forming source electrode and drain electrode and the material forming grid, can more enter one Step improves the performance of TFT, improves the image quality of image.

Such as, it is preferred that the material of described formation source electrode and drain electrode is copper or copper alloy, copper or copper alloy Resistivity relatively low, the delay of picture signal can be reduced, improve the image quality of image.

Such as, it is preferred that described second metal barrier is to have prevention to form source electrode and the material of drain electrode With formed the copper oxide of mutual diffusion function of material of grid, copper nitride, or nitrogen oxidation copper film layer.

Such as, it is preferred that described second metal barrier uses has prevention formation source electrode and the material of drain electrode The metal oxide semiconductor material of the mutual diffusion function of the material expected and form grid is made.

Such as, it is preferred that the structure of described thin film transistor (TFT) is:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Described semiconductor layer and the first metal barrier are positioned on described gate insulator；

Described etching barrier layer is positioned on described semiconductor layer；

Described second metal barrier is positioned on described semiconductor layer and the first metal barrier；

Described source-drain electrode layer is positioned on described second metal barrier；

Or the structure of described thin film transistor (TFT) is:

Described source-drain electrode layer is positioned on described substrate；

Described second metal barrier is positioned on described source-drain electrode layer；

Described etching barrier layer is positioned on described second metal barrier；

Described semiconductor layer and the first metal barrier are positioned on described etching barrier layer；

Described gate insulator is positioned on described semiconductor layer；

Described grid is positioned on described gate insulator.

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Described source electrode and drain electrode are positioned on described first metal barrier；

Or the structure of described thin film transistor (TFT) is:

Described source electrode and drain electrode are positioned on described substrate；

Described semiconductor layer and the first metal barrier are positioned in described source electrode and drain electrode；

Described gate insulator is positioned on described semiconductor layer and the first metal barrier；

Described grid is positioned on described gate insulator.

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Or the structure of described thin film transistor (TFT) is:

Described second metal barrier is positioned in described source electrode and drain electrode；

Described semiconductor layer and the first metal barrier are positioned on described second metal barrier；

Described grid is positioned on described gate insulator.

Such as, it is preferred that described first metal barrier is positioned at the position corresponding with described source electrode and drain electrode Put, simplify the structure of TFT as much as possible.

Such as, it is preferred that described second metal barrier is positioned at the position corresponding with described source electrode and drain electrode Put, simplify the structure of TFT as much as possible.

The embodiment of the present invention provides a kind of array base palte, it is characterised in that include above-mentioned being provided only with first The thin film transistor (TFT) of metal barrier, described first metal barrier stops formation source electrode and the material of drain electrode With the phase counterdiffusion of the material forming grid, improve the performance of TFT, improve the image quality of image.

Such as, it is preferred that described array base palte also includes: data wire and gate line, described data wire with The source electrode of described thin film transistor (TFT) is connected, and described gate line is connected with the grid of thin film transistor (TFT)；

Described first metal barrier is positioned at the position corresponding with described source electrode, drain electrode and data wire；Or Person

Described first metal barrier is positioned at the position corresponding with described source electrode, drain electrode and gate line；Or Person

Described first metal barrier is positioned at corresponding with described source electrode, drain electrode, gate line and data wire Position, described first metal barrier stops the material forming source electrode and drain electrode and the material forming grid Phase counterdiffusion, improves the performance of TFT, improves the image quality of image, is also prevented from forming gate line sum simultaneously According to the phase counterdiffusion of the material of line, improve the performance of TFT, improve the image quality of image.

The embodiment of the present invention provides a kind of array base palte, is provided with the first metal barrier and the including above-mentioned The thin film transistor (TFT) of two metal barriers, improves the performance of TFT further, improves the image quality of image.

Described first metal barrier is positioned at the position corresponding with described source electrode, drain electrode and data wire, or Person is positioned at the position corresponding with described source electrode, drain electrode and gate line, or is positioned at and described source electrode, leakage The position that pole, gate line are corresponding with data wire；And/or

Described second metal barrier is positioned at the position corresponding with described source electrode, drain electrode and data wire, or Person is positioned at the position corresponding with described source electrode, drain electrode and gate line, or is positioned at and described source electrode, leakage The position that pole, gate line are corresponding with data wire, arranging of the second metal barrier can be avoided further Form the phase counterdiffusion of the material of source electrode, drain electrode, gate line and data wire, improve TFT further Performance, improve image image quality.

The embodiment of the present invention provides a kind of display device, and including above-mentioned array base palte, this array base palte is only It is provided with the thin film transistor (TFT) of the first metal barrier, it is possible to achieve a kind of signal delay is less and image Image quality preferably display device.

The embodiment of the present invention provides a kind of display device, and including above-mentioned array base palte, this array base palte is same Time be provided with the first metal barrier and the thin film transistor (TFT) of the second metal barrier.

The embodiment of the present invention provides the manufacture method of a kind of thin film transistor (TFT), including:

Form the figure including grid, source electrode, drain electrode and semiconductor layer；Formation include gate insulator with And first figure of metal barrier；

Described gate insulator between described grid and semiconductor layer, described first metal barrier position Between described source electrode, drain electrode and gate insulator, wherein, described first metal barrier and described half Conductor layer is arranged with layer.Described first metal barrier stops the material forming source electrode and drain electrode and forms grid The phase counterdiffusion of the material of pole, improves the performance of TFT, improves the image quality of image.

Such as, it is preferred that also include the figure forming etching barrier layer, described etching barrier layer is positioned at institute State between semiconductor layer and source electrode, drain electrode, have the TFT of etching barrier layer be possible to prevent etching source and Impact on semiconductor layer during drain electrode.

Such as, it is preferred that when described TFT is metal-oxide TFT, described semiconductor layer is by gold Belong to oxide semiconductor material to be made.

Such as, it is preferred that also include the figure forming the second metal barrier, described second metal barrier Layer, between described first metal barrier and described source electrode, drain electrode, can further improve TFT Performance, improve image image quality.

Such as, it is preferred that described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator Layer, the figure of the first metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

Use patterning processes to be formed on the substrate being formed with described gate patterns and include gate insulator Figure；

Use to be formed on the substrate being formed with described gate insulator layer pattern with a patterning processes and include Semiconductor layer and the figure of the first metal barrier；

Use with patterning processes shape on the substrate being formed with semiconductor layer and the first metal barrier Become to include the figure of source electrode, drain electrode；

Or described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator, the first gold medal Belong to the figure on barrier layer, for:

Use and on substrate, form, with a patterning processes, the figure including source electrode, drain electrode；

Use to be formed on the substrate being formed with described source electrode, drain electrode with a patterning processes and include quasiconductor Layer and the figure of the first metal barrier；

Use patterning processes on the substrate being formed with described semiconductor layer and the first metal barrier layer pattern Form the figure including gate insulator；

Use patterning processes to be formed on the substrate being formed with described gate insulator layer pattern and include grid Figure.

Such as, it is preferred that described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator Layer, etching barrier layer, the first metal barrier and the figure of the second metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

Patterning processes is used to be formed on the substrate being formed with semiconductor layer and the first metal barrier layer pattern Figure including etching barrier layer；

Use formed on the substrate being formed with etch stopper layer pattern with patterning processes include source electrode, Drain electrode and the figure of the second metal barrier；

Or described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator, etching resistance Barrier, the first metal barrier and the figure of the second metal barrier, for:

Use to be formed on substrate with a patterning processes and include source electrode, drain electrode and the second metal barrier Figure；

Use patterning processes on the substrate being formed with described source electrode, drain electrode and the second metal barrier layer pattern Form the figure including etching barrier layer；

Use to be formed on the substrate being formed with described etch stopper layer pattern with a patterning processes and include Semiconductor layer and the figure of the first metal barrier；

Such as, it is preferred that described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator Layer, the first metal barrier and the figure of the second metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

Use patterning processes to be formed on the substrate being formed with described gate insulator layer pattern and include quasiconductor The figure of layer；

Patterning processes is used to form the first metal barrier on the substrate being formed with described semiconductor layer figure The figure of layer；

Use to be formed on the substrate being formed with the first metal barrier layer pattern with a patterning processes and include Source electrode, drain electrode and the figure of the second metal barrier；

Or described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator, the first gold medal Belong to barrier layer and the figure of the second metal barrier, for:

Patterning processes is used to be formed with described source electrode, drain electrode and the substrate of the second metal barrier layer pattern Upper formation includes the figure of semiconductor layer；

Use patterning processes to be formed on the substrate being formed with described first metal barrier layer pattern and include grid The figure of pole insulating barrier；

Such as, it is preferred that the material of described formation source electrode and drain electrode be resistivity relatively low copper or copper alloy.

Such as, it is preferred that the same patterning processes of described employing is at the base being formed with etch stopper layer pattern On plate, formation includes that the figure of source electrode, drain electrode and the second metal barrier is:

Coating process is used to be formed with described etch stopper layer pattern or the first metal barrier layer pattern Described copper metal or tin-copper alloy film layer is formed on substrate；Formed at the beginning of described copper metal or tin-copper alloy film layer Begin, in the time period, in cavity, to be passed through the mixed gas of the oxygen of preset ratio, nitrogen or oxygen and nitrogen Form copper or the oxide of copper alloy, nitride or nitrogen oxides are used for forming the second metal barrier, remove Copper metal or tin-copper alloy film layer outside described second metal barrier are used for forming source electrode and drain electrode；Use Single exposure, development, chemical wet etching step form described source electrode, drain electrode and the second metal barrier Figure；

Described employing is formed on the substrate being formed with the first metal barrier layer pattern with a patterning processes Figure including source electrode, drain electrode and the second metal barrier is:

Coating process is used to be formed with described etch stopper layer pattern or the first metal barrier layer pattern Described copper metal or tin-copper alloy film layer is formed on substrate；Formed at the beginning of described copper metal or tin-copper alloy film layer Begin, in the time period, in cavity, to be passed through the mixed gas of the oxygen of preset ratio, nitrogen or oxygen and nitrogen Form copper or the oxide of copper alloy, nitride or nitrogen oxides are used for forming the second metal barrier, remove Copper metal or tin-copper alloy film layer outside described second metal barrier are used for forming source electrode and drain electrode；Use Single exposure, development, chemical wet etching step form described source electrode, drain electrode and the second metal barrier Figure.

Such as, it is preferred that described employing is formed on substrate with a patterning processes includes source electrode, drain electrode And second the figure of metal barrier be:

Coating process is used to form described copper or tin-copper alloy film layer on substrate；Forming described copper or copper conjunction In the end time section of golden membranous layer, in cavity, it is passed through the oxygen of preset ratio, nitrogen or oxygen and nitrogen Mixed gas form copper or the oxide of copper alloy, nitride or nitrogen oxides for forming the second metal Barrier layer, copper metal in addition to described second metal barrier or tin-copper alloy film layer be used for being formed source electrode and Drain electrode；Single exposure, development, chemical wet etching step is used to form described source electrode, drain electrode and the second gold medal Belong to the figure on barrier layer.

The embodiment of the present invention provides a kind of barrier layer, be used for described in be provided only with the battle array of the first metal barrier Row substrate stops the first metal barrier of the diffusion of copper or copper alloy.

Such as, it is preferred that the material on described barrier layer be have stop the material forming source electrode and drain electrode with Form the metal-oxide of mutual diffusion function, metal nitride or the metal oxynitride of the material of grid Thing.

Such as, it is preferred that described metal-oxide is to have prevention to form source electrode and the material of drain electrode and shape Become indium gallium zinc oxide or the copper oxide of the mutual diffusion function of the material of grid.

Such as, it is preferred that described metal nitride is to have prevention to form source electrode and the material of drain electrode and shape Become the copper metal nitride of the mutual diffusion function of the material of grid.

Such as, it is preferred that described metal oxynitride be have stop the material forming source electrode and drain electrode with Form the copper metal oxynitride of the mutual diffusion function of the material of grid.

The embodiment of the present invention provides a kind of barrier layer, for described be provided with simultaneously the first metal barrier and The array base palte of the second metal barrier stops the diffusion of copper or copper alloy the first metal barrier and/ Or second metal barrier.

The thin film transistor (TFT) that the embodiment of the present invention provides, is arranged between source electrode, drain electrode and gate insulator There are the first metal barrier, described first metal barrier to stop and form source electrode and the material of drain electrode and formation The phase counterdiffusion of the material of grid, improves the performance of TFT, improves the image quality of image.Further, exist Second metal barrier, described second metal barrier are set between source electrode, drain electrode and the first metal barrier Layer stops the phase counterdiffusion of the material forming source electrode and drain electrode and the material forming grid further, improves The performance of TFT, improves the image quality of image.

Accompanying drawing explanation

The array base-plate structure schematic top plan view that Fig. 1 provides for the embodiment of the present invention one；

Fig. 2 be the TFT shown in Fig. 1 A-B to schematic cross-section；

Fig. 3 is the TFT structure schematic diagram with the second metal barrier shown in Fig. 2；

The array base-plate structure schematic top plan view that Fig. 4 provides for the embodiment of the present invention two；

Fig. 5 be the TFT shown in Fig. 4 A-B to sectional view；

Fig. 6 is the TFT structure schematic diagram that the TFT shown in Fig. 5 has the second metal barrier；

The TFT structure schematic diagram that Fig. 7 provides for embodiment two；

The array base palte schematic top plan view that Fig. 8 provides for the embodiment of the present invention four；

Fig. 9 is the schematic cross-section in C-D direction of the array base palte shown in Fig. 8；

The array base palte schematic cross-section that Figure 10 provides for the embodiment of the present invention four；

The manufacture method schematic flow sheet of the bottom gate type TTF that Figure 11 provides for the embodiment of the present invention six；

The manufacture method schematic flow sheet of the top gate type TTF that Figure 12 provides for the present invention.

Detailed description of the invention

Embodiments provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte, display dress Put and a kind of barrier layer, in order to improve the performance of TFT, improve the image quality of image.

Usually, grid that TFT at least includes being positioned on substrate, source electrode, drain electrode, semiconductor layer, with And the gate insulator between described grid and semiconductor layer.Source electrode and drain electrode are properly termed as source-drain electrode Layer, the film layer of source-drain electrode layer place TFT is referred to as SD layer.Further, TFT also includes being positioned at partly leading Etching barrier layer between body layer and source electrode and drain electrode.Typically, for non-crystalline silicon tft and polysilicon Without arranging etching barrier layer in TFT.For metal-oxide TFT, in order to prevent etching source and leakage The semiconductor layer formed by metal-oxide is impacted by pole figure, can arrange etching barrier layer, but It is also to be not excluded for certain form of metal-oxide to need not arrange etching barrier layer as semiconductor layer.This The TFT that inventive embodiments provides also includes the tool between described source electrode and drain electrode and gate insulator There is the barrier layer stoping the material forming source electrode and drain electrode with the mutual diffusion function of the material forming grid, Described barrier layer is the first metal barrier, and described first metal barrier stops and forms source electrode and drain electrode Material and the phase counterdiffusion of the material forming grid, improve the performance of TFT, improve the image quality of image.

The TFT that the embodiment of the present invention provides, the material of at least one source electrode, drain electrode, grid is resistivity Relatively low copper or copper alloy.Being certainly not limited to this, the purpose of the embodiment of the present invention is to use the first gold medal Belong to barrier layer and stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode, other shapes Grid, source electrode, the material of drain electrode is become to be also applied for the present invention when possessing the strongest diffusibility, such as gold, Silver etc..

Hereinafter the thin film transistor (TFT) that the embodiment of the present invention provides simply is introduced.

According to whether arranging etching barrier layer in TFT, TFT is divided into two categories below:

First kind TFT structure is: the grid, source electrode, drain electrode, the semiconductor layer that are positioned on substrate, be positioned at Gate insulator between described grid and semiconductor layer, between semiconductor layer and source electrode, drain electrode Etching barrier layer, and the first metal barrier between described source-drain electrode layer and gate insulator； Wherein, described first metal barrier is arranged with layer with described semiconductor layer, described first metal barrier Stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode.

It should be noted that described " source electrode, drain electrode " represents the source electrode and drain electrode arranged with layer, it is possible to " source electrode, the drain electrode " and " source-drain electrode layer " mentioned with referred to as source-drain electrode layer, the i.e. present invention all represents same Source electrode and drain electrode, the source electrode arranged with layer and drain electrode that layer is arranged are source-drain electrode layer.

Equations of The Second Kind TFT structure is: the grid, source electrode, drain electrode, the semiconductor layer that are positioned on substrate, be positioned at Gate insulator between described grid and semiconductor layer, between gate insulator and source electrode and drain electrode The first metal barrier；Described first metal barrier is between source electrode, drain electrode and gate insulator； Wherein, described first metal barrier is arranged with layer with described semiconductor layer, described first metal barrier Stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode.

The first metal barrier in above-mentioned two classes TFT of the present invention is for stoping formation source electrode, the material of drain electrode Material diffuses in gate insulator and/or grid, and for stoping the material forming grid to diffuse to partly lead In body layer and/or source-drain electrode layer.

In order to stop further or avoid in above-mentioned two classes TFT of the present invention formed source electrode, drain electrode material with Form the phase counterdiffusion of the material of grid, for instance, it is preferred that at the first metal barrier and source-drain electrode layer Between the second metal barrier is set.This second metal barrier is possible not only to stop and forms source electrode, drain electrode Material be diffused into semiconductor layer with the material forming grid, it is also possible to stop further forming source electrode, leakage The material of pole is diffused into gate insulator and grid.

The one of which preferred implementation of first kind TFT is: thin film transistor (TFT) includes substrate, is formed at Grid on described substrate, source-drain electrode layer, semiconductor layer；And be formed on described substrate be positioned at described Gate insulator between grid and semiconductor layer, the etching between semiconductor layer and source-drain electrode layer hinder Barrier, and the first metal barrier between described source-drain electrode layer and gate insulator；Wherein, Described first metal barrier is arranged with layer insulation with described semiconductor layer.

Described source electrode and drain electrode are made by copper metal, and in order to avoid copper metal ion, to be diffused into grid exhausted Edge layer, grid, pollute grid and gate insulator, causes TFT hydraulic performance decline, and the present invention exists Form the first metal barrier between source-drain electrode layer and gate insulator, stop that source-drain electrode layer metal ion expands Dissipate.

In order to prevent source-drain electrode layer metal copper ion to be diffused into semiconductor layer, at semiconductor layer and source-drain electrode layer Between arrange there is the phase counterdiffusion merit stoping the material forming source electrode and drain electrode with the material of formation grid The barrier layer of energy, described barrier layer is the second metal barrier, and this second metal barrier is possible not only to resistance Gear forms the material of source-drain electrode layer and is diffused into semiconductor layer, it is also possible to barrier metal copper ion diffusion further To gate insulator and grid.

The above-mentioned thin film crystalline substance that the present invention provides is illustrated below with reference to accompanying drawing and different embodiments Body pipe TFT and preparation method thereof, array base palte, display device and barrier layer.

The thin film transistor (TFT) TFT that the embodiment of the present invention provides can be bottom gate type or top-gate type structure, below Bottom gate type and the top gate type TFT that the embodiment of the present invention provides will be illustrated by accompanying drawing.

Embodiment one: corresponding above-mentioned first kind TFT.

The bottom gate type TFT that embodiment one provides, structure is:

Grid is positioned on substrate；

Gate insulator is positioned on described grid；

Semiconductor layer and the first metal barrier are positioned on described gate insulator；

Etching barrier layer is positioned on described semiconductor layer；

Source electrode and drain electrode are positioned on described etching barrier layer；

The top gate type TFT that embodiment one provides, structure is:

Source electrode and drain electrode are positioned on described substrate；

Etching barrier layer is positioned in described source electrode and drain electrode；

Described grid is positioned on described gate insulator.

Described semiconductor layer can arrange and can also arrange by different layers with layer with described first metal barrier, In order to reduce the integral thickness of TFT as far as possible, such as, it is preferred that semiconductor layer and described first metal Barrier layer is arranged with layer.

It should be noted that the structure of all TFT of present invention offer, the upper-lower position between each film layer Relation only represents between film layer with layer or different layers in addition to special instruction, is not offered as the concrete knot of film layer Structure and the concrete relative position with other film layers.Such as etching barrier layer is positioned at described source electrode and drain electrode On, only represent etching barrier layer and source electrode and drain electrode different layers, be positioned at source relative to base plate carving and corrosion barrier layer On pole and drain electrode, i.e. etching barrier layer compares source electrode and drains away from substrate.

Such as, it is preferred that described first metal barrier is arranged or mutually the most exhausted with the insulation of described semiconductor layer Edge is arranged.

In this embodiment, semiconductor layer and the first metal barrier insulate setting mutually.

Further, the material of described formation source electrode and drain electrode and formed grid material at least one Copper or copper alloy for low-resistivity.

Hereinafter will be illustrated by accompanying drawing, the array base palte including TFT that Fig. 1 provides for embodiment one Schematic top plan view, Fig. 2 be the TFT shown in Fig. 1 A-B to sectional view.

TFT shown in Fig. 1, including grid 2, source electrode 8, drain electrode 9, etching barrier layer 6 and half Conductor layer.Array base palte shown in Fig. 1 also includes the data wire 81 being connected with source electrode 8, with grid 2 The gate line 21 being connected.Source electrode 8 and drain electrode 9 are properly termed as source-drain electrode layer, source-drain electrode layer place TFT Film layer be referred to as SD layer.

Illustrating as a example by bottom gate type TFT, the bottom gate type TFT shown in Fig. 2 includes: substrate 1, substrate 1 On grid 2；

The gate insulator 3 being positioned on substrate 1 on grid 2；

The semiconductor layer 4 being positioned on substrate 1 on gate insulator 3 and the first metal barrier 5, partly lead Body layer 4 and the first metal barrier 5 are positioned at same layer；

The etching barrier layer 6 being positioned on substrate 1 on semiconductor layer 4, etching barrier layer 6 is positioned at quasiconductor The top of layer 4 raceway groove, when being used for protecting etching, raceway groove is unaffected.

The source electrode 8 being positioned on substrate 1 on first metal barrier 5 and drain electrode 9.

By being provided with the first metal barrier between source-drain electrode layer (SD layer) and gate insulator 3 Layer 5, stops that the metal ion of source-drain electrode layer enters gate insulator and grid layer.In like manner, also barrier grid The metal ion of pole layer enters semiconductor layer and source-drain electrode layer, improves TFT performance.

TFT shown in Fig. 2, semiconductor layer 4 and the first metal barrier 5 are positioned at same layer for a kind of excellent The embodiment of choosing, semiconductor layer 4 and the first metal barrier 5 can also be positioned at different layers, not do Concrete restriction.

For instance, it is preferred that in the material of the material of described formation source electrode and drain electrode and formation grid at least One of for copper or copper alloy.

In the material forming source electrode and drain electrode and the material forming grid at least one for copper or copper alloy Time, the phase counterdiffusion of material with the material forming grid in order to avoid the formation of source electrode and drain electrode further. Such as, it is preferred that the TFT that embodiment one provides also includes: the second metal barrier, described second gold medal Genus barrier layer is between described first metal barrier and described source electrode, drain electrode, and described second metal hinders Barrier stops the phase counterdiffusion of the material forming source electrode and drain electrode and the material forming grid.

Such as, bottom gate type TFT structure is:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Top gate type TFT structure is:

Described source-drain electrode layer is positioned on described substrate；

Described gate insulator is positioned on described semiconductor layer；

Described grid is positioned on described gate insulator.

Hereinafter will be illustrated by accompanying drawing, as it is shown on figure 3, the TFT that the embodiment of the present invention one provides, Also include: the second metal barrier 7, between source-drain electrode layer and the first metal barrier 5.

Described TFT structure is:

The grid 2 being positioned on substrate 1；

The gate insulator 3 being positioned on grid 2；

The semiconductor layer 4 being positioned on gate insulator 3 and the first metal barrier 5；

It is positioned at the etching barrier layer 6 above semiconductor layer 4；

It is positioned at the second metal barrier 7 on semiconductor layer 4 and the first metal barrier 5；

The source electrode 8 being positioned on the second metal barrier 7 and drain electrode 9.

TFT shown in Fig. 3, the second metal barrier 7 is positioned at source-drain electrode layer and the first metal barrier 5 Between, further block the metal ion of SD layer to gate insulator and/or gate diffusions, more enter One step improves the performance of TFT.

The TFT that above-mentioned Fig. 2 and Fig. 3 provides, the material of at least one source-drain electrode layer and grid is metallic copper Or copper alloy (Cu).For instance, it is preferred that the material of described formation source electrode and drain electrode is copper or copper alloy.

For instance, it is preferred that grid can be metallic copper (Cu), crome metal (Cr), tungsten (W), Titanium (Ti), metal tantalum (Ta), metal molybdenum (Mo) etc., or above-mentioned at least two metal Alloy.

In order to prevent source-drain electrode layer metal copper ion to be diffused into semiconductor layer, at semiconductor layer and source-drain electrode layer Between the second metal barrier is set, this second metal barrier be possible not only to barrier metal copper ion diffusion To semiconductor layer, it is also possible to barrier metal copper ion is diffused into gate insulator and grid further.

The first metal barrier and semiconductor layer that the TFT of any of the above-described mode is arranged with layer can use Commaterial is prepared from, or uses not same material to be prepared from.

Such as, it is preferred that described semiconductor layer is metal oxide semiconductor layer.

Described first metal barrier uses metal oxide semiconductor material to be made.

Further, described first metal barrier uses the material identical with described semiconductor layer to make Form.

Such as, with layer arrange the first metal barrier and semiconductor layer use commaterial preparation and Become.First metal barrier can use the material preparing metal oxide semiconductor layer, such as: permissible It it is indium gallium zinc oxide (IGZO), hafnium indium-zinc oxide (HIZO), indium-zinc oxide (IZO), non- Brilliant indium-zinc oxide (a-InZnO), amorphous zinc oxide doped oxyfluoride (ZnO:F), Indium sesquioxide. doping Tin-oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide adulterated al oxide (ZnO:Al), amorphous oxide titanium doped niobium oxidation Thing (TiO₂: Nb), chromium tin-oxide (Cd-Sn-O) or other metal-oxides.The arranged with layer When one metal barrier and semiconductor layer can use commaterial to be prepared from, the first metal barrier Being same film layer with semiconductor layer, in implementation process, semiconductor layer and the first metal barrier are by same One time patterning processes is made, and relative to existing making TFT, does not increase technological process.

The first metal barrier and the semiconductor layer that arrange for same layer use not same material to be prepared from. Such as, it is preferred that the first metal barrier can use copper oxide (CuO_x), copper nitride (CuN_y) Or nitrogen copper oxide (CuN_yO_x) etc. film layer, or such as, it is preferred that described first metal barrier is adopted It is made with the metal oxide semiconductor material differed with described semiconductor layer.

The TFT (TFT shown in corresponding diagram 2 and Fig. 3) of above two optimal way arrange with layer One metal barrier and semiconductor layer can insulate or on-insulated setting, as long as not affecting the reality of TFT function Now, in this no limit.The method that described insulation is arranged can be multiple, the most directly uses and swashs The mode of light cutting mode, doping process or patterning processes makes both insulate mutually.

When the first metal barrier that same layer is arranged and semiconductor layer use commaterial to be prepared from, Semiconductor layer and the first metal barrier insulate in the case of setting mutually, the semiconductor layer formed with layer and the One metal barrier can be by patterning processes, directly employing cut mode, doping process or composition The mode of technique makes both insulate mutually, provided of course that both can be made to keep insulating, does not limit tool The forming method of body.The method that described insulation is arranged can be multiple, the most directly uses cut side The mode of formula, doping process or patterning processes makes both insulate mutually.

For instance, it is preferred that the first metal barrier arranged with layer and semiconductor layer use commaterial It is prepared from, the two on-insulated setting.In specific implementation process, semiconductor layer and the first metal barrier Layer, by same film layer, is made with a patterning processes, relative to existing making TFT, does not increase Add technological process.

For instance, it is preferred that the TFT that above-mentioned Fig. 2 and Fig. 3 provides, at least one source-drain electrode layer and grid Material be metallic copper (Cu) or copper alloy.For instance, it is preferred that described formation source electrode and the material of drain electrode Material is copper or copper alloy.

Further, the second metal barrier can use copper oxide (CuO_x), copper nitride (CuN_y) Or nitrogen copper oxide (CuN_yO_x) etc. film layer；Or described second metal barrier uses metal-oxide half Conductor material is made.Such as: can be indium gallium zinc oxide (IGZO), hafnium indium-zinc oxide (HIZO), indium-zinc oxide (IZO), amorphous indium-zinc oxide (a-InZnO), amorphous zinc oxide are mixed Miscellaneous oxyfluoride (ZnO:F), indium-doped tin oxide oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum Oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide adulterated al oxide (ZnO:Al), the titanium doped niobium oxide of amorphous oxide (TiO₂: Nb), chromium tin-oxide (Cd-Sn-O) Or other metal-oxides.

The TFT of any of the above-described mode, the material of at least one source electrode, drain electrode, grid is that resistivity is relatively low Copper or copper alloy.For instance, it is preferred that source-drain electrode layer is metallic copper or copper alloy, the second metal barrier Layer is copper oxide (CuO_x), copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x) etc..Implementing Cheng Zhong, the second metal barrier and SD layer can use and be made with a patterning processes.Can manage Solving, the generation type of the second metal barrier and SD layer is not limited to this.

First, copper oxide (CuO_x), copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x) can be with Semiconductor layer and the first metal barrier form stable interface, secondly, and copper oxide (CuO_x), nitridation Copper (CuN_y) or nitrogen copper oxide (CuN_yO_x) etching performance and metallic copper or the source that formed of copper alloy The etching performance of drain electrode layer be similar to, at the same time to source-drain electrode layer and be disposed below first metal resistance When barrier carries out wet etching, owing to there is therebetween the second metal barrier (copper oxide (CuO_x)、 Copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x)), solve metallic copper or copper alloy directly with the One metal barrier combines the problem that wet etching is more difficult, or the Cross Section Morphology that wet etching goes out is paid no attention to The problem thought.

TFT based on any of the above-described mode, in order to preferably stop formation source electrode, the material of drain electrode and shape Becoming the phase counterdiffusion of the material of grid, first metal barrier projected area on substrate should be the most complete Cover source-drain electrode layer projected area on substrate, but should ensure that mutual position relationship does not affect TFT The realization of performance.

In order to preferably stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode, In the above embodiment of the present invention, second metal barrier projected area on substrate should at least be completely covered Source-drain electrode layer projected area on substrate, as long as not affecting the realization of TFT function, to concrete Position is not construed as limiting.

In the above embodiment of the present invention, the first metal barrier and the throwing on substrate of second metal barrier Shadow area and mutual position relationship the most too much limit, as long as not affecting the realization of TFT function.

For instance, it is preferred that for the performance improving oxide TFT, gate insulator may be designed as two-layer, Ground floor is silicon nitride (SiN_x) layer, it contacts with grid, and the second layer is silicon oxide (SiO_x) layer, It directly contacts with semiconductor layer and the first metal barrier.On the one hand the design of double layer of insulation can hinder The diffusion of the metal ion in each electrode in gear TFT, on the other hand can avoid the water in the external world, oxygen Deng the entrance of impurity, improve the performance of TFT.

For instance, it is preferred that for the electric conductivity improving semiconductor layer, the TFT of any of the above-described mode Also include: be positioned at the first ohmic contact layer and second ohmic contact layer of the both sides up and down of semiconductor layer.The One ohmic contact layer is between gate insulator and semiconductor layer, and the second ohmic contact layer is positioned at quasiconductor Between layer and source electrode, drain electrode.This first ohmic contact layer and the second ohmic contact layer can be electric conductivities Preferably doping semiconductor layer.

For instance, it is preferred that the substrate that the embodiment of the present invention provides can be glass substrate, quartzy or soft Property plastics.

It should be noted that the structure enumerated in the present invention the most specifically illustrates the lead-in wire of viewing area periphery The structure in region, each film layer is all formed at periphery when carrying out viewing area and making simultaneously.And show Show that the film layer order in region can have a variety of change, as long as producing the necessary element of panel driving (ratio Such as grid, source electrode, drain electrode and pixel electrode etc.), it is ensured that panel driven.So periphery Film layer structure has a lot of change the most accordingly, and such as grid is the most directly produced on substrate, and having can Can thereunder there is other film layer, in order to improve substrate and the tack of metallic diaphragm on substrate, it is also possible to Arranging cushion between substrate and grid, described cushion can be indium tin oxide (ITO) film layer Or indium-zinc oxide (IZO) film layer；Such as insulating barrier the most not necessarily must have 2 layers, grid and partly leading A more than layer insulating it is also possible between body layer.In the structure of the embodiment of the present invention, as long as guaranteeing each gold Belong to layer insulated from each other, and have be connected to outside can conductive component (such as ITO material make connection Electrode).

Illustrate as a example by above-described embodiment one and bottom gate type TFT, will simply introduce the embodiment of the present invention one below The top gate type TFT provided.

The bottom gate type TFT's of any one mode that the structure of top gate type TFT provides with above-described embodiment one Structure is similar to, say, that the first metal barrier in the TFT of the above-mentioned offer of embodiment one, second The correlation technique features such as metal barrier, gate insulator, substrate, ohmic contact layer and cushion are the suitableeest For top gate type TFT.Difference is, source electrode, drain electrode, grid, gate insulator and quasiconductor Layer changes with the relative position of substrate.Cushion between substrate and source-drain electrode layer, semiconductor portion Also cushion is had between separation structure and substrate.In the top gate type TFT that the embodiment of the present invention provides, except TFT Outside structure is different from above-mentioned bottom gate type TFT structure, other explanations are the most applicable.

Embodiment two: the one of which embodiment of corresponding embodiment one, the most corresponding above-mentioned first kind TFT One of which embodiment.

As a example by bottom gate type TFT.

Fig. 4 is TFT schematic top plan view, Fig. 5 be the TFT shown in Fig. 4 A-B to sectional view.

The TFT that this embodiment one provides, including grid 2 (structure as shown in the dotted line in Fig. 4) And be connected with grid 2 gate line 21, source electrode 8, drain electrode 9, the data wire 81 being connected with source electrode 8, And semiconductor layer 4.

Source electrode 8 and drain electrode 9 are properly termed as source-drain electrode layer, and the film layer of source-drain electrode layer place TFT is referred to as SD Layer.

See Fig. 5, the TFT that the embodiment of the present invention provides, including:

Substrate 1, formation grid 2 on substrate 1；

It is formed on substrate 1 gate insulator 3 being positioned on grid 2；

It is formed on substrate 1 semiconductor layer 4 and the first metal barrier 5 being positioned on gate insulator 3, Semiconductor layer 4 and the first metal barrier 5 are positioned at same layer；

It is formed on substrate 1 etching barrier layer 6 being positioned on semiconductor layer 4 and the first metal barrier 5, Etching barrier layer 6 is positioned at the top of semiconductor layer 4；

It is formed on substrate 1 source electrode 8 and drain electrode 9 being positioned on etching barrier layer 6.

Such as, it is preferred that the material of described formation source electrode and drain electrode and formed grid material at least One of for copper or copper alloy.

Such as, it is preferred that see Fig. 5, the first metal barrier 5 is positioned at and source-drain electrode layer (i.e. source electrode 8 and drain electrode 9) corresponding position.That is, the upright projection of source-drain electrode layer is positioned at the first metal barrier 5 In and semiconductor layer 4 in, to ensure that source-drain electrode layer metal ion is not diffuse into being positioned at the first metal resistance In gate insulator 3 below barrier 5 and grid 2.

Such as, it is preferred that the first metal barrier 5 shown in Fig. 5 is by the material identical with semiconductor layer 4 Material is made.

In implementation process, semiconductor layer 4 and the first metal barrier 5 are by same film layer, with once Patterning processes is made, and relative to existing making TFT, does not increase technological process.Semiconductor layer 4 Insulating mutually with the first metal barrier 5, the semiconductor layer 4 and the first metal barrier 5 that are formed with layer can To make to there is certain gap between it by patterning processes, provided of course that both can be made to keep insulation i.e. Can, do not limit concrete forming method.

Described semiconductor layer can be metal-oxide, such as: can be indium gallium zinc oxide (IGZO), Hafnium indium-zinc oxide (HIZO), indium-zinc oxide (IZO), amorphous indium-zinc oxide (a-InZnO), Amorphous zinc oxide doped oxyfluoride (ZnO:F), indium-doped tin oxide oxide (In₂O₃: Sn), amorphous Indium sesquioxide. doping molybdenum oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide mixes Miscellaneous aluminum oxide (ZnO:Al), amorphous oxide titanium doped niobium oxide (TiO₂: Nb), chromium tin-oxide Or other metal-oxides (Cd-Sn-O).

First metal barrier of the present invention is metal oxide film layer, and this metal oxide film layer can have Effect barrier metal ion, improves the performance of TFT.

TFT shown in Fig. 4 and Fig. 5, by source-drain electrode layer (SD layer) and gate insulator 3 Between be provided with the first metal barrier 5, stop the metal ion of source-drain electrode layer enter gate insulator and Grid layer.In like manner, also the metal ion of barrier grid layer enters semiconductor layer and source-drain electrode layer, improves TFT performance.

Such as, it is preferred that see Fig. 6, the TFT that the embodiment of the present invention provides, also include: the second gold medal Belong to barrier layer 7；Between source-drain electrode layer and the first metal barrier 5.

Such as, it is preferred that the second metal barrier 7, it is positioned at the position corresponding with source-drain electrode layer, position Between the first metal barrier 5 and source-drain electrode layer.Such as, it is preferred that the first metal barrier 5 He Second metal barrier 7 can be overlapping in the projection of vertical direction.

TFT shown in Fig. 6, the second metal barrier 7 is positioned at source-drain electrode layer and the first metal barrier 5 Between, further block the metal ion of SD layer to gate insulator or gate diffusions, also stop The metal ion of grid spreads to semiconductor layer and SD layer, further improves the performance of TFT. In implementation process, the second metal barrier and SD layer are made in a patterning processes.

Such as, it is preferred that the second metal barrier 7 is copper oxide (CuO), copper nitride (CuN), Or nitrogen copper oxide (CuNO) etc..Copper oxide (CuO), copper nitride (CuN), or nitrogen copper oxide (CuNO) Stable interface can be formed with semiconductor layer 4 and the first metal barrier 5, at the same time to source-drain electrode layer, When data wire and the first metal barrier 5 being disposed below carry out wet etching, due to therebetween There is the second metal barrier 7, such as copper oxide (CuO), copper nitride (CuN), or nitrogen copper oxide (CuNO), solve metallic copper and be directly combined more difficult the asking of wet etching with the first metal barrier 5 Topic, or the problem that the Cross Section Morphology that goes out of wet etching is undesirable.

Such as, it is preferred that for the performance improving oxide TFT, gate insulator may be designed as two-layer, Ground floor is silicon nitride (SiN_x), contacting with grid, the second layer is silicon oxide (SiO_x) directly with half Conductor layer and the contact of the first metal barrier.

Such as, it is preferred that for the electric conductivity improving semiconductor layer, described TFT also includes: be positioned at First ohmic contact layer of the both sides up and down of semiconductor layer and the second ohmic contact layer.First ohmic contact layer Between gate insulator and semiconductor layer, the second ohmic contact layer is positioned at semiconductor layer and source drain Between.This first ohmic contact layer and the second ohmic contact layer can be that electric conductivity preferably adulterates and partly leads Body layer.

Such as, it is preferred that the substrate that the embodiment of the present invention provides can be glass substrate, quartz, or Flexiplast etc..

It should be noted that the structure enumerated in the present invention the most specifically illustrates the lead-in wire of viewing area periphery The structure in region, each film layer is all formed at periphery when carrying out viewing area and making simultaneously.And show Show that the film layer order in region can have a variety of change, as long as producing the necessary element of panel driving (ratio Such as grid, source electrode, drain electrode and pixel electrode etc.), it is ensured that panel driven.So periphery Film layer structure has a lot of change the most accordingly, and such as grid is the most directly produced on substrate, and having can Can thereunder there is other film layer, in order to improve substrate and the tack of metallic diaphragm on substrate, it is also possible to Arranging cushion between substrate and grid, described cushion can be indium tin oxide (ITO) film layer Or indium-zinc oxide (IZO) film layer；Such as insulating barrier the most not necessarily must have a two-layer, grid and partly leading A more than layer insulating it is also possible between body layer.In the structure of the embodiment of the present invention, as long as guaranteeing each gold Belong to layer insulated from each other, and have be connected to outside can conductive component (such as ITO material make connection Electrode).

The TFT that above example two provides is bottom gate type TFT, will simply introduce top gate type TFT below.

Seeing Fig. 7, similar with above-mentioned bottom gate type TFT structure, difference is, grid and quasiconductor Layer location is different, and described TFT includes:

Substrate 1, form source electrode 8 on substrate 1 and drain electrode 9；

It is formed on substrate 1 etching barrier layer 6 being positioned in source electrode 8 and drain electrode 9；

It is formed on substrate 1 semiconductor layer 4 and the first metal barrier 5 being positioned on etching barrier layer 6；

It is formed on substrate 1 gate insulator 3 being positioned on semiconductor layer 4 and the first metal barrier 5；

It is formed on substrate 1 grid 2 being positioned on gate insulator 3.

Described etching barrier layer actually protection source electrode and drain electrode are not affected by etching.

Such as, it is preferred that described TFT also includes: be formed at the first metal barrier 5 and source electrode 8 And the second metal barrier 7 between drain electrode 9.

Such as, it is preferred that described TFT also includes: be formed on grid 2 and cover the blunt of whole TFT Change layer 10.

Similar with embodiment one, the array base palte including described top gate type TFT also includes pixel electrode 11.

Pixel electrode 11 is connected with the drain electrode 9 of TFT by via.

Other structures are similar with the array base-plate structure of bottom gate type TFT, repeat no more here.

Embodiment three: Equations of The Second Kind TFT (at least includes non-crystalline silicon or multi-crystal TFT).

The Equations of The Second Kind TFT that embodiment three provides is similar, the most in fact with the TFT that above-described embodiment one provides First metal barrier of example one offer, the second metal barrier, gate insulator, substrate, ohm are provided The material of the film layer of contact layer and cushion etc., the correlation technique features such as position are set all it are applicable to embodiment The three Equations of The Second Kind TFT provided.Difference includes following several respects:

(1) material of semiconductor layer is different, and the semiconductor layer of non-crystalline silicon tft and multi-crystal TFT is non- Crystal silicon or polysilicon.

(2) without etching barrier layer.

(3) first metal barriers and semiconductor layer use different materials to be made.

The below structure of the TFT that simple declaration embodiment three provides.

Such as, it is preferred that for the bottom gate type TFT only arranging the first metal barrier, for:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Such as, it is preferred that for the top gate type TFT only arranging the first metal barrier, for:

Described grid is positioned on described gate insulator.

Such as, it is preferred that for arranging the first metal barrier and the bottom gate of the second metal barrier simultaneously Type TFT, for:

Grid is positioned on described substrate；

Gate insulator is positioned on described grid；

Second metal barrier is positioned on described semiconductor layer and the first metal barrier；

Described source-drain electrode layer is positioned on described first metal barrier.

Such as, it is preferred that for arranging the first metal barrier and the top-gated of the second metal barrier simultaneously Type TFT, for:

Described grid is positioned on described gate insulator.

The top gate type TFT that embodiment three provides is similar with bottom gate type TFT structure, the such as first metal resistance The film layer of barrier, the second metal barrier, gate insulator, substrate, ohmic contact layer and cushion etc. Material, the correlation technique features such as position are set all it are applicable to top gate type TFT.The TFT that embodiment three provides At least include non-crystalline silicon or multi-crystal TFT.

Above by embodiment one to embodiment three, the TFT that the present invention provides is described.The present invention provides TFT is not limited to the embodiment that embodiment one to embodiment three provides, and any includes embodiment one to reality Execute the first metal barrier that example three provides and within the second metal barrier is all contained in the scope of the invention.

Embodiment four: array base palte.

The embodiment of the present invention three provide array base palte, including embodiment one to embodiment three provide arbitrary The TFT of mode, the TFT of the following stated at least include metal-oxide TFT, non-crystalline silicon tft and many Crystal silicon TFT.The TFT of the following stated, at least includes the first metal barrier, described TFT such as, The most also include the second metal barrier.

Described array base palte includes the TFT only including the first metal barrier of any of the above-described mode.

Described array base palte also includes: data wire and gate line, described data wire and described thin film transistor (TFT) Source electrode be connected, described gate line is connected with the grid of thin film transistor (TFT)；

Described first metal barrier is positioned at corresponding with described source electrode, drain electrode, gate line and data wire Position.

Described array base palte includes the first metal barrier and the second gold medal while including any of the above-described mode Belong to the TFT on barrier layer.

Described second metal barrier is positioned at the position corresponding with described source electrode, drain electrode and data wire, or Person is positioned at the position corresponding with described source electrode, drain electrode and gate line, or is positioned at and described source electrode, leakage The position that pole, gate line are corresponding with data wire.

Illustrating below by way of accompanying drawing, see Fig. 1, array base palte also includes: with grid in described TFT The gate line 21 that pole 2 is connected, and the data wire 81 being connected with source electrode 8.

Usually, the material of data wire 81 and/or gate line 21 is identical with source-drain electrode layer or grid.

On the basis of above-mentioned TFT, in order to preferably prevent in data wire and/or grid alignment TFT Film layer spreads, or stops data wire and the material phase counterdiffusion of gate line, including the array of above-mentioned TFT Substrate also includes: be positioned at the first metal barrier of data wire corresponding region, and/or it is corresponding to be positioned at gate line First metal barrier in region.

In order to further prevent the film layer in data wire and/or grid alignment TFT from spreading, or stop The material phase counterdiffusion of data wire and gate line, arranges the first gold medal at data wire and/or gate line corresponding region On the basis of belonging to barrier layer, array base palte also includes: be positioned at the second metal barrier of data wire corresponding region Layer, and/or it is positioned at the second metal barrier of gate line corresponding region.

First metal barrier projected area on substrate not less than correspondence position source electrode, drain, number According to line and/or the area of grid.Second metal barrier projected area on substrate is not less than correspondence position The area of source electrode, drain electrode, data wire and/or grid.The projection on substrate of data wire and/or grid It is positioned at the projection on substrate of first metal barrier, but should ensure that mutual position relationship does not affects The realization of TFT performance.The projection on substrate of data wire and/or grid is positioned at the second metal barrier and exists In projection on substrate, but should ensure that mutual position relationship does not affect the realization of TFT performance.

One is preferred embodiment: (Fig. 9 is the array base palte shown in Fig. 8 to see Fig. 8 and Fig. 9 C-D to sectional view), be respectively provided with the first metal at data wire 81 and the corresponding region of gate line 21 Barrier layer 5 and the second metal barrier 7.Such as, the first metal barrier 5 is arranged at source electrode 8 and leakage The region that pole 9 is corresponding, is additionally arranged at gate line 21 and the corresponding region of data wire 81.

Second metal barrier can also be arranged on and described source electrode, drain electrode and data wire or described source Pole, drain electrode and gate line or the corresponding position of described source electrode, drain electrode, gate line and data wire, this In repeat no more.

For instance, it is preferred that the first metal barrier and/or the second metal barrier are in the projection of vertical direction, It is completely superposed with data wire, source electrode and the drain electrode projection on substrate.

For bottom gate type TFT, a kind of embodiment is: first makes grid and gate line, makes first afterwards Metal barrier, finally makes data wire；First metal barrier can be arranged on above gate line and/ Or below data wire.Another embodiment is: gate line and data wire are formed with a patterning processes, Form gate line and data wire when forming grid, or form gate line and data when forming source-drain electrode layer Line；First metal barrier can be arranged on the top of gate line and/or data wire, or is arranged on grid Line and/or the lower section of data wire.Main purpose is to avoid the metal ion of gate line and data wire to be diffused into half TFT performance is impacted by conductor layer.

TFT shown in Fig. 8, is both provided with first in the region of gate line 21 and data wire 81 correspondence Metal barrier.After forming gate line 21, while forming semiconductor layer, formed and gate line The first metal barrier (not shown in Fig. 8) that 21 regions are corresponding.

Owing to data wire 81 and source electrode 8 are made in a patterning processes, material is identical.? Formed before data wire 81, while forming semiconductor layer 4, form the be positioned at below data wire 81 One metal barrier.

First barrier layer can with block data line metal ion be diffused into the grid of TFT or gate line or its His film layer structure, improves the performance of TFT further, and the image that further improve display device shows Effect.

Such as, it is preferred that this array base palte also include being positioned at the conductive film layer nearer with substrate and substrate it Between cushion, improve the adhesive force between conductive film layer and substrate.Such as between gate line and substrate, And first arrange cushion between barrier layer and substrate, improve gate line and the first barrier layer respectively with base The adhesive force of plate.

Certainly, the embodiment of the present invention one, embodiment two and embodiment three provide TFT and array base palte are tied It is relatively low by other resistivity that structure is equally applicable at least one source-drain electrode layer, grid, data wire and gate line And the TFT that makes of the higher metal or alloy of metal ion diffusibility and array base palte.Such as gold, silver, When billon or silver alloy etc. are as at least one source-drain electrode layer, grid, data wire and gate line, use TFT and array base palte that the embodiment of the present invention provides equally solve metal ion and spread half caused The problem of conductor hydraulic performance decline.

Seeing Fig. 9, the array base palte that the embodiment of the present invention provides also includes: be positioned on TFT source-drain electrode layer Passivation layer 10, and the pixel electrode 11 being connected with the drain electrode 9 of TFT.Pixel electrode 11 and drain electrode 9 are connected by via.

For instance, it is preferred that the passivation layer that the embodiment of the present invention provides, organic resin material it is made. Organic resin can be benzocyclobutene (BCB), it is also possible to be other organic photosensitive material.Organic tree The fat inorganic material hardness that compares is less, is more beneficial for array substrate outermost layer and plays smooth effect, has The ideal alignment of the liquid crystal molecule being beneficial between color membrane substrates and array base palte.

In the present invention, patterning processes, photoetching process can be only included, or, including photoetching process and quarter Erosion step, can also include simultaneously printing, ink-jet etc. other for the technique forming predetermined pattern；Photoetching Technique, refer to film forming, expose, the technical process such as development utilize photoresist, mask plate, exposure The technique that machine etc. form figure.Can be according to the corresponding patterning processes of structure choice formed in the present invention.

The mode of shape film forming layer generally have deposition, apply, the various ways such as sputtering, below all with therein One or more modes are illustrated and are illustrated.For example, use patterning processes to be formed on substrate to include The figure of grid, for: on substrate, first deposit gate electrode film layer, then coating photoresist, utilize mask Photoresist is exposed by plate and development treatment is to form photoetching agent pattern, followed by this photoetching agent pattern As etching mask, remove corresponding film layer by techniques such as etchings, and remove remaining photoresist, Final formation gate patterns on substrate.

Described array base palte is specifically introduced as a example by the TFT that embodiment two provides.

The array base palte that Figure 10 provides for the embodiment of the present invention.Wherein, including the TFT described in embodiment two.

Also include: the gate line 21 being connected with grid in TFT 2, and the data being connected with source electrode 8 Line 81.

Seeing Figure 10, the array base palte that the embodiment of the present invention provides, the first metal barrier 5 can also set Put (in Figure 10, gate line and data wire are positioned at the first metal barrier 5 with gate line and data wire Underface, embodies the most in Fig. 10) corresponding region.

For bottom gate type TFT, can be arranged on above gate line and/or below data wire.

TFT shown in Figure 10, at gate line and data wire, (gate line and data wire are the most not Illustrating) corresponding region is both provided with the first metal barrier 5.It is to say, the first metal barrier 5 and/or second metal barrier 7 in the projection of vertical direction, exist with data wire, source electrode 8 and drain electrode 9 Projection on substrate 1 is overlapping.

Being formed after gate line, while forming semiconductor layer, form corresponding with gate line region the One metal barrier.

Owing to data wire and source electrode are made in a patterning processes, material is identical.Forming number Before line, while forming semiconductor layer, form the first metal barrier.

First metal barrier can be diffused into grid or the gate line of TFT with block data line metal ion Or other film layer structures, simultaneously the metal ion of barrier grid polar curve or data wire can also be diffused into quasiconductor Layer, improves the performance of TFT further, further improves the image display effect of display device.

In like manner, the second metal barrier can also be arranged on the region corresponding with gate line and data wire, Here repeat no more.

Such as, it is preferred that this array base palte also includes being positioned at gate line and the first metal barrier and substrate Between cushion, improve the adhesive force of gate line and the first metal barrier and substrate.

Seeing Fig. 9, the array base palte that the embodiment of the present invention provides also includes: be positioned on TFT source-drain electrode layer Passivation layer 10, and the pixel electrode 11 being connected with the drain electrode 8 of TFT.Pixel electrode 11 and drain electrode 9 are connected by via, and this belongs to prior art, repeat no more.

Such as, it is preferred that the passivation layer that the embodiment of the present invention provides, organic resin material it is made. Organic resin can be benzocyclobutene (BCB), it is also possible to be other organic photosensitive material.Organic tree The fat inorganic material hardness that compares is less, is more beneficial for array substrate outermost layer and plays smooth effect, has The ideal alignment of the liquid crystal molecule being beneficial between color membrane substrates and array base palte.

The embodiment of the present invention provide TFT and array base palte, source-drain electrode layer and data wire can but not It is limited to be made by metallic copper (Cu).

The embodiment of the present invention provide grid can be metallic diaphragm, can be such as crome metal (Cr), Tungsten (W), Titanium (Ti), metal tantalum (Ta), metal molybdenum (Mo) etc., or above-mentioned The alloy of at least two metal.

Embodiment five: a kind of display device.

The embodiment of the present invention provide display device for above-described embodiment one to embodiment three provide arbitrary The TFT of mode；Or the array base of the either type that described display device provides for above-described embodiment four Plate.

Described display device can be liquid crystal panel, liquid crystal display, LCD TV, oled panel, The display devices such as OLED display, OLED TV or Electronic Paper.

One example of this display device is liquid crystal indicator, wherein, and array base palte and counter substrate Opposite each other to form liquid crystal cell, liquid crystal cell is filled with liquid crystal material.This counter substrate is for example, Color membrane substrates.The pixel electrode of each pixel cell of array base palte is used for applying electric field to liquid crystal material Degree of rotation be controlled thus carry out display operation.In some instances, this liquid crystal display Also include the backlight that backlight is provided for array base palte.

Another example of this display device is organic electroluminescent (OLED) display device, wherein, The thin film transistor (TFT) of each pixel cell of array base palte connects anode or the moon of Organnic electroluminescent device Pole, is used for driving luminous organic material luminous to carry out display operation.

Thin film transistor (TFT) TFT and battle array that the embodiment of the present invention provides will be described below in terms of technological process The manufacture method of row substrate.

Embodiment six: thin film transistor (TFT) TFT and the manufacture method of array base palte.

As a example by the TFT that above-described embodiment one to embodiment three provides, illustrate the TFT's of present invention offer Manufacture method.

The manufacture method entirety of described TFT includes:

Formed and include grid, source-drain electrode layer and the figure of semiconductor layer；Formation include gate insulator and The figure of the first metal barrier；Described gate insulator between described grid and semiconductor layer, institute State the first metal barrier between described source-drain electrode layer and gate insulator, described first metal barrier Layer is arranged with layer insulation with described semiconductor layer.

For being provided only with the TFT of the first metal barrier, described formation include grid, source-drain electrode layer and The figure of semiconductor layer；Formed and include gate insulator and the figure of the first metal barrier, for:

For bottom gate type TFT, described method is:

Patterning processes is used to form the figure including grid on substrate；

For top gate type TFT, described method is:

Further, on the basis of the TFT being formed with above-mentioned first metal barrier, also include being formed The figure of the second metal barrier, described second metal barrier is positioned at described first metal barrier and institute State between source electrode, drain electrode.

For the TFT of the either type that embodiment one or embodiment two provide, i.e. there is etching barrier layer TFT, also include formed etching barrier layer figure, described etching barrier layer be positioned at described semiconductor layer with Between described source electrode and drain electrode.

Further, described formation include grid, source electrode, drain electrode, semiconductor layer, gate insulator, Etching barrier layer, the first metal barrier and the figure of the second metal barrier, for:

For bottom gate type TFT, described method is:

Patterning processes is used to form the figure including grid on substrate；

For top gate type TFT, described method is:

The embodiment corresponding with embodiment two that one of which is more specific, (has at above-mentioned embodiment First metal barrier, the second metal barrier) on the basis of, further, described first metal resistance Barrier is arranged with the insulation of described semiconductor layer.Described semiconductor layer is made by metal oxide semiconductor material Forming, further, the material that described first metal barrier is identical with described semiconductor layer employing makes Form.

For embodiment three provide TFT, i.e. without the TFT of etching barrier layer, described formation include grid, Source electrode, drain electrode, semiconductor layer, gate insulator, etching barrier layer, the first metal barrier and second The figure of metal barrier, for:

For bottom gate type TFT, described method is:

Described formation includes grid, source electrode, drain electrode, semiconductor layer, gate insulator, the first metal resistance Barrier and the figure of the second metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

For top gate type TFT, described method is:

Such as, it is preferred that described employing is being formed with the first metal barrier layer pattern with a patterning processes Substrate on formed and include that the figure of source electrode, drain electrode and the second metal barrier is:

The manufacture method of the TFT of present invention offer will be described as a example by the TFT that embodiment two provides below, The manufacture method of the thin film transistor (TFT) of embodiment of the present invention offer is described below in terms of technological process.

The manufacture method entirety of the thin film transistor (TFT) that the embodiment of the present invention provides includes:

Formed and include grid, source-drain electrode layer and the figure of semiconductor layer；And formed include gate insulator, Etching barrier layer, and the figure of the first metal barrier；

Described gate insulator is between described grid and semiconductor layer, and described etching barrier layer is positioned at institute Stating between semiconductor layer and source-drain electrode layer, described first metal barrier is positioned at described source-drain electrode layer and grid Between insulating barrier, wherein, described first metal barrier is arranged with layer insulation with described semiconductor layer.

Seeing Figure 11, the method for the array base palte making bottom gate type TFT specifically includes following steps:

S11, employing patterning processes form the figure including grid on substrate；

S12, employing patterning processes are formed on the substrate being formed with described gate patterns and include gate insulator The figure of layer；

S13, employing are formed on the substrate being formed with described gate insulator layer pattern with a patterning processes Including semiconductor layer and the figure of the first metal barrier；

S14, employing patterning processes are on the substrate being formed with semiconductor layer and the first metal barrier layer pattern Form the figure including etching barrier layer；

S15, employing sequentially form on the substrate being formed with etch stopper layer pattern with a patterning processes Including source-drain electrode layer and the figure of the second metal barrier.

Further, the substrate of etching barrier layer can be formed with by the method for sputtering or thermal evaporation Upper deposition layer of metal film layer, in the initial time section of depositing metal membrane layer, to sputtering or thermal evaporation cavity Inside it is passed through the oxygen O of preset ratio₂And/or nitrogen N₂。

If do not include the step forming etching barrier layer, described formation includes source-drain electrode layer, Yi Ji The figure of two metal barriers, for:

The substrate being formed with the figure including semiconductor layer and the first metal barrier is formed one layer of gold Belong to film layer；

Use a patterning processes formed described in include source-drain electrode layer, and the figure of the second metal barrier Shape；

Wherein, in the initial time section forming metallic diaphragm, in cavity, the oxygen of preset ratio it is passed through Or nitrogen or oxygen and the mixed gas of nitrogen.

For instance, it is preferred that see Figure 12, the method for the array base palte making top gate type TFT is specifically wrapped Include following steps:

S21, employing sequentially form on substrate with a patterning processes and include source-drain electrode layer, and second The figure of metal barrier；

S22, employing patterning processes are being formed with described source-drain electrode layer and the base of the second metal barrier layer pattern The figure including etching barrier layer is formed on plate；

S23, employing are formed on the substrate being formed with described etch stopper layer pattern with a patterning processes Including semiconductor layer and the figure of the first metal barrier；

S24, employing patterning processes are being formed with described semiconductor layer and the base of the first metal barrier layer pattern The figure including gate insulator is formed on plate；

S25, employing patterning processes are formed on the substrate being formed with described gate insulator layer pattern and include grid The figure of pole.

For instance, it is preferred that the manufacture method of the array base palte of the TFT shown in Figure 12, described formation bag Include source-drain electrode layer, and the figure of the second metal barrier, for:

Substrate is formed layer of metal film layer；Use a patterning processes to be formed and include source-drain electrode layer, with And the second metal barrier layer pattern；

Wherein, in the end time section forming metallic diaphragm, in cavity, the oxygen of preset ratio it is passed through Or nitrogen or oxygen and the mixed gas of nitrogen.

Further, the substrate of etching barrier layer can be formed with by the method for sputtering or thermal evaporation Upper deposition layer of metal film layer, in the end time section of depositing metal membrane layer, to sputtering or thermal evaporation cavity Inside it is passed through the oxygen of preset ratio or nitrogen or oxygen and the mixed gas of nitrogen.

In the embodiment of the said method of the present invention, described formation source electrode and the material of drain electrode and formation grid Material at least one be copper or copper alloy, be certainly not limited to this, the purpose of the embodiment of the present invention It is to use the first metal barrier to stop the phase of the material and the material of formation grid that form source electrode, drain electrode Counterdiffusion, other form grid, source electrode, the material of drain electrode and are also applied for this when possessing the strongest diffusibility Invention, such as gold, silver etc..Following all to form source electrode and the material of drain electrode and to form the material of grid and be Metallic copper illustrates.

The first metal barrier and the semiconductor layer that arrange with layer in the above embodiment of the present invention can use Commaterial is prepared from, when semiconductor layer is metal oxide semiconductor layer, and the first metal barrier Layer can use the material preparing metal oxide semiconductor layer, such as: can be indium gallium zinc oxide (IGZO), hafnium indium-zinc oxide (HIZO), indium-zinc oxide (IZO), amorphous indium-zinc oxide (a-InZnO), amorphous zinc oxide doped oxyfluoride (ZnO:F), indium-doped tin oxide oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄)、 Amorphous zinc oxide adulterated al oxide (ZnO:Al), amorphous oxide titanium doped niobium oxide (TiO₂:Nb)、 Chromium tin-oxide (Cd-Sn-O) or other metal-oxides.

The first metal barrier and the semiconductor layer that arrange with layer in the above embodiment of the present invention can use Same material is not prepared from, when semiconductor layer is metal oxide semiconductor layer, and the first metal barrier Layer can use copper oxide (CuO_x), copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x) etc., or, Use and different other metal-oxides of metal-oxide of formation semiconductor layer；When semiconductor layer is non- When crystal silicon or polysilicon semiconductor layer, the first metal barrier can use prepares metal-oxide semiconductor (MOS) The material of layer, it would however also be possible to employ copper oxide (CuO_x), copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x) Deng.

The first metal barrier and the semiconductor layer that arrange with layer in the above embodiment of the present invention can insulate Or on-insulated setting, as long as not affecting the realization of TFT function, in this no limit.Described insulation The method arranged can be multiple, the most directly uses cut mode, doping process or patterning processes Mode make both insulate mutually.

In order to preferably stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode, In the above embodiment of the present invention, first metal barrier area on orthographic projection direction should cover the most completely The area of lid source-drain electrode layer, but should ensure that mutual position relationship does not affect the realization of TFT performance.

In order to preferably stop the phase counterdiffusion of material of the material and the formation grid that form source electrode, drain electrode, In the above embodiment of the present invention, second metal barrier area on orthographic projection direction should cover the most completely The area of lid source-drain electrode layer, as long as not affecting the realization of TFT function, does not limits concrete position Fixed.

In the above embodiment of the present invention, described second metal barrier can use copper oxide (CuO_x)、 Copper nitride (CuN_y) or nitrogen copper oxide (CuN_yO_x) etc.；Formation metal-oxide half can also be used The material of conductor layer, such as: can be indium gallium zinc oxide (IGZO), hafnium indium-zinc oxide (HIZO), Indium-zinc oxide (IZO), amorphous indium-zinc oxide (a-InZnO), amorphous zinc oxide doped oxyfluoride (ZnO:F), indium-doped tin oxide oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide adulterated al oxide (ZnO:Al), Amorphous oxide titanium doped niobium oxide (TiO₂: Nb), chromium tin-oxide (Cd-Sn-O) or other metals Oxide.

In the above embodiment of the present invention, the first metal barrier and the second metal barrier are in orthographic projection direction On area and mutual position relationship the most too much limit, as long as not affecting the realization of TFT function i.e. Can.

Below as a example by making the array base palte shown in Fig. 9 or Figure 10, illustrate to make TFT or array base The preferred technological process of plate.

Illustrate as a example by metal-oxide TFT it should be noted that following, described first metal barrier 5 use the metal-oxide preparation identical with semiconductor layer 4 to be formed, described formation source electrode 8 and drain electrode 9 Material be copper, described second metal barrier 7 is copper oxide (CuO_x), copper nitride (CuN_y) or Nitrogen copper oxide (CuN_yO_x) etc..

Array substrate manufacturing method includes:

Step one: grid 2 and the forming process of gate line 21 figure.

Using sputtering or the method for thermal evaporation on substrate, deposit grid metal film layer, thickness is preferablyGrid 2 and gate line is formed by single exposure development, photoetching and etching technics 21 figures.Formed grid 2 and the figure of gate line 21 and position same as the prior art the most no longer Repeat.

The metallic diaphragm of described formation grid 2 and gate line 21 figure can be metallic copper (Cu), metal Chromium (Cr), tungsten (W), Titanium (Ti), metal tantalum (Ta), metal molybdenum (Mo) etc., or Person is the alloy of above-mentioned at least two metal.

Step 2: the forming process of gate insulator 3 figure.

By chemical vapour deposition technique (PECVD) successive sedimentation insulating barrier on the substrate complete step one, Thickness is preferablyThis insulating barrier is the insulating barrier of gate insulator 2 figure to be formed； Specifically, this insulating barrier can be silicon oxide or silicon nitride layer.Silicon oxide or silicon nitride layer can be Oxide, nitride or oxynitrides are formed by chemical vapour deposition technique with reacting gas.Described Reacting gas can be silane (SiH₄), ammonia (NH₃) and nitrogen (N₂) mixture, or be Silicon dichloride (SiH₂Cl₂), ammonia (NH₃) and nitrogen (N₂) mixture.

In order to improve the performance of oxide TFT, gate insulator 2 figure can be different by materials at two layers Insulating barrier is formed, and ground floor is silicon nitride (SiN_x), the second layer is silicon oxide (SiO_x), ground floor nitrogen SiClx (SiN_x) gate insulator that formed directly contacts with grid, second layer silicon oxide (SiO_x) Directly contact with semiconductor layer and the first metal barrier.Double-deck grid layer pattern is by double hyer insulation Layer is formed by single exposure development, photoetching and etching technics.

Step 3: semiconductor layer 4 and the forming process of the first metal barrier 5 figure.

On the substrate being formed with gate insulator 3, by sputtering method successive sedimentation metal oxide film Layer, thickness is preferablyHalf is formed by single exposure development, photoetching and etching technics Conductor layer 4 and the figure of the first metal barrier 5.

Described metal-oxide can be indium gallium zinc oxide (IGZO), hafnium indium-zinc oxide (HIZO), Indium-zinc oxide (IZO), amorphous indium-zinc oxide (a-InZnO), amorphous zinc oxide doped oxyfluoride (ZnO:F), indium-doped tin oxide oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum oxide (In₂O₃: Mo), chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide adulterated al oxide (ZnO:Al), Amorphous oxide titanium doped niobium oxide (TiO₂: Nb), chromium tin-oxide (Cd-Sn-O) or other metals Oxide.

First metal barrier 5 is positioned at the position corresponding with source-drain electrode layer to be formed and data wire 81, And the position corresponding with grid 2.

Semiconductor layer 4 and the first metal barrier 5 are arranged with layer, do not increase technological process.This step Form the first metal barrier 5 figure by a patterning process, do not increase relative to prior art Technological process, but achieve the isolation features of the metal ion of source-drain electrode layer and data wire, this structure is permissible Stop the diffusion of metal ion under the diffusion of metal ion, especially high-temperature technology well, improve The performance of TFT.

Step 4: the forming process of etch stopper layer pattern 6.

By PECVD method successive sedimentation insulating barrier on the substrate complete step 3, thickness is preferablyInsulating barrier is etching barrier layer 6, etching barrier layer 6 can select oxide, Nitride or oxynitrides, corresponding reacting gas can be silane (SiH₄), ammonia (NH₃)、 Nitrogen (N₂) or silicon dichloride (SiH₂Cl₂), ammonia (NH₃), nitrogen (N₂), with formation grid Insulating barrier is similar to, and in order to improve the performance of oxide TFT, etching barrier layer may be designed as two-layer, and first Layer is silicon nitride (SiN_x), the second layer is silicon oxide (SiO_x), silicon oxide (SiO_x) layer directly with gold Belong to oxide interface.Double-deck etching barrier layer 6 figure be developed by single exposure by double layer of insulation, Photoetching and etching technics are formed.

Step 5: the second metal barrier layer pattern 7 and source-drain electrode layer (i.e. source electrode 8 and drain electrode 9) figure Forming process.

By sputtering or the method for thermal evaporation, depositing metal copper film on substrate, thickness is preferablyAs a example by forming copper (Cu) metallic diaphragm: specifically, in deposition metal (Cu) In the initial time Δ t of film layer, in sputtering or thermal evaporation cavity, it is passed through oxygen (the O of preset ratio₂)、 Nitrogen (N₂) or the two mixed gas, form one layer of copper nitride (CuN_y) (pass through nitrogen N₂ Situation), copper oxide (CuO_x) (by oxygen O₂Situation) or nitrogen copper oxide (CuN_yO_x) (logical Cross O₂And N₂Mixed gas), thickness be preferablyCopper nitride (the CuN formed_y)、 Copper oxide (CuO_x) or nitrogen copper oxide (CuN_yO_x) it is the second metal barrier 7.

Described initial time Δ t can be arranged based on experience value.Copper nitride (CuN_y), copper oxide (CuO_x)、 Or nitrogen copper oxide (CuN_yO_x) the most stable, stable interface can be formed with oxide semiconductor layer, should Material has the diffusivity of prevention copper (Cu) ion, the metal oxide semiconductor layer (first under it Metal barrier 5) there is the diffusivity stoping copper (Cu) ion further, can effectively stop Penetrating copper (Cu) ion of copper nitride film, this design can stop copper (Cu) ion effectively Diffusion, also simplify production technology simultaneously, solve copper (Cu) and barrier metal simultaneously and combine and carve The problem that etching technique is difficult.

Within the t-Δ t time period, stop being passed through the oxygen (O of preset ratio in cavity₂), nitrogen (N₂) Or the mixed gas of the two.The metallic diaphragm that this stage is formed is copper (Cu) metallic diaphragm, Ye Jiyuan Pole and drain electrode, and data wire.Wherein, t can be understood as forming the second metal barrier layer pattern and source Total time required for drain electrode layer figure.

The second metal barrier 7, source-drain electrode layer is formed by single exposure development, photoetching and etching technics, And the figure of data wire 81.

For instance, it is preferred that the figure of the second metal barrier 7 and source electrode 8 and drain electrode 9, and data The figure of line 81 is identical, and the two is completely superposed.

Step 6: the forming process of passivation layer 10 figure.

By PECVD method deposit passivation layer 10 on the substrate complete step 5, thickness is preferablyPassivation layer 10 can select oxide, nitride or oxynitrides, silicon Reacting gas corresponding to oxidation can be silane (SiH₄), nitrogen oxide (N₂O)；Nitride or Person's oxynitrides correspondence reacting gas is silane (SiH₄), ammonia (NH₃), nitrogen (N₂) or two Silicon chloride (SiH₂Cl₂), ammonia (NH₃), nitrogen (N₂)；Passivation layer 10 can use aluminium oxide (Al₂O₃) Film layer, or the double-deck or barrier structure of multilamellar.

Additionally, exposure imaging, photoetching and etching technics can also be passed through in this process forms gate solder Region (Gate PAD) and source-drain electrode layer welding region (SD PAD), it is simple to subsequent conditioning circuit plate and gate line It is connected with data wire.

Specifically, the forming process of passivation layer 10 is: by being formed with source-drain electrode layer and data wire Coating one layer of organic resin on the substrate of figure, thickness is preferablyOrganic resin Can be benzocyclobutene (BCB), it is also possible to be other organic photosensitive material.

Coat one layer of organic resin, after single exposure development, photoetching and etching technics, form array The Gate PAD and SD PAD of outer peripheral areas on substrate.

Step 7: the forming process of pixel electrode figure 11.

By the method deposition electrically conducting transparent tunic layer of sputtering or thermal evaporation on the substrate complete step 6, Thickness is preferably

By forming pixel electrode 11 after single exposure development, photoetching and etching technics.Described pixel electrode 11 can be ITO or IZO, or other transparent metal oxide.

Form array base palte technological process and above-mentioned steps one to the step of top gate type metal-oxide TFT The seven array base palte technological processes forming bottom gate type metal-oxide TFT are similar to, and repeat no more here.

But formed the second metal barrier and 7 source electrodes 8, drain electrode 9 process different, this be because of For, the second metal barrier 7 is formed at above source-drain electrode layer after being, forming process is as follows:

On substrate, layer of metal film layer is deposited by the method for sputtering or thermal evaporation；

Wherein, in the end time section of depositing metal membrane layer, it is passed through pre-in sputtering or thermal evaporation cavity If the oxygen (O of ratio₂) and/or nitrogen (N₂)。

Wherein, the gas of preset ratio and the thickness of shape film forming layer and each technique of being passed through of the present invention Parameter is correlated with, and does not limit at this.

Embodiment seven: a kind of barrier layer.

The embodiment of the present invention provides a kind of barrier layer, is provided only with the first metal barrier for above-described embodiment The thin film transistor (TFT) of layer or array base palte stop the first metal barrier of the diffusion of copper or copper alloy.

Such as, it is preferred that described metal-oxide is to have prevention to form source electrode and the material of drain electrode and shape Become the copper oxide (CuO of the mutual diffusion function of the material of grid_x), described metal-oxide can be tool Indium gallium zinc oxide (IGZO) of semiconductor property, hafnium indium-zinc oxide (HIZO), indium zinc is had to aoxidize Thing (IZO), amorphous indium-zinc oxide (a-InZnO), amorphous zinc oxide doped oxyfluoride (ZnO:F), Indium-doped tin oxide oxide (In₂O₃: Sn), amorphous oxide indium doping molybdenum oxide (In₂O₃:Mo)、 Chromium tin-oxide (Cd₂SnO₄), amorphous zinc oxide adulterated al oxide (ZnO:Al), amorphous titanium oxide Doping niobium oxide (TiO₂: Nb), chromium tin-oxide (Cd-Sn-O) or other metal-oxides etc..

Such as, it is preferred that described metal nitride is to have prevention to form source electrode and the material of drain electrode and shape Become the copper metal nitride of the mutual diffusion function of the material of grid, such as copper nitride (CuN_y) etc..

Such as, it is preferred that described metal oxynitride be have stop the material forming source electrode and drain electrode with Form the copper metal oxynitride of the mutual diffusion function of the material of grid, for example, nitrogen copper oxide (CuN_yO_x) etc..

The embodiment of the present invention provides another kind of barrier layer, is provided with the first metal barrier for described simultaneously With the diffusion stoping copper or copper alloy in the thin film transistor (TFT) of the second metal barrier or array base palte the One metal barrier and/or the second metal barrier.

Described barrier layer is not limited to use in TFT or array base palte, may be used for any needs and stops that height expands Dissipate the structure of property metal ion, do not enumerate.

In sum, embodiments provide a kind of thin film transistor (TFT), exhausted with grid at source-drain electrode layer Being provided with the first metal barrier between edge layer, this first metal barrier effectively stops source-drain electrode layer metal Ion is to gate insulator and gate diffusions.Improve the performance of TFT, improve the image quality of image.Additionally, Described thin film transistor (TFT) is also provided with the second metal resistance between source-drain electrode layer and the first metal barrier Barrier, further stops source-drain electrode layer metal ion to gate insulator and gate diffusions, improves TFT Performance, improve image image quality.The array base palte of embodiment of the present invention offer and display device, respectively Including above-mentioned thin film transistor (TFT), it is achieved image quality is preferable, the display device that signal delay is less.Stop Layer forms the material of source electrode and drain electrode and the mutual diffusion function of the material forming grid for having prevention Metal-oxide, metal nitride or metal oxynitride, and metal-oxide, metal nitride or gold Belonging to nitrogen oxides is material more typically.

Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention The spirit and scope of invention.So, if these amendments of the present invention and modification belong to right of the present invention Require and within the scope of equivalent technologies, then the present invention is also intended to comprise these change and modification.

Claims

1. a thin film transistor (TFT), including:

Grid, source electrode, drain electrode, semiconductor layer, gate insulator and the first metal being positioned on substrate Barrier layer；Described gate insulator is between described grid and described semiconductor layer；Described first metal Barrier layer is between described source electrode, drain electrode and gate insulator；Wherein, described first metal barrier With described semiconductor layer with layer insulation setting, described first metal barrier prevention formation source electrode and drain electrode Material and the phase counterdiffusion of material forming grid.

Thin film transistor (TFT) the most according to claim 1, also include being positioned at described source electrode, drain electrode with Etching barrier layer between described semiconductor layer.

Thin film transistor (TFT) the most according to claim 2, wherein said formation source electrode and the material of drain electrode Material and in forming the material of grid at least one for copper or copper alloy.

Thin film transistor (TFT) the most according to claim 3, wherein said semiconductor layer is burning Thing semiconductor layer.

Thin film transistor (TFT) the most according to claim 4, wherein said first metal barrier uses The material identical with described semiconductor layer is made.

Thin film transistor (TFT) the most according to claim 4, wherein said first metal barrier is oxygen Change copper, copper nitride or nitrogen oxidation copper film layer.

Thin film transistor (TFT) the most according to claim 4, wherein said first metal barrier uses The metal oxide semiconductor material differed with described semiconductor layer is made.

Thin film transistor (TFT) the most according to claim 3, wherein said thin film transistor (TFT) also includes: Second metal barrier, described second metal barrier is positioned at described first metal barrier and described source Between pole, drain electrode, described second metal barrier stops the material forming source electrode and drain electrode and forms grid The phase counterdiffusion of material.

Thin film transistor (TFT) the most according to claim 8, wherein said formation source electrode and the material of drain electrode Material is copper or copper alloy.

Thin film transistor (TFT) the most according to claim 9, wherein said second metal barrier is oxygen Change copper, copper nitride, or nitrogen oxidation copper film layer.

11. thin film transistor (TFT)s according to claim 9, wherein said second metal barrier uses Metal oxide semiconductor material is made.

12. thin film transistor (TFT)s according to claim 8, the structure of wherein said thin film transistor (TFT) is:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Described source electrode, drain electrode are positioned on described second metal barrier；

Or the structure of described thin film transistor (TFT) is:

Described source electrode, drain electrode are positioned on described substrate；

Described second metal barrier is positioned in described source electrode, drain electrode；

Described gate insulator is positioned on described semiconductor layer；

Described grid is positioned on described gate insulator.

13. thin film transistor (TFT)s according to claim 1, the structure of wherein said thin film transistor (TFT) is:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Or the structure of described thin film transistor (TFT) is:

Described grid is positioned on described gate insulator.

14. thin film transistor (TFT)s according to claim 8, the structure of wherein said thin film transistor (TFT) is:

Described grid is positioned on described substrate；

Described gate insulator is positioned on described grid；

Or the structure of described thin film transistor (TFT) is:

Described grid is positioned on described gate insulator.

15. thin film transistor (TFT)s according to claim 3, wherein said first metal barrier is positioned at The position corresponding with described source electrode and drain electrode.

16. thin film transistor (TFT)s according to claim 8, wherein said second metal barrier is positioned at The position corresponding with described source electrode and drain electrode.

17. 1 kinds of array base paltes, brilliant including the thin film described in claim 1-7,13,15 arbitrary claims Body pipe.

18. array base paltes according to claim 17, wherein said array base palte also includes: number According to line and gate line, described data wire is connected with the source electrode of described thin film transistor (TFT), and described gate line is with thin The grid of film transistor is connected；

19. 1 kinds of array base paltes, including the thin film described in claim 8-12,14,16 arbitrary claims Transistor.

20. array base paltes according to claim 19, wherein said array base palte also includes: number According to line and gate line, described data wire is connected with the source electrode of described thin film transistor (TFT), and described gate line is with thin The grid of film transistor is connected；

21. 1 kinds of display devices, including the array base palte described in claim 17 or 18.

22. 1 kinds of display devices, including the array base palte described in claim 19 or 20.

The manufacture method of 23. 1 kinds of thin film transistor (TFT)s, including:

Described gate insulator between described grid and semiconductor layer, described first metal barrier position Between described source electrode, drain electrode and gate insulator, wherein, described first metal barrier and described half Conductor layer is arranged with layer insulation.

24. methods according to claim 23, also include the figure forming etching barrier layer, institute State etching barrier layer between described semiconductor layer and source electrode, drain electrode.

25. methods according to claim 24, wherein said semiconductor layer is by metal-oxide half Conductor material is made.

26. according to the method described in claim 24 or 25, also includes forming the second metal barrier Figure, described second metal barrier is between described first metal barrier and described source electrode, drain electrode.

27. methods according to claim 23, wherein said formation includes grid, source electrode, leakage Pole, semiconductor layer, gate insulator, the figure of the first metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

28. methods according to claim 26, wherein said formation includes grid, source electrode, leakage Pole, semiconductor layer, gate insulator, etching barrier layer, the first metal barrier and the second metal barrier The figure of layer, for:

Patterning processes is used to form the figure including grid on substrate；

Use formed on the substrate being formed with etch stopper layer pattern with patterning processes include source electrode, Drain electrode and the figure of the second metal barrier.

29. methods according to claim 26, wherein said formation includes grid, source electrode, leakage Pole, semiconductor layer, gate insulator, etching barrier layer, the first metal barrier and the second metal barrier The figure of layer, for:

30. methods according to claim 26, wherein said formation includes grid, source electrode, leakage Pole, semiconductor layer, gate insulator, the first metal barrier and the figure of the second metal barrier, for:

Patterning processes is used to form the figure including grid on substrate；

Use to be formed on the substrate being formed with the first metal barrier layer pattern with a patterning processes and include Source electrode, drain electrode and the figure of the second metal barrier.

31. methods according to claim 26, wherein said formation includes grid, source electrode, leakage Pole, semiconductor layer, gate insulator, the first metal barrier and the figure of the second metal barrier, for:

32. methods according to claim 28, the material of wherein said formation source electrode and drain electrode is Copper or copper alloy.

33. methods according to claim 29, the material of wherein said formation source electrode and drain electrode is Copper or copper alloy.

34. methods according to claim 30, the material of wherein said formation source electrode and drain electrode is Copper or copper alloy.

35. methods according to claim 31, the material of wherein said formation source electrode and drain electrode is Copper or copper alloy.

36. methods according to claim 28, the same patterning processes of wherein said employing is in shape Become to have to be formed on the substrate of etch stopper layer pattern and include source electrode, drain electrode and the figure of the second metal barrier Shape is:

Coating process is used to form copper or copper alloy on the substrate being formed with described etch stopper layer pattern Film layer；In forming the initial time section of described copper or tin-copper alloy film layer, in cavity, it is passed through preset ratio Oxygen, nitrogen or oxygen and the mixed gas of nitrogen formed copper or the oxide of copper alloy, nitride or Nitrogen oxides is for forming the second metal barrier, and copper or copper in addition to described second metal barrier close Golden membranous layer is used for forming source electrode and drain electrode；Single exposure, development, chemical wet etching step is used to be formed described Source electrode, drain electrode and the figure of the second metal barrier.

37. methods according to claim 30, the same patterning processes of wherein said employing is in shape Become to have to be formed on the substrate of the first metal barrier layer pattern and include source electrode, drain electrode and the second metal barrier Figure be:

Coating process is used to form copper or copper alloy on the substrate being formed with the first metal barrier layer pattern Film layer；In forming the initial time section of described copper or tin-copper alloy film layer, in cavity, it is passed through preset ratio Oxygen, nitrogen or oxygen and the mixed gas of nitrogen formed copper or the oxide of copper alloy, nitride or Nitrogen oxides is for forming the second metal barrier, and copper or copper in addition to described second metal barrier close Golden membranous layer is used for forming source electrode and drain electrode；Single exposure, development, chemical wet etching step is used to be formed described Source electrode, drain electrode and the figure of the second metal barrier.

38. according to the method described in claim 33 or 35, and wherein said employing is with a patterning processes On substrate, formation includes that the figure of source electrode, drain electrode and the second metal barrier is:

Coating process is used to form described copper or tin-copper alloy film layer on substrate；Forming described copper or copper conjunction In the end time section of golden membranous layer, in cavity, it is passed through the oxygen of preset ratio, nitrogen or oxygen and nitrogen Mixed gas form copper or the oxide of copper alloy, nitride or nitrogen oxides for forming the second metal Barrier layer, copper or tin-copper alloy film layer in addition to described second metal barrier are used for forming source electrode and leakage Pole；Single exposure, development, chemical wet etching step is used to form described source electrode, drain electrode and the second metal The figure on barrier layer.

39. 1 kinds of barrier layers, including for the array base palte described in the arbitrary claim of claim 17 or 18 First metal barrier of the diffusion of middle prevention copper or copper alloy.

40. according to the barrier layer described in claim 39, and the material on wherein said barrier layer is metal oxygen Compound, metal nitride or metal oxynitride.

41. barrier layers according to claim 40, wherein said metal-oxide is indium gallium zinc oxygen Compound or copper oxide.

42. barrier layers according to claim 40, wherein said metal nitride is copper nitride.

43. barrier layers according to claim 40, wherein said metal oxynitride is copper nitrogen oxygen Compound.

44. 1 kinds of barrier layers, including for the array base palte described in the arbitrary claim of claim 19 or 20 First metal barrier of the diffusion of middle prevention copper or copper alloy and/or the second metal barrier.

45. barrier layers according to claim 44, the material on wherein said barrier layer is metal oxygen Compound, metal nitride or metal oxynitride.

46. barrier layers according to claim 45, wherein said metal-oxide is indium gallium zinc oxygen Compound or copper oxide.

47. barrier layers according to claim 45, wherein said metal nitride is copper nitride.

48. barrier layers according to claim 45, wherein said metal oxynitride is copper nitrogen oxygen Compound.