CN104409103A - Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory - Google Patents
Novel two-dimensional coding reinforcing method and circuit arrangement for aerospace memory Download PDFInfo
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Abstract
A two-dimensional coding reinforcing method for aerospace memories. Low-complexity multiple bit error detection and correction method is introduced into the reinforcing method, and the multiple bit error detection and correction method can carry out detection and correction on arbitrary multiple bit error. The reinforcing method comprises the following steps: 1, reading the word width of the memory, and logically converting a word with width N into a (k1, k2) two-dimensional matrix form; 2, determining the line number k1 and the column number k2 of the two-dimensional matrix; 3, adding a horizontal error detection code in each line, adding a vertical parity check code in each column; 4, when a word in the memory occurs multiple bit upsets, indicating the row and column the error respectively by the horizontal error detection code and the vertical parity check code; and when the interval of discontinuous multiple bit errors is less than L, giving a wrong signal by the horizontal error detection code; and 5, according to the amendment information bit, amending the information bits, and completing the amendment.
Description
Technical Field
The invention relates to a two-dimensional coding reinforcing method and a circuit device for an aerospace memory.
Background
As integrated circuit process sizes and supply voltages decrease, memories are more sensitive to soft errors generated by spatial radiation environments and ground noise environments than ever before. The memory occupies more than 60% of the chip area of the integrated circuit system, and most failures in the system are caused by the memory, so the research on the memory reinforcing technology is one of the most important ways to improve the reliability of the integrated circuit system. Charged energetic particles, protons and neutrons in a space environment and alpha particles in a ground environment may generate single event upsets (single event upsets) and multiple bit upsets (multiple bit upsets) on a memory, thereby affecting the correctness of stored data]. When integrated circuit process dimensions are reduced below deep submicron: (<0.18 μm), the memory is not significantly affected by single event upsets, but tends to saturate. However, as the process size decreases, more memory cells can be placed on the same semiconductor wafer, and the distance between adjacent cells is continually decreasing. The probability of the memory being subject to multi-bit flips is greatly increased.
Hamming codes are one of the most common hardening techniques used in memory. However, hamming codes can only correct one bit, detect two bit errors, and cannot correct multi-bit flips that occur in memories.
The layout bit interleaving technique can reduce the multi-bit upset in the memory, and distributes the bit units on different words into adjacent units on a physical layout structure, thereby avoiding the simultaneous upset of a plurality of bit units on one word. However, the layout bit interleaving technology has certain limitations and defects: the bit interleaving technique makes word and column selection wirings of the memory longer, negatively affects area, data access time, and power consumption, and the above problem is more apparent as the number of bits interleaved increases.
Another method that can suppress multi-bit flips is multi-bit error correction code techniques. BCH codes, RS codes, hybrid codes, etc., can correct for multi-bit flips that occur in memory. A common drawback of these approaches is the large amount of delay, power consumption and area overhead required. In addition, their encoding and decoding circuits are more complex and require the multiplication operations of the higher order fields to be handled in the manner of look-up tables.
The multi-bit flip in the memory can also be corrected by a Built-in current detector (build in current sensors) in combination with a hamming code or parity check code. However, this approach requires the addition of a built-in current probe for each column of the memory, and the built-in current probes themselves are also sensitive to soft errors, possibly introducing additional errors. In addition, the method requires a plurality of cycles to complete the error location and correction, and is not suitable for the practical application of high-speed memories.
The two-dimensional correction code can effectively inhibit multi-bit upset in the memory, thereby improving the reliability of the memory. The two-dimensional correction code is constructed by adding a horizontal error code to each row of the memory, while adding a vertical error code to each column of the memory. In the prior art, when a word needs to be written into the memory array, the corresponding bit must be read out from each row first to update the vertical error code, which significantly increases the access delay and power consumption. In the prior art, the proposed scheme can only correct two bit errors. When the radiant energy increases further, they will not be able to correct more errors.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a novel two-dimensional correction code, designs an effective memory multi-bit upset strengthening scheme, and realizes the correction of multi-bit upset of any given width through lower hardware expense.
The technical solution of the invention is as follows:
a two-dimensional coding reinforcing method for an aerospace memory introduces a low-complexity multi-bit error detection and correction method, and the multi-bit error detection and correction method can detect and correct any multi-bit error.
The reinforcing method comprises the following steps:
step 1, reading the width of a memory word and setting a bit width asNIs converted into ak1, k2) In the form of a two-dimensional matrix of (c),k1representing the number of rows,k2representing the number of columns.
Step 2, determining the number of rows of the two-dimensional matrixk1Sum column numberk2。
And 3, inserting a horizontal error detection code and a vertical parity check code. Adding horizontal error detection codes into each row, and adding vertical parity check codes into each column;
step 4, when one word of the memory is inverted by multiple bits, the horizontal error detection code and the vertical parity check code respectively indicate the row and the column where the error occurs, and when the interval of discontinuous multiple-bit errors is less thanLAlthough the horizontal error detection code cannot correctly determine the number of errors, an error signal can still be given. Using the row location indicated by this error signal and the column location indicated by the parity code, either a continuous error or a discontinuous error can be located and corrected by flipping its value.
Step 5, according to the corrected information bitCorrecting the information bits in placeAnd finishing the correction.
The invention also provides a two-dimensional correction code reinforced memory circuit adopting the two-dimensional coding reinforcing method of the aerospace memory, as shown in figure 6, which comprises an encoder, a decoder, a memory and a MUX,
as shown in fig. 4, the encoder is implemented by writing Verilog code according to a calculation formula of the stored data of each detection bit and check bit, in the encoder, 8 groups of exclusive or logic are used to generate the detection code of the horizontal error detection code, 16 groups of buffers are used to enhance the driving capability of the data input end to the memory module, and the other 8 groups of exclusive or logic are used to generate the check bit of the vertical parity check code.
As shown in FIG. 5, the decoder is implemented by writing Verilog code to detect bitsD i ’And check bitC i ’The data are respectively generated by 8 groups of exclusive-OR logics, and correct data are output through 16 groups of exclusive-OR logics after judgment logic.
The MUX is provided with 16 data test ports and a test enabling port, correction test can be carried out on the two-dimensional correction code reinforced memory circuit through the MUX, and the method specifically comprises the following steps: firstly, writing data into a memory in a normal working mode; then, the test enabling end is set to be effective, a test mode is entered, test data are input, and data stored in a normal working mode are modified; and finally, reading the written data, and comparing whether the output result is consistent with the written data in the normal working mode. And if the output data is consistent with the written data, the two-dimensional correction code reinforced memory circuit is effective.
The memory is designed by adopting a layout division method, the layout division method is to consider the physical sequence of the layout of the memory cells, avoid the data bits with operational relationship from being too close to the redundancy bits during logic input, and divide and place the data bits, as shown in fig. 2, specifically: dividing a horizontal error detection code and a vertical parity check code by using information bits; the information bits and the corresponding check bits and detection bits having operational relationship need to be separated by a distance greater thanLSo as to ensure that the information bits and the redundant bits with operation relation can not generate errors at the same time.
Compared with the prior art, the invention has the beneficial effects that:
first, to avoid the problem of continuous update of vertical codes, the present invention splits the words of the memory into a two-dimensional matrix. Second, to reduce the hardware overhead of the consolidation scheme, a low complexity multi-bit error detection and correction method is used that can detect arbitrary consecutive errors. By combining with the vertical parity check code, the proposed two-dimensional correction code can correct both continuous and discontinuous multi-bit errors. Subsequently, a correction algorithm for multi-bit flip of the memory is given. Finally, the proposed scheme is subjected to circuit and layout design, and a 'layout division method' is proposed, so that the possible multi-bit upset in the redundant bit of the two-dimensional correction code is effectively inhibited by utilizing the layout structure of the memory cell, and the reliability of the memory is further improved. Therefore, the proposed multi-bit flip-flop reinforcing circuit of the memory has significantly higher reliability and lower hardware overhead compared to other multi-bit error correction codes.
Drawings
FIG. 1 is a two-dimensional correction code of data width 16 bits;
FIG. 2 illustrates several types of errors occurring in a memory;
FIG. 3 is a flowchart of a space memory two-dimensional coding reinforcement method according to the present application;
FIG. 4 is a two-dimensional correction code encoder circuit design;
FIG. 5 is a circuit design of a two-dimensional correction code decoder;
FIG. 6 is a multi-bit flip resistant memory system with test functionality;
fig. 7 is a layout structure of a 16-bit wide word.
Detailed Description
The invention is further described with reference to the following figures and examples.
The invention provides a two-dimensional coding reinforcing method for an aerospace memory, which introduces a low-complexity multi-bit error detection and correction method, and can detect and correct any multi-bit error.
The multi-bit error detection and correction method specifically comprises the following steps: the maximum number of errors in a multi-bit flip caused by a radiation event isLThen the required use of the probing capability in the memory system isLThe vertical error detection code of (1). To a device withNWord of bits, detection bits of horizontal error detection codeD i This can be calculated by the following detection bit equation:
wherein,the symbols represent an exclusive or,i,LandKtake a positive integer, andKis taken to satisfy，b i Representing the corresponding information bits in the memory, the encoding being effected by inputting the information bits into the encoder in accordance with a formula for detecting bits having a detection capability ofLHorizontal error detection code ofLEach detection bit performs a respective parity XOR computation.
For example, for oneL=4,NFor a memory of =8, the detection bits of the horizontal error detection code can be expressed as, , And. FromD i Can be learned if 1 toLAfter a successive error occurs, only one detection bit is affected. Therefore, the position is detected by monitoringD i In a changed mode, the effect that no more than one word is contained in one word can be realizedLA continuous error is detected. In the decoding process, if an error occurs in a received codeword, a detection bit is usedD i The resulting parity calculation results in an error signal.
The multi-bit error detection and correction method can realize the detection of multi-bit errors only by one-stage XOR logic of encoding and decoding, thereby having very low transmission delay and hardware overhead.
The reinforcing method comprises the following steps:
step 1, reading the width of a memory word and setting a bit width asNIs converted into ak1, k2) In the form of a two-dimensional matrix of (c),k1representing the number of rows,k2representing the number of columns.
The traditional method directly encodes the whole storage array, when accessing data of one word, the vertical check code needs to calculate the data of the whole storage array, and the redundant bit number of the vertical check code is the same as the data width in the memory, thereby bringing larger hardware redundancy.
Step 2, determining the number of rows of the two-dimensional matrixk1Sum column numberk2。
Is differentk1Andk2the values of (A) can bring different redundancy expenses, and the row number is reasonably selected with the aim of minimizing redundant bitsk1Sum column numberk2The value of (a) is selected,
the redundant bits are the sum of the number of bits of the detection bits of the horizontal error detection code and the number of bits of the check bits of the vertical parity check code.
Bit width of one word of memoryN=16Maximum number of errors of multi-bit flips caused by a radiation eventL=4When a 16-bit wide word is converted into a matrix form, the corresponding (A) and (B) arek1, k2) Values are (1, 16), (4, 4), (2, 8), i.e.、OrA matrix with L detection bits per row and one check bit per column according to the multi-bit error detection and correction method can be derivedThe number of bits of the detection bits and the check bits of the matrix is 4 and 16, the redundant bits are 20,the number of bits of the detection bits and the check bits of the matrix is 8 and 8, the redundant bits are 16,the number of bits of the detection bit and the check bit of the matrix is 16 and 4, the redundant bit is 20, and the redundant bit is selected according to the target being the least redundant bitk1=2，k2=8。
And 3, inserting a horizontal error detection code and a vertical parity check code. Adding horizontal error detection codes into each row, and adding vertical parity check codes into each column;
determined according to step 2 aboveA matrix into which corresponding detection bits and check bits are inserted, wherein D1,D2,D3And D4For the detection bits of the horizontal error detection code of the first row, D5,D6,D7And D8For the detection bits of the horizontal error detection code of the second row, the stored data of the respective detection bits can be obtained by the following equation.
i=(1,2,3,4)
i=(5,6,7,8)
C1-C8Are check bits, and the stored data of each check bit can be obtained by the following equation.
i=(1,2,3,…,8) ；
The encoder of the two-dimensional correction code can be realized by utilizing the calculation formula of the stored data of each detection bit and check bit through an exclusive OR logic.
Step 4, when one word of the memory is inverted by multiple bits, the horizontal error detection code and the vertical parity check code respectively indicate the row and the column where the error occurs, and when the interval of discontinuous multiple-bit errors is less thanLAlthough the level is wrongThe misdetection code cannot correctly determine the number of errors, but can still give an error signal. Using the row location indicated by this error signal and the column location indicated by the parity code, either a continuous error or a discontinuous error can be located and corrected by flipping its value.
The specific steps of correcting by inverting the value of the self are as follows:
step 4.1, generating decoding detection bit by received dataD i ’And decoding check bitsC i ’；；
Step 4.2, calculate horizontal syndromeS Di And a vertical syndromeS Ci ：
i=(1,2,3,…,8)
i=(1,2,3,…,8)
Step 4.3, when the horizontal syndrome of any bitS Di Valid, this indicates an error and is corrected by the following equation, whereBy decoding information bits to obtain modified information bits。
And 5, correcting the information bit according to the corrected information bit, and finishing correction.
The two-dimensional correction code provided by the invention can correct continuous errors and discontinuous errors. Fig. 2 shows different types of multi-bit flips, and the error correction capability of two-dimensional correction codes under different error types will be analyzed below. In types 1 and 2, whether the errors occur in the same row or different rows, consecutive errors can be detected by respective horizontal error detection codes. Detecting the signal once horizontalD i ’Effectively, the error can be corrected by the vertical parity check code. In type 3, the errors are discontinuous, so some bit errors (b)1And b5) And is not distinguishable by horizontal error detection codes. In this case, however, the horizontal error detection code will be based on b3And b4Information of (2), statement D3' and D4' effective. Thus incorporating a vertical check bit C1' and C5As a result of' all errors can be corrected. In type 4, if the spacing of errors is greater thanLThen this type of error is uncorrectable. However, the results of the radiation experiments show that the interval between the generation of multi-bit errors by a single radiation event hardly exceeds 3 bits. Thus, the errors that occur in type 4 are not present in a single radiation event, and have left the scope of investigation for single radiation event failures. The above-mentioned errors are only possible in more than two radiation events and can be corrected by erasure techniques.
As shown in fig. 3, the reinforcing method may also be used to perform reinforcing design on words with data widths of 32, 64, and 128 bits, etc. commonly used in memories.
The invention also provides a two-dimensional correction code reinforced memory circuit adopting the two-dimensional coding reinforcing method of the aerospace memory, as shown in figure 6, which comprises an encoder, a decoder, a memory and a MUX,
as shown in fig. 4, the encoder is implemented by writing Verilog code according to a calculation formula of the stored data of each detection bit and check bit, in the encoder, 8 groups of exclusive or logic are used to generate the detection code of the horizontal error detection code, 16 groups of buffers are used to enhance the driving capability of the data input end to the memory module, and the other 8 groups of exclusive or logic are used to generate the check bit of the vertical parity check code.
As shown in FIG. 5, the decoder is implemented by writing Verilog code to detect bitsD i ’And check bitC i ’The data are respectively generated by 8 groups of exclusive-OR logics, and correct data are output through 16 groups of exclusive-OR logics after judgment logic.
The MUX is provided with 16 data test ports and a test enabling port, correction test can be carried out on the two-dimensional correction code reinforced memory circuit through the MUX, and the method specifically comprises the following steps: firstly, writing data into a memory in a normal working mode; then, the test enabling end is set to be effective, a test mode is entered, test data are input, and data stored in a normal working mode are modified; and finally, reading the written data, and comparing whether the output result is consistent with the written data in the normal working mode. And if the output data is consistent with the written data, the two-dimensional correction code reinforced memory circuit is effective.
And when the MUX is set in a test mode, the reinforced memory system after the tape-out has testability on faults.
The two-dimensional correction code can effectively correct errors occurring in data bits in a memory, but when a redundant bit introduced by the two-dimensional correction code has an error, the correctness of corrected data is affected, and the problem cannot be solved in the conventional research. The following analyses are possible for the locations where errors may occur, for a total of four possibilities: first, errors all occur in the horizontal error detection code; second, errors all occur in the vertical parity code; third, errors occur in both the horizontal error detection code (the original is a multi-bit error code) and the vertical parity code; fourth, errors occur in the information bits and the corresponding check bits.
The memory is designed by adopting a layout division method, the layout division method is to consider the physical sequence of the layout of the memory cells, avoid the data bits with operational relationship from being too close to the redundancy bits during logic input, and divide and place the data bits, as shown in fig. 2, specifically: dividing a horizontal error detection code and a vertical parity check code by using information bits; the information bits and the corresponding check bits and detection bits having operational relationship need to be separated by a distance greater thanLSo as to ensure that the information bits and the redundant bits with operation relation can not generate errors at the same time.
The layout division method of the invention fully utilizes the layout structure of the memory cell and inhibits the error on the redundant bit.
The memory is a radiation-resistant hardened memory with a data width of 16 bits, a word number of 4096 and a capacity of 64K. The two-dimensional correction code reinforced memory circuit and the layout thereof are designed by a 0.18 mu m standard cell process library of a Hejian (HJ). The function of the two-dimensional correction code reinforced memory circuit is verified by using ModelSim, the performance parameters and the gate-level netlist are obtained through a Synopsys Design Compiler, and layout and wiring are carried out through a Cadence SOC Encounter.
The area, power consumption and delay parameters of the proposed two-dimensional correction circuit and other correction circuits are shown in table 1. With the Hamming code as a reference, it can be seen from the results in Table 1 that the performance parameters of the two-dimensional correction circuit are significantly better than those of other correction circuits. The area, delay, and power consumption of the two-dimensional correction circuit having an error correction capability of 4 are 51%, 50%, and 113% of the hamming code, respectively. From table 1, it can be found that the delay of the two-dimensional correction circuit having the error correction capability of 4 is smaller than that of the two-dimensional correction circuit having the error correction capability of 2. This is because the correction circuit with the error correction capability of 4 encodes a lower logic depth, resulting in a smaller delay. Therefore, after the two-dimensional correction scheme provided by the invention is used, the performance of the correction circuit is hardly influenced by the increase of the error correction capability, and only corresponding redundant bits need to be added.
Table 1: delay parameter list for area and power consumption of correction circuit
In summary, the present invention provides an effective two-dimensional correction circuit, which achieves the purpose of suppressing multi-bit flip of a memory with low hardware overhead. The proposed two-dimensional correction scheme can correct errors with any given width, and meanwhile, the higher reliability of the memory can be ensured by combining the proposed layout segmentation method. The reliability and performance analysis result shows that the radiation-resistant memory can well meet the application requirement under the high-energy space radiation environment, and the performance of the correction circuit is superior to that of the existing multi-bit error correction code circuit.
The above-described embodiments are merely illustrative of the present invention, and should not be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (10)
1. A two-dimensional coding reinforcing method for a space navigation memory is characterized by comprising the following steps: the reinforcement method introduces a low-complexity multi-bit error detection and correction method, the multi-bit error detection and correction method can detect and correct any multi-bit error, and the reinforcement method comprises the following steps:
step 1, reading the width of a memory word and setting a bit width asNIs converted into ak1, k2) In the form of a two-dimensional matrix of (c),k1representing the number of rows,k2represents the number of columns;
step 2, determining the number of rows of the two-dimensional matrixk1Sum column numberk2，
Is differentk1Andk2the values of (A) can bring different redundancy expenses, and the row number is reasonably selected with the aim of minimizing redundant bitsk1Sum column numberk2The value of (a) is selected,
the redundant bit is the sum of the number of bits of the detection bit of the horizontal error detection code and the number of bits of the check bit of the vertical parity check code;
step 3, inserting a horizontal error detection code and a vertical parity check code, adding the horizontal error detection code into each row, and adding the vertical parity check code into each column;
step 4, when one word of the memory is inverted by multiple bits, the horizontal error detection code and the vertical parity check code respectively indicate the row and the column where the error occurs, and when the interval of discontinuous multiple-bit errors is less thanLWhen the error detection code is used, although the horizontal error detection code cannot correctly judge the number of errors, an error signal can still be given, and by utilizing the row position indicated by the error signal and the column position indicated by the parity check code, whether continuous errors or discontinuous errors can be positioned and corrected by turning the value of the error signal;
step 5, according to the corrected information bitCorrectionAnd finishing the correction of the information bit.
2. The space memory two-dimensional coding reinforcing method according to claim 1, characterized in that: the multi-bit error detection and correction method is characterized in that the maximum error number of multi-bit upset caused by one radiation event isLThen the required use of the probing capability in the memory system isLFor a vertical error detection code ofNWord of bits, detection bits of horizontal error detection codeD i This can be calculated by the following detection bit equation:
，
wherein, the symbolRepresents an exclusive or, and represents a logical xor,i,LandKtake a positive integer, andKthe value of (A) is satisfied,b i representing the corresponding information bits in the memory, the encoding being effected by inputting the information bits into the encoder in accordance with a formula for detecting bits having a detection capability ofLHorizontal error detection code ofLEach detection bit performs a corresponding parity XOR calculation;
the multi-bit error detection and correction method can realize the detection of multi-bit errors only by one-level XOR logic of encoding and decoding, and has very low transmission delay and hardware overhead.
3. The space memory two-dimensional coding reinforcing method according to claim 2, characterized in that: in the step 2, in the step of processing,
bit width of one word of memoryN=16Maximum number of errors of multi-bit flips caused by a radiation eventL=4When a 16-bit wide word is converted into a matrix form, the corresponding (A) and (B) arek1, k2) Values are (1, 16), (4, 4), (2, 8), i.e.、OrA matrix according to said multi-bit error detection and correction method, eachA row with L detection bits and each column should have a check bit, then one can deriveThe number of bits of the detection bits and the check bits of the matrix is 4 and 16, the redundant bits are 20,the number of bits of the detection bits and the check bits of the matrix is 8 and 8, the redundant bits are 16,the number of bits of the detection bit and the check bit of the matrix is 16 and 4, the redundant bit is 20, and the redundant bit is selected according to the target being the least redundant bitk1=2，k2=8。
4. The two-dimensional coding reinforcing method for aerospace memory according to claim 3, characterized in that: in the step 3, the step of processing the image,
determined according to said step 2A matrix into which corresponding detection bits and check bits are inserted, wherein D1,D2,D3And D4For the detection bits of the horizontal error detection code of the first row, D5,D6,D7And D8For the detection bits of the horizontal error detection code of the second row, the stored data of each detection bit can be obtained by the following equation:
，i=(1,2,3,4)，
，i=(5,6,7,8) ，
C1-C8is schoolThe check bits, the stored data of each check bit, can be obtained by the following equation:
i=(1,2,3,…,8)。
5. the space memory two-dimensional coding reinforcing method according to claim 4, characterized in that: in the step 4, the specific step of correcting by inverting the value of the self-body is as follows:
step 4.1, generating decoding detection bit by received dataD i ’And decoding check bitsC i ’；
Step 4.2, calculate horizontal syndromeS Di And a vertical syndromeS Ci ：
， i=(1,2,3,…,8)，
，i=(1,2,3,…,8) ；
Step 4.3, when the horizontal syndrome of any bitS Di Valid, this indicates an error and is corrected by the following equation, whereBy decoding information bits to obtain modified information bits：
。
6. The two-dimensional coding reinforcing method for aerospace memory according to any one of claims 1-5, wherein: the two-dimensional coding reinforcing method can also be used for reinforcing and designing words with data widths of 32, 64 and 128 bits and the like which are commonly used in a memory.
7. A two-dimensional correction code reinforced memory circuit using the two-dimensional code reinforcing method for an aerospace memory according to any one of claims 1 to 6, characterized in that: which comprises an encoder, a decoder, a memory and a MUX,
the encoder writes Verilog codes through a calculation formula of stored data of each detection bit and check bit, 8 groups of exclusive OR logics are used for generating detection codes of horizontal error detection codes in the encoder, 16 groups of buffers are used for enhancing the driving capability of a data input end to a memory module, and the other 8 groups of exclusive OR logics are used for generating check bits of vertical parity check codes;
the decoder is realized by writing Verilog code and detecting bitsD i ’And check bitC i ’Respectively generated by 8 groups of exclusive-OR logics, and finally outputting correct data through 16 groups of exclusive-OR logics after judgment logic;
the MUX is provided with 16 data test ports and a test enabling port, correction test can be conducted on the two-dimensional correction code reinforced memory circuit through the MUX, and the reinforced memory system after the stream chip is tested and set has testability on faults;
the memory is designed by adopting a layout division method, wherein the layout division method is to consider the physical sequence of the layout of the memory cells, avoid the data bits with operational relationship from being too close to the redundancy bits during logic input and divide and put the data bits.
8. The two-dimensional correction code-hardened memory according to claim 7, wherein the MUX correction test process is specifically:
firstly, writing data into a memory in a normal working mode;
then, the test enabling end is set to be effective, a test mode is entered, test data are input, and data stored in a normal working mode are modified;
finally, reading the written data, and comparing whether the output result is consistent with the data written in the normal working mode;
and if the output data is consistent with the written data, the two-dimensional correction code reinforced memory circuit is effective.
9. The two-dimensional correction code-hardened memory device of claim 7, wherein:
the layout segmentation method specifically comprises the following steps: dividing a horizontal error detection code and a vertical parity check code by using information bits; the information bits and the corresponding check bits and detection bits having operational relationship need to be separated by a distance greater thanLSo as to ensure that the information bits and the redundant bits with operation relation can not generate errors at the same time.
10. A two-dimensional correction code hardening memory according to claim 7, wherein said memory is a radiation hardening memory with a data width of 16 bits, a word count of 4096, and a capacity of 64K; the design of the two-dimensional correction code reinforced memory circuit and the layout thereof is realized by a 0.18 mu m standard unit process library of a Hejian (HJ); the function of the two-dimensional correction code reinforced memory circuit is verified by using ModelSim, the performance parameters and the gate-level netlist are obtained through a Synopsys Design Compiler, and layout and wiring are carried out through a Cadence SOC Encounter.
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| CN107845404A (en) * | 2017-10-30 | 2018-03-27 | 中北大学 | A kind of new low redundancy two-dimensional matrix code carries out reinforcement means to memory |
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| CN110931074A (en) * | 2019-11-25 | 2020-03-27 | 北京时代民芯科技有限公司 | Optional bit width error correction and detection circuit for single event upset resistant memory |
| CN110931074B (en) * | 2019-11-25 | 2021-09-28 | 北京时代民芯科技有限公司 | Optional bit width error correction and detection circuit for single event upset resistant memory |
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