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CN103515304B - 无蚀刻损伤和电子系统级(esl)的双镶嵌金属互连件 - Google Patents

无蚀刻损伤和电子系统级(esl)的双镶嵌金属互连件 Download PDF

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CN103515304B
CN103515304B CN201210530680.9A CN201210530680A CN103515304B CN 103515304 B CN103515304 B CN 103515304B CN 201210530680 A CN201210530680 A CN 201210530680A CN 103515304 B CN103515304 B CN 103515304B
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dielectric
layer
hole
low
etching
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CN103515304A (zh
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辛书尼
李忠儒
包天一
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种形成用于半导体器件的双镶嵌金属互连件的方法。该方法包括形成低k介电层，形成穿过低k介电层的通孔，沉积牺牲层，形成穿过牺牲层的沟槽，用金属填充通孔和沟槽，去除牺牲层，然后沉积超低k介电层以填充在沟槽之间。该方法允许形成用于双镶嵌结构的第二层的超低k介电层同时避免通过诸如沟槽蚀刻和沟槽金属沉积的工艺对该层的损伤。该方法的另一优点为避免通孔层电介质和沟槽层电介质之间出现蚀刻终止层。本发明提供了无蚀刻损伤和电子系统级(ESL)的双镶嵌金属互连件。

Description

无蚀刻损伤和电子系统级(ESL)的双镶嵌金属互连件
技术领域
本发明涉及半导体器件，更具体而言，涉及用于形成包含超低k电介质的双镶嵌金属互连件的工艺、所得的结构以及包括这些结构的器件。
背景技术
多年的研究致力于减小集成电路(IC)的关键尺寸(CD)和结构密度。当密度增大时，电阻电容(RC)延迟时间已成为电路性能的一个限制因素。为减少RC延迟，期望用具有较低介电常数的材料来替换镶嵌金属互连结构中的电介质。这些材料被称作低k电介质或超低k电介质。低k电介质是介电常数小于SiO2的介电常数的材料。SiO2的介电常数为约4.0。超低k电介质是介电常数为约2.1或更小的材料。
在镶嵌金属互连结构中使用超低k电介质的理论优势被将这些材料集成到制造工艺中的实际困难抵消。超低k电介质通常具有大孔和高的总孔隙率。这些性质使得超低k介电层在高能量等离子体蚀刻期间易于受到入侵和损伤，尤其是当蚀刻气体包括氧气时。蚀刻损伤可以降低器件的可靠性并抵消由低k电介质转换为超低k电介质获得的RC性能增益。对以生产具有减少RC延迟的可靠器件的方法将超低k电介质结合到半导体器件中的经济性工艺具有盼望已久的需要。
发明内容
本发明提供了一种形成用于半导体器件的双镶嵌金属互连件的方法。该方法包括形成第一介电层，形成穿过该层的通孔，在第一介电层上方沉积牺牲层，以及形成穿过牺牲层的沟槽。如果在形成通孔之后沉积牺牲层并且牺牲层的材料进入通孔，则从通孔去除牺牲材料。然后用金属填充通孔和沟槽。然后去除牺牲层。然后在第一介电层上方形成第二介电层以填充在金属填充的沟槽之间。第二介电层与第一介电层具有以下所述内容中的一处或多处区别：第二介电层具有更低的等效介电常数，第二介电层具有更高的孔隙率，以及第二介电层具有气隙。该方法允许形成用于双镶嵌结构的第二层的超低k介电层同时避免诸如沟槽蚀刻和沟槽金属沉积的工艺对该层的损伤。
本发明还提供可以通过前述工艺形成的双镶嵌金属互连结构以及包括这些结构的半导体器件。双镶嵌结构的第一层包括位于第一电介质区域中的金属填充的通孔。双镶嵌结构的第二层包括位于第二电介质区域中的金属填充的沟槽。第一层电介质和第二层电介质是不同的。双镶嵌结构的特征还在于在第一层电介质和第二层电介质之间无蚀刻终止层。该结构还可以具有可以是区别特征的以下特征中的一个或多个：气隙在第二介电层中，而不在第一介电层中；第二介电层的等效介电常数小于2.1，而第一介电层的等效介电常数则不；第二介电层具有20％或更多的孔隙率，而第一介电层则没有；第二介电层中无蚀刻损伤，且填充沟槽和通孔的金属是基于铜的金属。
该总结的主要目的是以简明的形式介绍发明人的某些构思以便于理解随后的更多详细说明。该总结并不是对发明人的每一个能够被称之为“发明”的构思或构思的每一种组合的全面描述。对于本领域普通技术人员来说，通过以下与附图一起进行的详细描述会想到发明人的其它构思。本文公开的特定内容可以是广义的、狭义的，并且可以以各种方式与发明人要求的作为他们保留用于随后的权利要求的发明的最终声明相结合。
一方面，本发明提供了一种形成双镶嵌铜互连结构的方法，包括：在衬底上方沉积第一介电层；在所述第一介电层上方沉积牺牲层；蚀刻延伸穿过所述牺牲层但未穿过所述第一介电层的沟槽；在前述两个步骤中的一个或两个之前或之后，蚀刻通孔穿过所述第一介电层；沉积导电材料以填充所述沟槽和所述通孔并形成镶嵌结构，所述镶嵌结构包括位于第一层电介质区域中的导电材料填充的通孔和位于牺牲层材料区域中的导电材料填充的沟槽；去除所述牺牲层；以及沉积第二介电层以形成镶嵌结构，所述镶嵌结构包括位于所述第一层电介质区域中的铜填充的通孔和位于第二层电介质区域中的导电材料填充的沟槽，其中所述第一层电介质的孔隙率小于20％，而所述第二层电介质的孔隙率大于20％。
在所述的方法中，在沉积所述牺牲层之前蚀刻所述通孔穿过所述第一介电层。
在所述的方法中，在沉积所述牺牲层之前蚀刻所述通孔穿过所述第一介电层，其中：沉积所述牺牲层用所述牺牲层的材料填充所述通孔；以及在室中蚀刻所述沟槽并且在从该室取出衬底之前通过在该室中进一步蚀刻从所述通孔去除所述牺牲层材料。
在所述的方法中，在沉积所述牺牲层之前蚀刻所述通孔穿过所述第一介电层，其中，所述通孔的位置由用作蚀刻所述通孔的掩模的光刻胶决定。
在所述的方法中，通过非共形沉积工艺沉积所述第二介电层，在所述第二介电层中留下气隙。
在所述的方法中，所述第一介电层的等效介电常数大于2.1且小于3.5，而所述第二介电层的等效介电常数小于2.1。
另一方面，本发明提供了一种半导体器件制造工艺，包括：提供半导体衬底；通过前段工艺加工在所述衬底上形成栅极结构；在所述栅极结构上方形成低k介电层；图案化通孔穿过所述低k介电层；在所述低k介电层上方形成牺牲层；图案化沟槽穿过所述牺牲层；用金属填充所述通孔和所述沟槽；去除所述牺牲层；在所述低k介电层上方形成超低k介电层；以及其中所述超低k介电层比所述低k介电层具有更低的介电常数。
在所述的工艺中，通过非共形沉积工艺沉积所述超低k介电层。
在所述的工艺中，不使用硬掩模图案化所述通孔穿过所述低k介电层。
在所述的工艺中，所述低k介电层的等效介电常数大于2.1，而所述超低k介电层的等效介电常数小于2.1。
在所述的工艺中，所述低k介电层比所述超低k介电层具有更低的孔隙率。
在所述的工艺中，形成没有气隙的所述低k介电层，而形成具有气隙的所述超低k介电层。
在所述的工艺中，所述牺牲层包括非晶碳。
在所述的工艺中，所述牺牲层包括非晶碳，其中，所述第一介电层是有机硅酸盐玻璃。
在所述的工艺中，所述牺牲层包括非晶碳，其中，所述第一介电层是有机硅酸盐玻璃，其中，采用含有NH3或含有N2和H2组合的蚀刻气体通过等离子体蚀刻图案化所述沟槽。
在所述的工艺中，去除所述牺牲层包括采用相对于组成所述低k介电层的材料优先去除组成所述牺牲层的材料的蚀刻条件进行蚀刻。
又一方面，本发明提供了一种包括双镶嵌金属互连结构的半导体器件，包括：所述双镶嵌结构的第一层，包括位于第一电介质区域中的金属填充的通孔；以及所述双镶嵌结构的第二层，包括位于第二电介质区域中的金属填充的沟槽；其中所述双镶嵌结构的特征还在于在所述第一层和所述第二层之间无蚀刻终止层；以及其中所述第二层包括气隙，所述气隙大幅减小该层的等效介电常数，而所述第一层不包括所述气隙。
在所述的器件中，所述第二电介质无蚀刻损伤。
在所述的器件中，所述第一电介质的孔隙率小于20％，而所述第二电介质的孔隙率大于20％。
在所述的器件中：所述第一电介质的等效介电常数大于2.1且小于3.5；以及所述第二电介质的等效介电常数小于2.1。
附图说明
图1提供本发明的示例性工艺。
图2示出根据本发明的用于形成双镶嵌结构的示例性起始点。
图3示出形成金属覆盖层后的图2的结构。
图4示出形成第一介电层后的图3的结构。
图5示出在第一介电层上方形成图案化的掩模并蚀刻以形成穿过第一介电层的通孔以及去除掩模后的图4的结构。
图6示出形成牺牲层后的图5的结构。
图7示出在牺牲层上方形成硬掩模并对其进行图案化后的图6的结构。
图8示出在蚀刻以形成穿过牺牲层的沟槽以及从通孔去除牺牲层后的图7的结构。
图9示出在用金属填充通孔和沟槽后的图8的结构。
图10示出在化学机械抛光和形成第二金属覆盖层后的图9的结构。
图11示出去除牺牲层后的图10的结构。
图12示出沉积第二介电层后的图11的结构。
图13示出化学机械抛光后的图12的结构。
图14提供图1工艺中的步骤106的可选顺序。
图15提供图1工艺中的步骤106的另一可选顺序。
具体实施方式
图1提供形成双镶嵌结构225的工艺100的步骤的示例性顺序。图2至13示出随着该工艺进展的衬底200。工艺100开始于步骤101，步骤101为提供衬底200，其为制造中间阶段的半导体器件。衬底200包括半导体201和在前段工艺(FEOL)加工期间形成的一个或多个器件结构。工艺100将双镶嵌金属互连件225加入到衬底200。
在可以包括nMOS和pMOS区域的衬底200的区域的上方形成双镶嵌结构225。半导体的实例包括但不限于硅、绝缘体上硅(SOI)、Ge、SiC、GaAs、GaAlAs、InP、GaN、SiGe。在FEOL加工期间形成的器件结构可以包括但不限于存储器器件；逻辑器件；FET及其元件，诸如源极区、漏极区和栅电极；有源器件；无源器件和这些的组合。衬底200也可以包括绝缘体、导体和先前形成的互连结构，包括在后段工艺(BEOL)加工的早期阶段期间形成的结构。衬底200包括终端203。通过工艺100形成的双镶嵌结构包括与终端203接触的通孔209，如将在下面更全面理解的。
步骤103为在终端203上形成金属覆盖层205的可选步骤。覆盖层205可以包括一层或多层。覆盖层可以提供以下功能中的一种或多种：保护下面的材料在后续加工期间免受损伤；在将要形成的镶嵌金属217和终端203的金属之间提供界面；提供扩散阻挡物；以及阻止电迁移。覆盖层材料的实例包括但不限于钨(W)、钴(Co)、钴钨磷化物(CoWP)和钴钨硼酸盐(CoWB)。在阻止电迁移和减少RC延迟方面，含钴覆盖层205是特别合适的。可以通过任何合适的工艺或工艺的组合形成覆盖层205。化学镀(自动催化)工艺可以有效地仅在终端203上而不在衬底200的其它表面提供覆盖层205。
图1的步骤105为形成第一介电层207，其通常是低k介电层。可以使用任何合适的电介质。可以适用于第一介电层207的低k电介质的实例包括有机硅酸盐玻璃(OSG)，诸如碳掺杂的二氧化硅、氟掺杂的二氧化硅(又被称为氟化硅玻璃(或FSG))和有机聚合物低k电介质。有机聚合物低k电介质的实例包括聚芳醚(polyaryleneether)、聚酰亚胺(PI)、苯并环丁烯和非晶聚四氟乙烯(PTFE)。可以通过任何合适的工艺形成第一介电层207，其中适合性取决于所使用的材料。沉积第一介电层207的工艺的实例包括旋涂和CVD工艺。
介电层具有等效介电常数，其是层中所用的电介质和层的物理结构的函数。将孔隙率和气隙引入到介电层中减小层的等效介电常数，然而，孔隙率和气隙也使得层在结构上更脆弱且更易于遭受蚀刻损伤。考虑到后来的这些影响因素，在一个实施例中第一介电层207具有小于20％的孔隙率，而在一个实施例中形成没有气隙的第一介电层207。孔隙率是分布在形成介电层的整个电介质材料中的空隙空间，而气隙是除由介电材料填充的层间隔以外的层间隔中较大的空隙。在通过非共形沉积工艺沉积介电层时，气隙与层的几何形状相关并包括在角落和其它凹槽中形成的空隙。
低孔隙率和无气隙通常意味着第一介电层207的等效介电常数为至少约2.1。通常可以实现介电常数介于约2.4至3.5范围内的第一介电层207而不会过度损害得到的双镶嵌结构225的结构稳定性。落在该范围下端的介电常数适合于为得到的双镶嵌结构225提供低电容。第一介电层207的等效介电常数一般小于2.9，通常接近于2.4。
步骤107为形成穿过第一介电层207的通孔209。举例来说，通常通过包括光刻和各向异性高能量等离子体蚀刻的工艺来形成通孔209。光刻通常包括用光刻胶涂布衬底，根据期望的通孔图案选择性地使光刻胶曝光，将光刻胶显影，以及使用光刻胶作为蚀刻掩模来蚀刻出通孔209或蚀刻硬掩模，该硬掩模变成用于蚀刻出通孔209的蚀刻掩模。
在一个实施例中，如果在第一介电层207上方直接形成硬掩模，在进一步加工前去除硬掩模。硬掩模可以如同蚀刻终止层那样显著地增大电容。避免使用硬掩模通常比去除硬掩模更容易些，并且减少对第一介电层207的污染和损伤。例如，通常可以使用图案化的光刻胶作为蚀刻掩模来蚀刻OSG电介质。可以通过无损伤等离子体蚀刻或湿法工艺从第一电介质207去除光刻胶。
步骤109为在第一介电层207的上方形成牺牲层211。任何合适的材料可以用于牺牲层211。易于去除是做出选择时所要考虑的一个因素。另一考虑因素是易于识别和实施优先去除第一介电层207的材料上方的牺牲材料的蚀刻工艺。牺牲层211可以是通过在约250℃到约450℃之间的温度下的热处理、通过UV处理或通过这些处理的组合分解和/或蒸发的材料。这些材料的实例包括聚合物，诸如聚酰亚胺(PI)、聚丙二醇(PPG)、聚丁二烯(PB)、聚乙二醇(PEG)和聚己内酯二醇(PCL)。非晶碳通常是用于牺牲层211的合适的材料。通常可以通过对第一介电层207产生很小的损伤或不产生损伤的蚀刻工艺去除非晶碳。
步骤111和113形成穿过牺牲层211的沟槽215。这通常包括光刻。步骤111为形成掩模213。掩模213可以是光刻胶或硬掩模。形成硬掩模包括：形成硬掩模材料层，在硬掩模层的上方形成光刻胶层，根据期望的沟槽图案选择性地使光刻胶曝光，将光刻胶显影，使用图案化的光刻胶蚀刻沟槽图案穿过硬掩模层以形成图案化的硬掩模213，以及使用图案化的硬掩模213来限制高能量等离子体蚀刻以得到用于沟槽215的期望图案。
可以通过任何合适的工艺通过掩模213蚀刻出沟槽215。合适的工艺可以包括一个或多个步骤。例如，可以使用非选择性蚀刻或仅在牺牲层材料和第一介电层207的材料之间表现出有限的选择性的蚀刻工艺来蚀刻部分、大部分或全部穿过牺牲层211的沟槽。例如，可以使用非选择性蚀刻，直到暴露出介电层207。当介电层207暴露出来时，为了避免损伤介电层207，可以期望改变蚀刻化学物质和减慢蚀刻工艺。最初使用非选择性蚀刻或较少选择性蚀刻工艺可以加速整个蚀刻。
另一方面，对整个步骤113来说，使用单个蚀刻工艺可能是适合且方便的。例如，当牺牲层211由非晶碳形成并且介电层207是OSG时，选择性工艺可以是在蚀刻气体中使用N2和H2或者NH3的高能量等离子体蚀刻。使用单个蚀刻进行整个步骤113具有诸如易于应用和结果一致性的优点。
步骤113包括打通(open)通孔209。如果在形成牺牲层211之前蚀刻通孔209，通孔209通常会填充有牺牲层211的材料。如果通孔的形成延至形成牺牲层211之后，那么打通通孔209就不包括在步骤113中。当通孔209填充有牺牲层211的材料时，随着沟槽蚀刻工艺的继续可以方便地去除该材料。蚀刻条件可以在整个蚀刻过程中保持不变或随着蚀刻的进行而发生改变。蚀刻条件可以如上述所述或仅当蚀刻接近最后阶段以及金属盖顶205暴露出来时发生改变。尽管蚀刻条件改变，但整个工艺通常可以在一个蚀刻室内实施，这可以减少加工时间。
步骤115为用导电金属217填充通孔209和沟槽215。导电金属217可以是例如Cu、Al、Au、Ag、W和它们的合金。可以作为具有不同组分的多层提供金属217。可以通过任何合适的工艺填充金属217。合适的工艺可以包括化学镀、电镀、溅射沉积和化学汽相沉积(CVD)。
虽然金属217可以是任何合适的金属或金属的组合，但本发明的工艺尤其适合使用铜(Cu)。如本文用来描述填充通孔209和沟槽215的金属，铜包括纯铜、含痕量杂质的铜以及大部分是铜的合金。铜可以与少量的元素(诸如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆)形成合金。铜提供较低的电阻但与现有技术中许多工艺不兼容。
铜的化学镀通常包括形成铜晶种层，接着进行自动催化铜沉积。晶种层的材料的实例包括但不限于铜(Cu)、镍(Ni)、金(Au)、银(Ag)、钯(Pd)、铟(In)、镍钯金(NiPdAu)和镍金(NiAu)。可以通过任何合适的工艺形成晶种层。晶种层可以通过化学沉积、溅射或化学汽相沉积自身形成。
在用铜等填充之前，沟槽215和通孔209通常衬有阻止电迁移的阻挡物。阻挡层的材料的实例包括钌(Ru)、锰(Mn)、钴(Co)、铬(Cr)、氮化钛(TiN)、钛钨(TiW)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)和这些的组合。可以通过任何合适的工艺(诸如CVD沉积)来沉积阻挡层。
促进粘着的层可以包括在阻挡层里。界面层可以是自组装单层(SAM)。可以例如通过包括含有机化学物质的气体的热工艺处理形成自组装单层。可选地，仅在第一介电层207上形成自组装单层并作为通孔209的衬层，而不作为沟槽215的衬层。
步骤115完成图9所示的双镶嵌结构218的形成。双镶嵌结构218包括第一层，其包括位于第一介电层207区域中的金属217填充的通孔209；以及第二层，其包括位于牺牲层211区域中的金属217填充的沟槽215。后续加工用第二介电层221替换结构218中的牺牲材料层211。
步骤117为将衬底200的上表面平坦化。平坦化后的表面包括具有金属217镶嵌物的牺牲材料层211。通常通过化学机械抛光(CMP)来实现平坦化。由于CMP总是以至少略微变化的速率去除不同的材料，所以表面并不会变成完全平坦的。
步骤119为在金属217的暴露上表面上形成金属盖顶219的可选步骤，如图10中所示。盖顶219与盖顶203可以是相同的或者不同的，然而，关于盖顶203在组成、工艺和功能性方面的说明同样适用于盖顶209。
步骤121为去除牺牲层211。可以通过任何合适的工艺去除牺牲层211。取决于所用的材料，为便于去除牺牲层211对牺牲层211进行预处理是可能的和期望的。可以使用的预处理工艺的实例包括氧化、热处理以及UV辐射。去除工艺本身可以是例如湿法清洁或等离子体蚀刻。如图11所示，牺牲层211的去除使得沟槽215的金属217暴露出来。
步骤123为形成第二介电层221。第二介电层221填充先前被牺牲层211占据的空间并形成围绕沟槽215的金属217的区域。第二介电层221通常是超低k介电层。为了具有低介电常数，可以形成孔隙率为至少20％的第二介电层221。也可以形成具有气隙223的第二介电层221。第二介电层221可以是会被用于形成沟槽215、用金属217填充沟槽215或平坦化步骤117的工艺损伤的介电层。
为了获得2.1或更小的等效介电常数，第二介电层221的材料可以是如上所述的但具有孔隙率或气隙223的低k电介质。气隙可以使层的介电常数减小5％或更多，这是大幅度的减小。孔隙率也可大幅度地减小层的等效介电常数。可以引入孔隙率作为形成第二介电层221的工艺的一部分。例如，可以通过旋涂工艺或CVD工艺将OSG前体和致孔剂一起施加到衬底200来形成OSG介电层221。该工艺可以进一步包括致孔剂的可控蒸发。OSG前体的实例包括有机硅烷和有机硅氧烷。有机硅烷的实例包括甲基倍半硅氧烷(MSQ)和氢倍半硅氧烷(HSQ)。有机硅氧烷的实例包括属于甲基硅氧烷家族(诸如甲基二乙氧基硅烷)的聚合物。致孔剂的实例包括有机溶剂。有机溶剂可以是例如甲苯、庚烷、环己醇或它们的混合物。在诸如旋涂或CVD的介电层形成工艺之后，可以通过沉积后处理诸如热处理、UV处理或电子束处理来改善孔形成、机械强度或这两者。
也可以通过选择合适的形成工艺将气隙223引入第二介电层221中。形成具有气隙223的介电层221的合适工艺可以是非共形沉积工艺，诸如等离子体增强化学汽相沉积(PECVD)。非共形工艺在凹槽区域诸如图11标出的角部220中形成气隙223。示例性的非共形沉积工艺是等离子体增强CVD。孔隙率大于20％并具有气隙223的OSG层的等效介电常数可以为2.0或更小。
步骤125为另一平坦化步骤，通常也可以采用化学机械抛光(CMP)来实现。步骤125使第二介电层221的上表面、盖顶金属219的上表面或沟槽金属217的上表面(如果不存在盖顶219)平坦化。可选地，在平坦化之前，用保护性“填充”材料浸润第二介电层221的孔结构。可以在平坦化后去除填充材料。填充材料可以是例如单体碳氢化合物。可以通过载液诸如超临界二氧化碳将这种材料运送到介电层221的孔内。
图13示出具有通过工艺100形成的双镶嵌结构225的衬底200。双镶嵌结构225包括第一层，该第一层包括位于第一介电层207区域中的金属217填充的通孔209；以及第二层，该第二层包括位于第二介电层221区域中的金属217填充的沟槽215。双镶嵌结构225的一个特征是无蚀刻终止层。另一个特征是在第二介电层221中无蚀刻损伤。第一介电层207是孔隙率小于20％并且没有气隙的低k电介质。第一介电层207为结构225提供机械强度和稳定性。第二介电层221是孔隙率大于20％并包含气隙223的超低k电介质。第二介电层221为结构225提供低电容。
虽然仍生产如图13所示的双镶嵌结构225结构，但工艺100的步骤107、109、111和113的顺序可以不同于图1所示的顺序106。具体地，步骤107形成通孔209可以延至步骤109形成牺牲层211之后。
图14和图15示出两种可选的顺序300和400。在顺序300和400中，通孔蚀刻107延至步骤109形成牺牲层211之后。在这些顺序中，牺牲层211的材料没有填充通孔209并且在沟槽蚀刻113期间不从通孔209蚀刻。
在顺序300中，在沟槽蚀刻113之前实施通孔蚀刻107。顺序300中的沟槽蚀刻113包括蚀刻穿过牺牲层211，然后穿过第一介电层207。在工艺300中，期望包括可选步骤108塞住通孔209，以便提供用于在其上形成沟槽蚀刻掩模213的层表面。可以在沟槽蚀刻113期间或者在沟槽蚀刻113之后的单独步骤114中从通孔209去除插塞材料。在顺序400中，在通孔蚀刻107前实施沟槽蚀刻113。
工艺顺序106、300和400中的每一种相对于其它工艺顺序均具有优点。与顺序300和400相比，顺序106对通孔209的尺寸提供更好的控制。顺序300和400相对于顺序106的改进之处在于它们避免了直接在层207上形成通孔蚀刻掩模时可能发生的第一介电层207的可能污染。顺序300比顺序400更能容许沟槽和通孔掩模之间的不对准。另一方面，顺序106、顺序300相对于工艺400需要采用高纵横比来蚀刻通孔209。
就某些构思、元件和部件方面已经显示和/或描述了如通过以下权利要求描述的本发明。虽然本文中可能仅就一个或几个构思或实例或者以广义和狭义公开了特定元件或部件，广义或狭义构思中的元件或部件可以与广义或狭义构思中的一个或多个其它元件或部件相结合，其中本领域普通技术人员能够认识到这种组合是合乎逻辑的。而且，本说明书可以描述多于一个的发明，并且以下的权利要求并不必涵盖本文所述的每一个构思、方面、实施例或实例。

Claims (18)

1.一种形成双镶嵌铜互连结构的方法，包括：
在衬底上方沉积第一介电层；
在所述第一介电层上方沉积牺牲层；
蚀刻延伸穿过所述牺牲层但未穿过所述第一介电层的沟槽；
在前述两个步骤中的一个或两个之前或之后，蚀刻通孔穿过所述第一介电层；
沉积导电材料以填充所述沟槽和所述通孔并形成镶嵌结构，所述镶嵌结构包括位于第一层电介质区域中的导电材料填充的通孔和位于牺牲层材料区域中的导电材料填充的沟槽；
去除所述牺牲层；以及
沉积第二介电层以形成镶嵌结构，所述镶嵌结构包括位于所述第一层电介质区域中的铜填充的通孔和位于第二层电介质区域中的导电材料填充的沟槽，
其中所述第一层电介质的孔隙率小于20％，而所述第二层电介质的孔隙率大于20％。
2.根据权利要求1所述的方法，其中，在沉积所述牺牲层之前蚀刻所述通孔穿过所述第一介电层。
3.根据权利要求2所述的方法，其中：
沉积所述牺牲层用所述牺牲层的材料填充所述通孔；以及
在室中蚀刻所述沟槽并且在从该室取出衬底之前通过在该室中进一步蚀刻从所述通孔去除所述牺牲层材料。
4.根据权利要求2所述的方法，其中，所述通孔的位置由用作蚀刻所述通孔的掩模的光刻胶决定。
5.根据权利要求1所述的方法，其中，通过非共形沉积工艺沉积所述第二介电层，在所述第二介电层中留下气隙。
6.根据权利要求1所述的方法，其中，所述第一介电层的等效介电常数大于2.1且小于3.5，而所述第二介电层的等效介电常数小于2.1。
7.一种半导体器件制造工艺，包括：
提供半导体衬底；
通过前段工艺加工在所述衬底上形成栅极结构；
在所述栅极结构上方形成低k介电层；
图案化通孔穿过所述低k介电层；
在所述低k介电层上方形成牺牲层；
图案化沟槽穿过所述牺牲层；
用金属填充所述通孔和所述沟槽；
去除所述牺牲层；
在所述低k介电层上方形成超低k介电层；以及
其中所述超低k介电层比所述低k介电层具有更低的介电常数。
8.根据权利要求7所述的工艺，其中，通过非共形沉积工艺沉积所述超低k介电层。
9.根据权利要求7所述的工艺，其中，不使用硬掩模图案化所述通孔穿过所述低k介电层。
10.根据权利要求7所述的工艺，其中，所述低k介电层的等效介电常数大于2.1，而所述超低k介电层的等效介电常数小于2.1。
11.根据权利要求7所述的工艺，其中，所述低k介电层比所述超低k介电层具有更低的孔隙率。
12.根据权利要求7所述的工艺，其中，形成没有气隙的所述低k介电层，而形成具有气隙的所述超低k介电层。
13.根据权利要求7所述的工艺，其中，所述牺牲层包括非晶碳。
14.根据权利要求13所述的工艺，其中，所述低K介电层为第一介电层，所述第一介电层是有机硅酸盐玻璃。
15.根据权利要求14所述的工艺，其中，采用含有NH3或含有N2和H2组合的蚀刻气体通过等离子体蚀刻图案化所述沟槽。
16.根据权利要求7所述的工艺，其中，去除所述牺牲层包括采用相对于组成所述低k介电层的材料优先去除组成所述牺牲层的材料的蚀刻条件进行蚀刻。
17.一种包括双镶嵌金属互连结构的半导体器件，包括：
所述双镶嵌结构的第一层，包括位于第一电介质区域中的金属填充的通孔；以及
所述双镶嵌结构的第二层，包括位于第二电介质区域中的金属填充的沟槽；
其中所述双镶嵌结构的特征还在于在所述第一层和所述第二层之间无蚀刻终止层；以及
其中所述第二层包括气隙，所述气隙大幅减小该层的等效介电常数，而所述第一层不包括所述气隙，
其中，所述第一电介质的孔隙率小于20％，而所述第二电介质的孔隙率大于20％，并且所述第二电介质无蚀刻损伤。
18.根据权利要求17所述的器件，其中：
所述第一电介质的等效介电常数大于2.1且小于3.5；以及
所述第二电介质的等效介电常数小于2.1。
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