CN103390539B - The preparation method of thin silicon wafer - Google Patents
The preparation method of thin silicon wafer Download PDFInfo
- Publication number
- CN103390539B CN103390539B CN201210145549.0A CN201210145549A CN103390539B CN 103390539 B CN103390539 B CN 103390539B CN 201210145549 A CN201210145549 A CN 201210145549A CN 103390539 B CN103390539 B CN 103390539B
- Authority
- CN
- China
- Prior art keywords
- silicon
- silicon chip
- thickness
- back side
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention discloses the preparation method of a kind of thin silicon wafer, including step: 1) at the grown above silicon silicon nitride of conventional thickness or silicon oxynitride；2) at silicon chip back side resist coating, silicon chips periphery exposure, development, make photoresist only be retained in the periphery of silicon chip back side；3) at the local etching groove of the unglazed photoresist of silicon chip back side；4) in groove, conductive heat conducting material is filled；5) sealing one layer of insulant on conductive heat conducting material again, follow-up flow process traditionally completes the preparation of thin silicon wafer.The present invention, by silicon chip back side digging groove filler metal material or insulant, the big angularity problem brought after effectively reducing wafer thinning, makes the thickness of silicon chip be minimized 20～500 μm；It addition, the present invention is based on existing technique, existing production line can be made full use of, thus decrease equipment expense, reduce production cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to the preparation method of a kind of thin silicon wafer.
Background technology
The effective thickness of silicon on-chip circuit layer is generally 5～10 μm, and in order to ensure its function, it is necessary for having certain support thickness
, therefore, the thickness limit of silicon on-chip circuit layer is 20～30 μm.And 20～30 μm only account for a little portion of silicon chip gross thickness
Point, account for gross thickness about 90% is backing material, is to ensure that silicon chip has during manufacturing, testing and transport enough
Intensity.Therefore, after circuit layer completes, need silicon chip carries out thinning back side (backside thinning) so that it is
Reach required thickness, silicon chip is carried out scribing (Dicing) processing the most again, forms the most thinning bare chip.
Chip after thinning has the following advantages:
(1) thermal diffusion efficiency is improved.Along with semiconductor structure becomes increasingly complex, integrated level is more and more higher, and transistor volume is continuous
Reducing, heat radiation has been increasingly becoming the key factor affecting chip performance and life-span, and thin chip is more beneficial for heat radiation.
(2) chip package volume is reduced.Microelectronic product develops to compact direction day by day, reduces chip package volume and is
Adapt to the only way of this development trend.
(3) mechanical performance is improved.Chip mechanical performance after thinning significantly improves, and silicon chip is the thinnest, and its pliability is the best, by outward
The stress that power impact causes is the least.
(4) electric property is improved.The thickness of wafer is the thinnest, and the line between element will be the shortest, and element conductive resistance will be the lowest,
Signal delay time is the shortest, thus realizes higher performance.
(5) scribing processing capacity is alleviated.Cut again after thinning, processing capacity during scribing (Dicing) can be reduced, reduce core
Sheet collapses the incidence rate on limit.
At present, the thinning back side technology of silicon chip mainly have grinding, grind, chemically-mechanicapolish polish (CMP), dry type polishing (dry
Polishing), electrochemical corrosion (electro chemical etching), wet etching (wet etching), plasma
Assistant chemical corrosion (PACE), atmospheric plasma corrosion (atmospheric downstream plasma etching, ADPE)
Deng, the thinning back side technology of most common of which has grinding, CMP, wet etching, ADPE and dry type to polish five kinds.
CMP can be greatly enhanced the intensity of silicon chip, reduces warpage, and its shortcoming is need to protect the front of silicon chip, right
The calibration capability of grinding mark is weak, is not suitable for being machined with the silicon chip (bumped wafer) of projection, and corrosion rate is fast, and (clearance is
5～40mm/min) and uneven (for 5%～the 10% of etching extent), there is problem of environmental pollution.
Atmospheric plasma corrosion is that a kind of pure chemistry worked at atmosheric pressure that newly-developed gets up, that utilize Magnetic Control is made
Dry corrosion technology, under ar gas environment, carbon tetrafluoride gas is introduced ion plasma by ADP system, is allowed to 100% decomposition,
F (fluorine) generates SiF with the material generation chemical reaction of silicon chip surface4, reach to remove the purpose of material；Add man-hour, utilize
Silicon chip is suspended in above ion plasma by the pressure that Bernoulli effect produces, and the front of silicon chip needs like that not necessarily like wet corrosion
Protect with adhesive tape, therefore, be suitable for the silicon chip that processing is relatively thin, also be adapted for being machined with the silicon chip of projection.
ADPE can remove the damage layer that silicon chip back side causes due to grinding, and process velocity is 1～4mm/min, and back side removal amount can
Reaching 50～100 μm, the profile pattern after processing is better than wet corrosion.
Dry type polishing is the technology of emerging removal silicon chip stress, and its process principle is similar to silicon chip grinding, different from grinding it
The buff wheel that place's fiber and metal-oxide are made instead of skive.Dry type polishing can remove silicon chip back side effectively
The residual stress that grinding causes, low cost, but working (machining) efficiency is low, process velocity is only 1mm/min, is only suitable for removing shallower
Damage layer.
The original thickness of silicon chip is generally 675～775 μm, to be finally thinned to 100～200 μm, to be the most even thinned to
50μm.Silicon chip typically can not be ground in wafer thinning technique the thinnest size, because if silicon chip to be directly ground to core
Thickness needed for sheet encapsulation, due to the existence of mechanical damage layer, in transport and post-order process, fragment rate is the highest.Therefore, real
In the application of border, for the silicon chip of 200 μm, if needing the thin silicon wafer of 100 μm, the most first remove the biggest by the mode of grinding
Part surplus, about thinning back side to 180 μm, then by the one or two in CMP, wet etching, ADPE and dry type polishing
Plant and eliminate damage layer and the residual stress that grinding causes, obtain undamaged surface.
Summary of the invention
The technical problem to be solved in the present invention is to provide the preparation method of a kind of thin silicon wafer, it can avoid thinning after silicon chip occur
Big angularity problem, it is possible to reduce thickness and the production cost of silicon chip.
For solving above-mentioned technical problem, the thickness of the present invention is the preparation method of the thin silicon wafer of 20～500 μm, comprises the following steps:
1) at one layer of silicon nitride of the grown above silicon that thickness is 675～775 μm or silicon oxynitride；
2) coat a layer photoetching glue at silicon chip back side, then in silicon chips periphery exposure, development, make photoresist only be retained in the silicon chip back of the body
The periphery in face；
3) at the local etching groove of the unglazed photoresist of silicon chip back side, the degree of depth of groove is step 1) in silicon wafer thickness deduct described
The thickness of thin silicon wafer；
4) in groove, conductive heat conducting material is filled；
5) on described conductive heat conducting material, seal one layer of insulant again, then grow nitrogen oxides, complete the preparation of thin silicon wafer.
The present invention, by silicon chip back side digging groove filler metal material and insulant, brings after effectively reducing wafer thinning
Big angularity problem, makes the thickness of silicon chip be minimized 20～500 μm；It addition, the present invention is based on existing technique, can
To make full use of existing production line, thus decrease huge equipment expense, reduce the production cost of product.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the embodiment of the present invention.
Detailed description of the invention
More specifically understand for the technology contents of the present invention, feature are had with effect, in conjunction with embodiment illustrated, describe in detail such as
Under:
The preparation method of the thin silicon wafer of the present embodiment, comprises the following steps that:
Step 1, grows one layer of silicon nitride, such as Fig. 1 (a) institute in the front of the silicon chip that thickness is 725 μm, a diameter of 200mm
Show.
The type of silicon chip, in addition to above-mentioned size, it is also possible to use the various sizes silicon chip of existing industrial standard, such as 4 cun, 6
Very little, 8 cun, 12 cun etc..
The deposit of silicon nitride LPCVD (low-pressure chemical vapor deposition) technique forms, and its thickness is depending on oxide thickness to be etched
Depending on degree.
Step 2, is coated with last layer negative photoresist at silicon chip back side, then silicon chips periphery is exposed, develops, makes photoresist only protect
Stay the periphery of silicon chip back side, as shown in Fig. 1 (b).
The photoresist width retained is 1～5mm, and thickness is 10nm～100 μm.
Gluing board is TEL ACT-8.Exposure bench is Nikon I-14, and exposure energy is 20mj/cm2。
Step 3, at 60 DEG C, with the KOH aqueous solution of 30% (mass percent concentration), carries out wet in vibration temperature chamber
Method etching (can also use additive method etching silicon wafer substrate), etches a groove being slightly less than silicon chip at silicon chip back side, such as figure
Shown in 1 (c).
The degree of depth of groove deducts, equal to the thickness of the normal silicon chip in step 1, the silicon wafer thickness being actually needed, for example, it is desired to 100
The silicon chip of μ m thick, we are accomplished by etching the groove that 725-100=625 μm is deep.
Step 4, with dry method (other lithographic methods can also be used) etching silicon wafer substrate, further that etching groove is uniform and smooth,
As shown in Fig. 1 (d).
Dry etching uses plasma (plasma) lithographic method, and etching gas is SF4And O2Mixed gas.
Step 5, in the trench fill oxide (such as silicon dioxide) or other conductive heat conducting materials, as shown in Fig. 1 (e)；
Step 6, the implant in groove is sealed one layer of PMMA (polymethyl acrylate) or other insulant again, such as figure
Shown in 1 (f).
Step 7, follow-up flow process traditionally completes the preparation of thin silicon wafer.The thickness of the thus prepared thin silicon wafer obtained is permissible
As little as 20～500 μm, and the problem that there is not big angularity.
After the insulant such as the PMMA of silicon chip back side residual and oxide can grow nitrogen oxides below, do last weld pad
Remove before photolithography process.Oxide can use organic solvent (such as phenol, methyl phenyl ethers anisole, oxide) to remove, typically
Way is: with HF and H2O ratio is the hydrofluoric acid rinse (depending on the rinsing time thickness according to the oxide to float) of 1:10；
Overflow 5 minutes；Wash by water 10 times；Dry.
Claims (10)
1. the preparation method of thin silicon wafer, the thickness of described thin silicon wafer is 20～500 μm, it is characterised in that comprise the following steps:
1) at one layer of silicon nitride of the grown above silicon that thickness is 675～775 μm or silicon oxynitride；
2) coat a layer photoetching glue at silicon chip back side, then in silicon chips periphery exposure, development, make photoresist only be retained in the silicon chip back of the body
The periphery in face；
3) at the local etching groove of the unglazed photoresist of silicon chip back side, the degree of depth of groove is step 1) in silicon wafer thickness deduct described
The thickness of thin silicon wafer；
4) fill oxide or conductive heat conducting material in groove；
5) on described oxide or conductive heat conducting material, seal one layer of insulant again, then grow nitrogen oxides, complete thin silicon wafer
Preparation.
Method the most according to claim 1, it is characterised in that step 1), the thickness of described silicon chip is 725 μm, directly
Footpath is 200mm.
Method the most according to claim 1, it is characterised in that step 1), use low-pressure chemical vapor deposition process raw
Long silicon nitride or silicon oxynitride.
Method the most according to claim 1, it is characterised in that step 2), described photoresist is negative photoresist.
Method the most according to claim 1, it is characterised in that step 2), the width of the photoresist retained is 1～5mm,
Thickness is 10nm～100 μm.
Method the most according to claim 1, it is characterised in that step 3), first etch ditch with wet etching method
Groove, then etches uniform and smooth with dry etching method by described groove further.
Method the most according to claim 6, it is characterised in that step 3), described wet etching method is: at 60 DEG C
Under, it is the potassium hydroxide aqueous solution of 30% with mass percent concentration, performs etching in vibration temperature chamber.
Method the most according to claim 6, it is characterised in that step 3), described dry etching method is that plasma is carved
Erosion, etching gas is SF4And O2Mixed gas.
Method the most according to claim 1, it is characterised in that step 4) and step 5) in, described oxide is oxygen
SiClx.
Method the most according to claim 1, it is characterised in that step 5), described insulant is polymethyl acrylate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210145549.0A CN103390539B (en) | 2012-05-11 | 2012-05-11 | The preparation method of thin silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210145549.0A CN103390539B (en) | 2012-05-11 | 2012-05-11 | The preparation method of thin silicon wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103390539A CN103390539A (en) | 2013-11-13 |
| CN103390539B true CN103390539B (en) | 2016-08-17 |
Family
ID=49534774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210145549.0A Active CN103390539B (en) | 2012-05-11 | 2012-05-11 | The preparation method of thin silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103390539B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110526201B (en) * | 2018-05-25 | 2022-11-01 | 浙江清华柔性电子技术研究院 | Preparation method of flexible silicon wafer |
| CN110526202B (en) * | 2018-05-25 | 2022-11-01 | 浙江清华柔性电子技术研究院 | Preparation method of flexible silicon wafer |
| CN111180332B (en) * | 2020-01-03 | 2022-08-16 | 上海华虹宏力半导体制造有限公司 | Wafer back monitoring method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6162702A (en) * | 1999-06-17 | 2000-12-19 | Intersil Corporation | Self-supported ultra thin silicon wafer process |
| CN101350332A (en) * | 2007-07-20 | 2009-01-21 | 万国半导体股份有限公司 | Ultra thin wafers having an edge support ring and manufacture method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080242052A1 (en) * | 2007-03-30 | 2008-10-02 | Tao Feng | Method of forming ultra thin chips of power devices |
| US8084335B2 (en) * | 2008-07-11 | 2011-12-27 | Semiconductor Components Industries, Llc | Method of thinning a semiconductor wafer using a film frame |
-
2012
- 2012-05-11 CN CN201210145549.0A patent/CN103390539B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6162702A (en) * | 1999-06-17 | 2000-12-19 | Intersil Corporation | Self-supported ultra thin silicon wafer process |
| CN101350332A (en) * | 2007-07-20 | 2009-01-21 | 万国半导体股份有限公司 | Ultra thin wafers having an edge support ring and manufacture method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103390539A (en) | 2013-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101246822A (en) | Laser etching and trench digging method of semiconductor chip | |
| CN101399195A (en) | Thinning method for backing side of wafer | |
| CN103390539B (en) | The preparation method of thin silicon wafer | |
| CN104952794A (en) | Kerf preparation for backside metallization | |
| CN102737961A (en) | Method for reducing collapsing or shift of photoresist (PR) mask | |
| CN102243995B (en) | The integrated approach of different thickness grid oxygen in high-pressure process | |
| Asano et al. | A novel wafer dicing method using metal-assisted chemical etching | |
| CN104979271B (en) | The forming method of interconnection structure | |
| CN101452873B (en) | Shallow trench isolation process | |
| Zhou et al. | Integrated process for silicon wafer thinning | |
| WO2020214238A1 (en) | Method of thin film deposition in trenches | |
| CN105551940A (en) | Method of removing photoetching anti-reflective layer containing particle defects | |
| CN109216259A (en) | A kind of production method of memory | |
| CN103809241B (en) | A kind of method making optical fiber align pedestal array in silica-based technique | |
| CN102420124B (en) | Etching method of dielectric layer | |
| JP2013008753A (en) | Method for producing spherical photoelectric conversion element | |
| CN103624032B (en) | A kind of monolithic cleaning method of wafer | |
| CN103309151B (en) | Method for processing photoresist, and method of manufacturing semiconductor device | |
| CN106098869A (en) | A kind of substrate desquamation method of vertical structure LED | |
| CN103279015A (en) | Photoresist treatment method and preparation method of semiconductor devices | |
| Charavel et al. | Wafer bevel protection during deep reactive ion etching | |
| TWI855393B (en) | Method of manufacturing semiconductor devices | |
| CN104124150A (en) | Method for forming semiconductor device | |
| CN115020301A (en) | Method for applying small-size wafer to large-size wafer etching equipment | |
| CN110526202A (en) | The preparation method of flexible silicon wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140115 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140115 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |