CN103336239B

CN103336239B - The method of wafer sort

Info

Publication number: CN103336239B
Application number: CN201310217973.6A
Authority: CN
Inventors: 王善屹; 王磊
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-06-03
Filing date: 2013-06-03
Publication date: 2016-12-28
Anticipated expiration: 2033-06-03
Also published as: CN103336239A

Abstract

The present invention provides a kind of method of wafer sort, wafer to be tested is tested respectively by the method for this wafer sort along two mutually orthogonal directions, when wafer sort is affected by the factor of test own, the different test results on direction can present significantly distinguishes distribution, so, whether the yield distribution that directly can tell test result from test result is affected by the factor of test own, substantially increases production efficiency.

Description

The method of wafer sort

Technical field

The present invention relates to IC manufacturing field, a kind of method particularly relating to wafer sort.

Background technology

Wafer sort (Chip Probing, CP) is after wafer manufacture completes, and carries out each chip on wafer Electrically ability and the test of circuit function.Chip testing (die sort) or wafer electrical measurement (wafer are also in wafer sort Sort).

Wafer sort is for following purpose, it is possible, firstly, to before wafer is delivered to encapsulate factory, identify qualified core Sheet, underproof chip does not carry out follow-up encapsulation process, cost-effective.It addition, the electrical parameter of devices/circuits can be carried out Characteristic evaluation, engineer controls the quality level of technique by the distribution of these monitoring parameters.

When test, wafer is fixed on the chuck of pull of vacuum, and probe connects with each weld pad of chip simultaneously Touch.Curtage is inputted measured device by probe by tester, then tests the response for this input signal of this chip, Obtain unit for electrical property parameters.Quantity, order and the type of test are by computer program control.Existing chip on wafer is carried out The order of test is, along a direction, to test the chip on wafer one by one.As it is shown in figure 1, be existing to wafer On chip carry out the schematic diagram tested, the grid that wherein dotted line surrounds represents the chip on wafer, fills the grid table of shade Show labeled bad or that electrical property is the best chip.In actual production, wafer is often formed with breach (notch) 101 and is used for thick The position of alignment wafer, in the present example, breach 101 is towards right side after coarse alignment for wafer to be tested, and probe is from water Square the most line by line chip is tested in (path that in for example, Fig. 1, solid line marks), then by qualified chip with not Non-defective unit position on wafer is recorded with the form of wafer figure on computers.

In general, wafer production is to produce by batch by product category, and such as, same box wafer, through the most same Production process and technological parameter, chip yield thereon is also in similar distribution.But, the result sometimes tested can not be true The real distribution reflecting chip bad on wafer, due to reasons such as board calibration or test setting, test result can show All it is marked as bad for the chip on measurement direction of some region on this batch wafer or unit for electrical property parameters is the best (such as figure Dash area in 1).Therefore, engineer can not tell when in the face of such test result is that these chips are implicitly present in The problem that defect still causes due to test, thus can only increase by retesting or confirming by other means Process time, the most serious reduce production efficiency.

Summary of the invention

The present invention provides a kind of method of wafer sort, cannot directly tell bad test knot solving prior art Fruit is the problem owing to chip is the most defective or causes due to test.

For solving above-mentioned technical problem, the present invention provides a kind of method of wafer sort, enters the chip on wafer one by one Row test, the method for described wafer sort is treated test wafer respectively two mutually orthogonal directions and is tested.

Optionally, wafer to be tested is the more wafers of the like products of same batch, and described more wafers is divided into two Group, the direction that the carrying out of two groups of wafers is tested is mutually perpendicular to.

Optionally, the wafer of odd number sheet in described more wafers is tested in a first direction；To described many platelets Even slice wafer in circle is tested in the second direction vertical with first direction.

Optionally, wafer to be tested is single-wafer, and described single-wafer is divided into multiple region, adjacent region The direction carrying out testing is mutually perpendicular to.

Optionally, on wafer, wafer is divided into four regions, two adjacent regions to survey by orthogonal two strings The direction of examination is mutually perpendicular to.

Optionally, on wafer, wafer is divided into four regions by orthogonal two diameters, defines in the direction of the clock These four regions are first area, second area, the 3rd region, the 4th region, and wherein first area and the 3rd region are first Direction is tested, and second area and the 4th region are tested in second direction.

Optionally, definition notched wafer is first direction with the direction of the diameter at place, the wafer center of circle, defines wafer plane The interior direction vertical with first direction is second direction.

Compared with prior art, the method for the wafer sort that the present invention provides has the advantage that

Wafer to be tested is tested in orthogonal both direction by the method for described wafer sort, if brilliant When circle test is affected by the factor of test own, the different test results on direction can present significantly distinguishes distribution, So directly can tell whether this measurement is affected by the factor of test own by test result, it is thus possible to effectively Owing to the factor of test itself affects, the chip of labelling is bad in resolution, the most just decreases needs and retests or by other handss The situation that test result is confirmed by section, further, moreover it is possible to determine what the factor of tested person own affected by test result The concrete interval of wafer, is greatly improved efficiency.

Accompanying drawing explanation

Fig. 1 is the existing schematic diagram testing the chip on wafer；

The schematic diagram of the crystal round test approach that Fig. 2 A to Fig. 2 B is provided by the embodiment of the present invention one；

The schematic diagram of the crystal round test approach that Fig. 3 is provided by the embodiment of the present invention two.

Detailed description of the invention

The core concept of the present invention is, it is provided that a kind of method of wafer sort, and the method for this wafer sort is to be tested Wafer test respectively along two mutually orthogonal directions, when wafer sort is affected by the factor of test own, The different test results on direction can present significantly distinguishes distribution, as such, it is possible to directly tell from test result Whether the yield distribution of test result is affected by the factor of test own, substantially increases production efficiency.

Below in conjunction with schematic diagram, the method for the wafer sort of the present invention is described in more detail, which show this The preferred embodiment of invention, it should be appreciated that those skilled in the art can revise invention described herein, and still realizes this The advantageous effects of invention.Therefore, it is widely known that description below is appreciated that for those skilled in the art, and does not make For limitation of the present invention.

Referring to the drawings the present invention the most more particularly described below in the following passage.Want according to following explanation and right Book, advantages and features of the invention is asked to will be apparent from.It should be noted that, accompanying drawing all uses the form simplified very much and all uses non- Ratio accurately, only in order to facilitate, to aid in illustrating lucidly the purpose of the embodiment of the present invention.

Embodiment one

Wafer to be tested is that the box in the production of the more wafers of the like products for same batch, e.g. standard is brilliant Circle (25), is divided into two groups by described more wafers, and the direction that the carrying out of these two groups of wafers is tested is mutually perpendicular to.If there is survey The impact of the own factor of examination, then carry out presenting significantly difference on the wafer tested at different directions, directly divide with this Discern the problem that this time tests whether to there is test itself.

Preferably, it is divided into two groups by odd number sheet and even slice, the wafer of odd number sheet is tested in a first direction；Right Even slice wafer in described more wafers is tested in the second direction vertical with first direction.Preferably, with reference to figure 2A to Fig. 2 B, definition notched wafer is first direction with the direction (horizontal direction in figure) of the diameter at place, the wafer center of circle, definition In wafer plane, the direction (in figure vertical direction) vertical with first direction is second direction.It is to say, the 1st of this batch the Wafer carries out test (as shown in Figure 2 A) the most line by line, the 2nd wafer in the vertical direction pair in the horizontal direction to chip Chip carries out test (as shown in Figure 2 B) the most by column, and chip is carried out the most line by line by the 3rd wafer in the horizontal direction Test ... the rest may be inferred.

If the odd even sheet number that test result presses wafer is the spaced apart of rule, such as, all show as on odd number sheet Horizontal direction upper part region chip is marked as bad or unit for electrical property parameters is the best (dash area in Fig. 2 A), at even number platelet All show as in the vertical direction subregion chip on circle and be marked as bad or unit for electrical property parameters is the best (shadow part in Fig. 2 B Point), or on even slice, corresponding region chipless are labeled as bad in the horizontal direction or unit for electrical property parameters is the best.Then May determine that this test is affected by the factor of test itself, the problem etc. set such as detection calibration or parameter.Further , if by the odd even sheet number of wafer be the phenomenon spaced apart of rule certain wafer from this batch wafer start occur or Terminate, the concrete interval of the wafer of determination tested person factor impact that can be concrete own.

If the rule of odd number sheet or even slice, example are not pressed in test result distribution of defective region on this batch wafer No matter as odd number sheet or even slice are all labeled as bad at the chip in region in the horizontal direction, then can get rid of is due to test The impact of factor.

Embodiment two

In the present embodiment, wafer to be tested is single-wafer, to the zones of different in this this wafer two phases The most vertical direction is treated test wafer respectively and is tested, and can be picked out the yield distribution of test result by test result Whether affected by test problem.

Concrete, in the present embodiment, wafer is divided into four regions by two strings orthogonal on it by wafer, adjacent The direction that two regions carry out testing is mutually perpendicular to.Preferably, utilize on wafer orthogonal two diameters by wafer decile It is four regions, in the present embodiment, chooses a wherein a diameter of diameter through notched wafer, as shown in Figure 3.By clockwise It is first area 311, region 314, second area the 312, the 3rd region the 313, the 4th that direction defines these four regions；Definition wafer Breach is first direction with the direction of the diameter at place, the wafer center of circle, and in definition wafer plane, the direction vertical with first direction is Second direction, wherein first area 311 and the 3rd region 313 are tested in a first direction, second area 312 and the 4th region 314 test in second direction.It is identical with the principle in embodiment one, if the yield in these four regions is distributed along with test The difference in direction occurs the change of rule in different regions, such as, edge occur in first area 311 and the 3rd region 313 The bad chip distribution of first direction, occurs that in second area 312 and the 4th region 314 bad chip in a second direction divides Cloth, as shown in Figure 3, then can conclude that this test exist the chip caused due to the reason of test own be marked as bad because of Element；If the yield in these four regions is distributed not with measurement direction difference generation significant change, such as, appearance edge, first area The distribution of the bad chip of first direction, the bad chip of second area still for be distributed in the first direction, then may determine that and is not The chip caused due to the reason of test own is marked as bad.

In another embodiment of the invention the method for testing to single-wafer in embodiment two is attached to embodiment In one, the test mode during every wafer is all carried out such as embodiment two, and make the measurement direction of the same area of adjacent wafers It is mutually perpendicular to, equally the more wafers of same batch is tested.

In sum, the present invention provides a kind of method of wafer sort, and the method is right in orthogonal both direction Wafer to be tested is tested, it is thus possible to effective resolution is owing to the factor of test itself affects, the chip of labelling is bad, And from test result, directly tell whether test result is affected by the factor of test own, the most just decrease needs again Test or situation about confirming test result by other means, substantially increase efficiency.

Obviously, those skilled in the art can carry out various change and the modification essence without deviating from the present invention to the present invention God and scope.So, if these amendments of the present invention and modification belong to the scope of the claims in the present invention and equivalent technologies thereof Within, then the present invention is also intended to comprise these change and modification.

Claims

1. a method for wafer sort, tests one by one to the chip on wafer, it is characterised in that described wafer sort Method is treated test wafer respectively two mutually orthogonal directions and is tested；Described wafer to be tested is identical with batch The more wafers of product, is divided into two groups by described more wafers, and the direction that the carrying out of two groups of wafers is tested is mutually perpendicular to.

2. the method for wafer sort as claimed in claim 1, it is characterised in that to the crystalline substance of odd number sheet in described more wafers Circle is tested in a first direction；To the even slice wafer in described more wafers in the second direction vertical with first direction Test.

3. the method for wafer sort as claimed in claim 2, it is characterised in that definition notched wafer and place, the wafer center of circle The direction of diameter is first direction, and in definition wafer plane, the direction vertical with first direction is second direction.