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CN103329263A - 用于缩减多重堆栈的整体封装尺寸的针脚凸块堆栈设计 - Google Patents

用于缩减多重堆栈的整体封装尺寸的针脚凸块堆栈设计 Download PDF

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Publication number
CN103329263A
CN103329263A CN2011800490077A CN201180049007A CN103329263A CN 103329263 A CN103329263 A CN 103329263A CN 2011800490077 A CN2011800490077 A CN 2011800490077A CN 201180049007 A CN201180049007 A CN 201180049007A CN 103329263 A CN103329263 A CN 103329263A
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China
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crystal grain
stitch
solder joint
distribution
engaged
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CN2011800490077A
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CN103329263B (zh
Inventor
赖玉清
F·Y·何
W·K·南
K·E·龙
S·冯
关凯澄
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Infineon Technology Co ltd
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Spansion LLC
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Abstract

本发明揭示一种用于堆栈晶粒的方法。在一实施例中，形成覆在衬底上的第一晶粒。第一配线接合至该第一晶粒以及至该衬底的指状焊片，其中，该第一配线用第一焊点接合至该指状焊片。形成覆在该第一针脚焊点上的第一针脚凸块，其中，该第一针脚凸块是由导电材料的一熔球形成。形成覆在该第一晶粒上的第二晶粒。第二配线接合至该第二晶粒以及至该第一针脚凸块，其中，该第二配线用第二焊点接合至该第一针脚凸块。

Description

用于缩减多重堆栈的整体封装尺寸的针脚凸块堆栈设计
技术领域
本揭示内容大体涉及半导体的制造领域，且更特别的是，涉及最小化具有堆栈晶粒(stacked die)配置的半导体的领域。
背景技术
现今半导体工业的趋势是生产有越来越多性能的半导体组件，同时减少组件的大小及半导体封装件的总高度。堆栈晶粒配置为实现半导体装置密度提高的常用方法。在实现更小封装件尺寸以及使封装件高度更薄的需求为持续驱动因素下，人们在寻求新的晶粒堆栈方法。
图1为多个堆栈晶粒的横截面图。如图1所示，多个集成电路(IC)芯片(也就是，晶粒)120以堆栈晶粒配置配置于衬底110上。在此实施例中，该堆栈晶粒配置由4个晶粒120组成。不过，可使用其它数量的晶粒。介于晶粒120之间的是晶粒间隔物(die spacer)124。晶粒间隔物124在两个晶粒120之间提供必要的空间以防上面的晶粒120接触、短路或损坏下面的接合线130。在一实施例中，晶粒间隔物124为硅间隔物。晶粒120及晶粒间隔物124用粘着层(adhesive layer)122相互粘贴。下晶粒120用粘着层122粘贴至衬底120。在制造工艺期间，每个晶粒120或间隔物124的底面可用粘着片黏合，一般是在晶圆层级。在其它实施例中，粘着层122可为在粘贴时施加的环氧树脂或液状膏。然后，固化(例如，烘烤)粘着层122以完成晶粒粘贴。
图2为图1中的部分D的俯视图。每个晶粒120用在焊线工艺期间形成的配线电性连接至衬底110(例如，印刷电路板或其它电子系统)。如图1及图2所示，焊线工艺使每个晶粒120上连接于焊垫132(未图示)之间的接合线(bond wire)130接附至在衬底110上的指状焊片(bond finger)136上的接触点134。图2以俯视图图示图1的部分D，包含：有多个接触点134及附着接合线130的指状焊片136。焊线工艺是以形成第一焊点于晶粒上开始。此第一焊点的形成是通过熔化接合线130的末端以在焊垫132上形成熔球(molten ball)138。在使接合线130接附至晶粒以及提供有足够松弛量的接合线130后，该焊线工艺通过把接合线130压在接触点134上以形成鱼尾状针脚焊点(stitchbond)140来结束。如图2所示，在多个堆栈晶粒下，施加至每个指状焊片136的多个针脚焊点140需要多个线内接触点134。进一步如图3所示，也可有在每个晶粒120上的多个焊垫132以及对应多个指状焊片136。
在焊线工艺期间，焊线机用超音波、热音波或热压接合法将接合线130焊接于焊垫132、接触点134之间。如图1、图2及图3所示，每个晶粒120有至少一接合线130由焊垫132延伸至接触点134。每条接合线130有它自己的对应焊垫132及接触点134。不过，如图2所示，随着晶粒堆栈增加(例如，4个晶粒)，指状焊片长度也必须增加以容纳在附加接触点134连接至同一指状焊片136的附加接合线。为了防止在焊线工艺期间损坏已布设接合线130，需要在接触点134之间提供最小空间，而加剧总指状焊片的长度要求。例如，在示范单一接点指状焊片长度可为0.20毫米时，如图2所示，示范四个焊点(线内)需要0.56毫米。因此，即使以增加晶粒堆栈的层数来增加半导体装置的密度，然而这会造成指状焊片长度增加而需要增加半导体装置封装件的尺寸。
发明内容
对于以堆栈晶粒配置的半导体装置与生俱来的挑战，本发明提供解决方案。在本发明的实施例的一方法中，揭示一种用于堆栈晶粒的方法。安置覆在一衬底上的第一晶粒。第一配线接合至该第一晶粒以及至该衬底的一指状焊片，其中，该第一配线用第一针脚焊点接合至该指状焊片。形成覆在该第一针脚焊点上的第一针脚凸块。安置覆在该第一晶粒上的第二晶粒。第二配线接合至该第二晶粒以及至该第一针脚凸块，其中，该第二配线用第二针脚焊点接合至该第一针脚凸块，其中，该第二配线覆在该第一针脚凸块上。最后，形成覆在该第二针脚焊点上的第二针脚凸块。在本发明的另一实施例中，揭示一种半导体装置。该半导体包含一衬底与覆在该衬底上的多个晶粒，其中，所述多个晶粒呈堆栈配置。该半导体进一步包含多条接合线，其中，每条接合线接附至所述多个晶粒中的一个以及至该衬底的一指状焊片。多条接合线接附至该指状焊片，其中，所述多个接合线的每条接合用一针脚焊点线接附至该指状焊片。最后，所述多个针脚焊点在每一对针脚焊点之间有一针脚凸块下处于堆栈配置。
附图说明
阅读以结合附图的详细说明，将更加了解本发明，图中类似的组件用相同的组件符号表示，且其中：
图1根据现有技术示意图示展现指状焊片长度增加的半导体装置的横截面图；
图2为进一步图示指状焊片长度增加的图1的一部分的俯视图；
图3为进一步图示多个指状焊片的立体(3D)视图；
图4A根据本发明的一实施例示意图示半导体装置的横截面图；
图4B根据本发明的一实施例示意图示半导体装置的一部分的横截面图；
图5根据本发明的一实施例的半导体装置的立体视图；
图6根据本发明的一实施例示意图示半导体装置的横截面图；
图7根据本发明的一实施例示意图示方法的步骤的流程图；
图8A至图8D根据本发明的一实施例示意图示半导体装置的横截面图；
图9根据本发明的一实施例示意图示方法的步骤的流程图；以及
图10A至图10D根据本发明的一实施例示意图示半导体装置的横截面图。
具体实施方式
此时将详细参考实施例图示于附图的本发明的较佳实施例。尽管用所述较佳实施例来描述本发明，然而应了解，不是要把本发明限制于所述实施例。反而是，希望本发明可涵盖落在由随附权利要求书定义的本发明精神及范畴内的替代、修改及等价陈述。此外，在以下本发明实施例的详细说明中，提出许多特定细节供彻底了解本发明。不过，本技艺一般技术人员会明白，在没有所述特定细节下仍可实施本发明。在其它情况下，不详述众所周知的方法、组件及电路以免不必要地混淆本发明实施例的方面。图示本发明实施例的附图为半图解说明以及为了说明清楚而不按比例绘制而且在附图中以夸大方式图示，特别是，有些尺寸。同样，尽管为了便于描述而以大体相同的方位图示附图，然而大部分的部件在附图中是以任意方式描绘。本发明大体可在任何方位下操作。
符号和术语：
以下详细说明的某些部分以程序、步骤、逻辑块、处理、及操作在电脑存储器中的数据位的其它符号表示来呈现。这些说明及表示为熟谙此艺者通常用于资料处理领域的手段，以有效地将工作内容传达给其它熟谙此艺者。于此，程序、电脑执行步骤、逻辑块、处理等通常视为导致所需结果的自相一致顺序的步骤或指令。这些步骤包含物理量的物理操控。通常但非必要，这些数量采用电或磁的讯号形式，而能被储存、转移、组合、比较、或在电脑系统中用其它方式操纵。已证明在方便时，主要是一般使用原因，将这些讯号表示为位、值、组件、符号、字母、术语、数字、或类似者。
不过，应记住，所有所述及类似术语是要与适当的物理量关连而且只是应用于所述数量的便利标签。显然由以下描述可明白，除非另有说明，应了解在本发明中，使用术语(例如，“处理”或“存取”或“执行”或“储存”或“呈现”或其类似者)的说明是指电脑系统(例如，图1的多节点电脑系统10)或类似电子计算装置的动作及处理，其是操纵以及把在电脑系统的暂存器及存储器或其它电脑可读取媒体内代表物理(电子)数量的数据转换成在电脑系统存储器或暂存器或其它信息储存、传输或显示装置内同样代表物理量的其它数据。当组件出现于数个实施例时，使用相同组件符号的意思是该组件与原始实施例所示的组件相同。
对于以堆栈晶粒配置的半导体装置的固有日增挑战，本发明提供解决方案。本揭示内容的各种实施例通过形成堆栈式鱼尾状针脚焊点来减少指状物长度。如以下所详述的，在来自第一晶粒的第一配线针脚接合至指状焊片后，形成由导电材料构成覆在第一针脚焊点上的熔球，在此被称为第一针脚凸块。之后，来自堆栈于第一晶粒上面的第二晶粒的第二配线可针脚接合至第一针脚凸块以形成覆在第一针脚凸块上的第二针脚焊点，接着是在第二针脚焊点上形成第二针脚凸块，等等。
图4A根据本发明的一实施例图示多个堆栈晶粒的横截面图。如图4A所示，多个集成电路(IC)芯片(也就是，晶粒)120在衬底110上以堆栈晶粒配置排列。在此实施例中，该堆栈晶粒配置包含4个晶粒120。不过，可使用有其它数量的晶粒。介于晶粒120之间的是晶粒间隔物124。晶粒间隔物在两个晶粒之间提供必要的空间以防上面的晶粒接触、短路或损坏下面的接合线。在一实施例中，晶粒间隔物124均为硅间隔物。晶粒120及晶粒间隔物124用粘着层122相互粘贴。下晶粒120用粘着层122粘贴至衬底120。每个晶粒120的底面或间隔物124在制造工艺期间可用粘着片黏合，这常在晶圆层级。在其它实施例中，粘着层122可为环氧树脂或液状膏。如图4A所示，每个晶粒120及间隔物124将会有黏着它的粘着层122。然后，固化(例如，烘烤)粘着层122以完成晶粒粘贴。
每个晶粒120用在焊线工艺期间形成的配线传输地(communicatively)耦合至衬底110(例如，印刷电路板或其它电子系统)。在焊线工作站使用超音波、热音波或热压接合法的焊线工艺开始是通过熔化接合线130末端来形成熔球138于焊垫132(未图示)上。一旦接合线130接附至晶粒120，该机构将会上升离开焊垫，以及在形成预定的松弛量后，会使配线130下降到指状焊片136。该工艺以冲压配线130于接触点134上继续，以形成扁平的鱼尾状针脚焊点140。如图5所示，每个晶粒120上也可以有多个焊垫132以及衬底110上有对应多个指状焊片136，使得多条接合线130耦合至每个指状焊片136。
不过，如以下所详述的，图4A及图4B图示多个针脚焊点140只需要单一接触点134的堆栈晶粒实施例，而不是，如图1所要求的，多个针脚焊点140在每个指状焊片136上需要多个接触点134。每个晶粒120有由焊垫132延伸至接触点134的至少一接合线130。不过，在本发明的一实施例中，多条接合线130及彼等的对应连接针脚焊点140是堆栈于单一接触点134上面，而不是每条接合线130有自己的对应焊垫132及接触点134。如以下所述，通过使导电材料的熔球介于各个针脚焊点140之间，使得以此方式堆栈针脚焊点140变成有可能。导电材料的熔球是由加热导电配线的末端形成。熔球在此被称为针脚凸块402。
因此，如图4A及图4B所示，在第一接合线130针脚接合140至指状焊片136的接触点134后，形成覆在第一针脚焊点140上的第一针脚凸块402。第一针脚凸块402用与在接触垫132上形成熔球138的相同工艺形成，除了切断配线而只留下熔球以形成针脚凸块402以外。在第一针脚凸块402形成后，第二接合线130针脚接合140至第一针脚凸块402的正面以覆在第一针脚凸块402上。之后，在第二针脚焊点140上形成第三针脚凸块402以及继续该工艺。与图2所示可观察到对应指状焊片长度随着晶粒堆栈增加而增加的实施例不同的是，指状焊片长度保持不变而与接合线针脚接合至指状焊片136的数目无关。换句话说，不论有一个晶粒还是4个晶粒的堆栈，指状焊片长度可保持在0.20毫米。因此，即使在增加晶粒的堆栈层数使半导体装置的密度增加时，不变的指状焊片长度更有助于减少半导体装置封装尺寸及增加密度。
图6根据本发明的另一实施例图示多个堆栈晶粒的横截面图。图6与图4相同，除了间隔物124及粘着层122换成膜覆线(film over wire；簡稱F.O.W.)层624以外。在一示范实施例中，FOW层624由有机粘着剂形成。FOW层624也可预先黏合于晶粒120上。在安置有黏合FOW层的晶粒之前，将会加热该FOW层以使它软化。如图6所示，在将软化的FOW层624放在晶粒120上时，接附至晶粒120的接合线130在软化的FOW层624放在下晶粒120的上表面上时有一部分沉入软化的FOW层624。这导致接合线130有一部分630以及接附焊点138嵌入覆在晶粒120上的FOW层624。在间隔物124以FOW层624代替时，也可移除晶粒120的粘着层122，除了第一晶粒120仍有粘着层112用来使第一晶粒120接附至衬底110以外。使用允许排除间隔物124及粘着层122的FOW层624，将会通过减少整体封装件高度来进一步改善半导体装置的密度。
图7的步骤图示用于使多个晶粒120以其多条接合线130接附至衬底110的一工艺。图8A至图8D进一步图示该制造工艺的阶段以及提供图7中的步骤的额外细节。
在图7的步骤702中，粘贴第一晶粒，然后形成第一焊线。步骤702进一步图示于图8A，在此接附第一晶粒120于衬底110。第一晶粒120用粘着层122接附至衬底110。如上述，粘着层122在晶圆层级的上一个步骤可粘合至晶粒120或在粘贴时粘贴至晶粒120或者是底下表面。在使第一晶粒120接附至衬底110后，多条接合线130各自接合至第一晶粒120的焊垫132以及至衬底110上的指状焊片136的对应接触点134。接合线130可由任何适当导电材料(例如，铜、银及金)形成。图8A图示接合于第一晶粒120、衬底110之间的两条接合线130；不过，可使用任意多条接合线。换句话说，在每个晶粒120上，可有用于接附接合线130的一或更多焊垫。每条接合线130用习称“第一焊点”的熔球138接合至第一晶粒120以及用习称“第二焊点”的针脚焊点140接合至接触点134。换句话说，每条接合线用第一及第二焊点接合至一晶粒及一指状焊片。
在图7的步骤704中，形成第一针脚凸块。步骤704进一步图示于图8B，在此形成覆在第一针脚焊点140上的第一针脚凸块402。如上述，第一针脚凸块402用与在焊垫132上形成熔球138(也就是，“第一焊点”)的相同工艺形成。不过，在通过熔化配线的一部分来形成熔球后，配线由新摆上的熔球切断以形成第一针脚凸块402。
在图7的步骤706中，粘贴第二晶粒，然后形成第二焊线。步骤706进一步图示于图8C，在此将膜覆线(FOW)层624及第二晶粒120安置成覆在第一晶粒120上。FOW层624可在个别步骤施加至第一晶粒120或预先施加至第二晶粒120的底面藉此同时施加第二晶粒120及附上的FOW层624。在接附第二晶粒120及FOW层624于第一晶粒120后，第二多条接合线130各自接合至第二晶粒120的焊垫132以及至对应第一针脚凸块402的正面，藉此形成覆在第一针脚凸块402上的第二针脚焊点140。每条接合线130用熔球138接合至第二晶粒120上的焊垫132以及用第二针脚焊点140接合至第一针脚凸块402，使得第二针脚焊点140覆在第一针脚凸块402上。图8C进一步图示接合于第二晶粒120、衬底110之间的两条接合线130；不过，可使用任意多条接合线。换句话说，在每个晶粒120上，可有用于接附接合线130的一或更多焊垫。
在图7的步骤708中，形成第二针脚凸块。步骤708进一步图示于图8D，在此在形成于步骤706的每个第二针脚焊点140上形成第二针脚凸块402，使得每个第二针脚凸块402覆在第二针脚焊点140上。如图8B所示及以上所述，第二针脚凸块402也用与在焊垫132上形成熔球138的相同工艺形成。在通过熔化配线的一部分来形成熔球后，配线由新摆上的熔球切断以形成第二针脚凸块402。可重复该工艺用于接附附加晶粒120及彼等的对应接合线130。
图9的步骤图示用于使多个晶粒120以其多条接合线130接附至衬底110的另一工艺。图示于图9的工艺的步骤优先于图示于图7的工艺的步骤。如以下所详述的，通过在放置下一个晶粒后只放置每个针脚凸块，实现更强健的工艺。由于直到放置下一个晶粒之后才放置针脚凸块，针脚凸块堆栈在制造工艺期间损坏有较低的风险。
图10A至图10D进一步图示该制造工艺的阶段以及提供图9中的步骤的额外细节。在图9的步骤902中，粘贴第一晶粒，然后形成第一焊线。步骤902进一步图示于图10A，在此接附第一晶粒120于衬底110。第一晶粒120用粘着层122接附至衬底110。如上述，粘着层122在晶圆层级的上一个步骤可粘合至晶粒120或在粘贴时粘贴至晶粒120或者是底下表面。在接附第一晶粒120于衬底110后，多条接合线130各自接合至第一晶粒120的焊垫132以及至衬底110上的指状焊片136的对应接触点134。接合线130可由任何适当导电材料(例如，铜、银及金)形成。图10A图示接合于第一晶粒120、衬底110之间的两条接合线130；不过，可使用任意多条接合线。换句话说，在每个晶粒120上，可有用于接附接合线130的一或更多焊垫。每条接合线130用习称“第一焊点”的熔球138接合至第一晶粒120，以及用习称“第二焊点”的针脚焊点140接合至接触点134。换句话说，每条接合线用第一及第二焊点接合至一晶粒及一指状焊片。
在图9的步骤904中，粘贴第二晶粒，然后形成第一针脚凸块。步骤904进一步图示于图10B，在此将第一膜覆线(FOW)层624及第二晶粒120放在第一晶粒120上。第一FOW层624可在个别步骤施加至第一晶粒120或可预先施加至第二晶粒120藉此同时施加第二晶粒120及附上的FOW层624。在接附第二晶粒120及第一FOW层624于第一晶粒120后，形成第一针脚凸块402于第一针脚焊点140上。如上述，第一针脚凸块402用与在焊垫132上形成熔球138的相同工艺形成。不过，在通过熔化配线的一部分来形成熔球后，配线由新摆上的熔球切断以形成第一针脚凸块402。
图9的步骤906中，形成第二焊线。步骤906进一步图示于图10C，在此第二多条接合线130各自接合至第二晶粒120的焊垫132以及至对应第一针脚凸块402的正面，藉此形成覆在第一针脚凸块402上的第二针脚焊点140。每条接合线130用熔球138接合至第二晶粒120上的焊垫132以及用第二针脚焊点140接合至第一针脚凸块402。图10C图示接合于第二晶粒120、衬底110之间的两条接合线130；不过，可使用任意多条接合线。换句话说，在每个晶粒120上，可有用于接附接合线130的一或更多焊垫。
在图9的步骤908中，粘贴第三晶粒，然后形成第二针脚凸块。步骤908进一步图示于图10D，在此将第二膜覆线(FOW)层624及第三晶粒120放在第二晶粒120上。第二FOW层624可在个别步骤施加至第二晶粒120或预先施加至第三晶粒120藉此同时施加第三晶粒120及附上的FOW层624。在接附第三晶粒120及第二FOW层624于第二晶粒120后，形成第二针脚凸块402于已形成于第一针脚凸块402之上的第二针脚焊点140上。如上述，第二针脚凸块402也用与在焊垫132上形成熔球138的相同工艺形成。在通过熔化配线的一部分来形成熔球后，配线由新摆上的熔球切断以形成第二针脚凸块402。然后，可重复该工艺用于接附对应接合线130至第三晶粒120及衬底，以及接附附加晶粒120及彼等的对应接合线130。
尽管本文已揭示一些较佳实施例及方法，显然受益于前述揭示内容的熟谙此艺者仍可做出所述实施例及方法的变更及修改而不脱离本发明的精神与范畴。希望本发明只限于随附权利要求书及适用法律的规定及原则所要求的程度。

Claims (20)

1.一种用于堆栈晶粒的方法，包含下列步骤：
使第一晶粒覆在一衬底上；
使第一配线接合至该第一晶粒以及至该衬底的一指状焊片，其中，该第一配线用第一焊点接合至该指状焊片；
形成覆在该第一焊点上的第一针脚凸块，其中，该第一针脚凸块是由导电材料的一熔球形成；
使第二晶粒覆在该第一晶粒上；以及
使第二配线接合至该第二晶粒以及至该第一针脚凸块，其中，该第二配线用第二焊点接合至该第一针脚凸块，其中，该第二焊点覆在该第一针脚凸块上。
2.根据权利要求1所述的方法，进一步包括以下步骤：在安置第二晶粒的该步骤之前，使一晶粒间隔物覆在该第一晶粒上，其中，该晶粒间隔物位在该第一晶粒与该第二晶粒之间。
3.根据权利要求2所述的方法，其中，该第一晶粒、该晶粒间隔物及该第二晶粒的底面用一粘着层黏合。
4.根据权利要求1所述的方法，进一步包括以下步骤：在安置第二晶粒的该步骤之前，使一膜覆线FOW层覆在该第一晶粒上，其中，该FOW位在该第一晶粒与该第二晶粒之间。
5.根据权利要求4所述的方法，其中，该第一晶粒的底面用一粘着层黏合。
6.根据权利要求1所述的方法，其中，该第一焊点及该第二焊点为针脚焊点，以及其中，针脚焊点有鱼尾形状。
7.根据权利要求1所述的方法，其中，该第一配线及该第二配线是通过形成导电材料的熔球而各自接合至该第一晶粒及该第二晶粒。
8.一种用于堆栈晶粒的方法，包含下列步骤：
使第一晶粒覆在一衬底上；
使第一配线接合至该第一晶粒以及至该衬底的一指状焊片，其中，该第一配线用第一焊点接合至该指状焊片；
使第二晶粒覆在该第一晶粒上；
形成覆在该第一焊点上的第一针脚凸块，其中，该第一针脚凸块是由导电材料的一熔球形成；以及
使第二配线接合至该第二晶粒以及至该第一针脚凸块，其中，该第二配线用第二焊点接合至该第一针脚凸块，其中，该第二焊点覆在该第一针脚凸块上。
9.根据权利要求8所述的方法，进一步包括：
在安置第二晶粒的该步骤之前，使一晶粒间隔物覆在该第一晶粒上，其中，该晶粒间隔物位在该第一晶粒与该第二晶粒之间。
10.根据权利要求9所述的方法，其中，该第一晶粒、晶粒间隔物及第二晶粒的底面用一粘着层黏合。
11.根据权利要求8所述的方法，进一步包括：
在安置该第二晶粒的该步骤之前，使一膜覆线FOW层覆在该第一晶粒上，其中，该第一FOW位在该第一晶粒与该第二晶粒之间。
12.根据权利要求11所述的方法，其中，该第一晶粒的底面用一粘着层粘合。
13.根据权利要求8所述的方法，其中，该第一焊点及该第二焊点为针脚焊点，以及其中，针脚焊点有鱼尾形状。
14.根据权利要求8所述的方法，其中，该第一配线及该第二配线是通过形成导电材料的熔球而各自接合至该第一晶粒及该第二晶粒。
15.一种半导体装置，包含：
一衬底；
覆在该衬底上的多个晶粒，其中，所述多个晶粒呈堆栈配置；
多条接合线，其中，每条接合线接附至所述多个晶粒中的一个以及至该衬底的一指状焊片，其中，多条接合线接附至该指状焊片，其中，所述多个接合线中的每一接合线用一焊点接附至该指状焊片，以及其中，所述多个焊点与在每一对焊点之间的一针脚凸块呈堆栈配置，其中，一针脚凸块是由导电材料的一熔球形成。
16.根据权利要求15所述的半导体装置，其中，所述多个晶粒由两个晶粒构成，以及其中，所述多个焊点由有一针脚凸块在第一及第二焊点之间的两个焊点构成。
17.根据权利要求16所述的半导体装置，进一步包括：
在第一及第二晶粒之间的第一晶粒间隔物。
18.根据权利要求17所述的半导体装置，其中，该第一及该第二晶粒及该晶粒间隔物的底面用一粘着层黏合。
19.根据权利要求16所述的半导体装置，进一步包括：
在第一及第二晶粒之间的一膜覆线FOW层，其中，接附至该第一晶粒的至少一接合线部分嵌入该FOW层。
20.根据权利要求19所述的半导体装置，其中，该第一晶粒的底面用一粘着层粘合。
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