CN103151256B

CN103151256B - Remove the dry etching method of residual polycrystalline silicon below grid side wall

Info

Publication number: CN103151256B
Application number: CN201110400967.5A
Authority: CN
Inventors: 吴智勇; 刘鹏
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2011-12-06
Filing date: 2011-12-06
Publication date: 2015-08-19
Anticipated expiration: 2031-12-06
Also published as: CN103151256A

Abstract

The invention discloses a kind of dry etching method removing residual polycrystalline silicon below grid side wall, the method is at the end of the polysilicon lead-in wire dry etch process flow of routine, increase the isotropism over etching of a step polysilicon, etching polysilicon residual in the recess under grid abutment wall is fallen.The present invention by adding the isotropic etching processing step that a step is high to oxide-film selection and comparison, polysilicon etch rate is very high in the etching technics of polysilicon lead-in wire loop, thoroughly remove the residual polycrystalline silicon in recess under grid abutment wall, thus improve electric property and the production capacity of device.

Description

Remove the dry etching method of residual polycrystalline silicon below grid side wall

Technical field

The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of dry etching method removing residual polycrystalline silicon below grid side wall.

Background technology

In order to improve the integrated level of economical SiGe BiCMOS (germanium silicon-bipolar transistor-complementary metal oxide field effect transistor), need in SiGe BiCMOS structure, add source and drain polysilicon (SD POLY) structure, simultaneously, in order to reduce cost, source and drain polysilicon will use same layer polysilicon with polysilicon lead-in wire loop (RUNNER POLY) for being connected base polysilicon and emitter-polysilicon.Because source and drain polysilicon directly must contact with the active area (active area, AA) of silicon substrate, therefore, before deposit source and drain polysilicon and polysilicon lead-in wire, the oxide-film on active area must first be removed.Component failure is caused due to other structure can be damaged to the oxide-film of dry etching active area, and it is almost nil by the etching of wet etching oxide-film to other material, namely Selection radio is very high, therefore, must be removed the oxide-film on active area by the method for wet etching.But, when wet etching oxide-film, recess (NOTCH) under grid abutment wall, can be left, when subsequent deposition source and drain polysilicon and polysilicon lead-in wire, also can depositing polysilicon equally in recess, as shown in Figure 1.

Typical polysilicon lead-in wire loop etching technics (after source and drain polysilicon completes), generally includes following processing step, as shown in Figure 2:

1) etching bottom anti-reflecting layer.If be not coated with bottom anti-reflection layer in source and drain polysilicon manufacturing process, then this step can be omitted.

2) natural oxidizing layer is etched.

3) anisotropically etch polysilicon, forms polysilicon lead-in wire.

4) polysilicon over etching, falls recess with the remaining polycrystalline silicon etching of exterior domain.

The defect of above-mentioned process is, cannot remove polysilicon residual in recess, this can affect the electric property of device.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of dry etching method removing residual polycrystalline silicon below grid side wall, and it can improve the electric property of device.

For solving the problems of the technologies described above, the dry etching method of removal residual polycrystalline silicon below grid side wall of the present invention, it is the end of the polysilicon lead-in wire dry etch process flow in routine, increase the isotropism over etching of a step polysilicon, etching polysilicon residual in the recess under grid abutment wall is fallen.

Preferably, after above-mentioned isotropism over etching step completes, can also repeat to do once common polysilicon over etching again.

The present invention is last by the polysilicon lead-in wire loop dry etch process in routine, add a step high to oxide-film selection and comparison, the isotropic etching processing step that polysilicon etch rate is very high, thoroughly remove the residual polycrystalline silicon in recess under grid abutment wall, thus improve electric property and the production capacity of device.

Accompanying drawing explanation

Fig. 1 makes source and drain polysilicon and polysilicon lead-in wire by existing technique, after completing polysilicon deposition, and SEM (electronic scanner microscope) figure of residual polycrystalline silicon below grid side wall.

Fig. 2 is existing typical polysilicon dry etch process flow figure.

Fig. 3 is the polysilicon lead-in wire loop dry etch process flow figure after improving by the method for the present embodiment.

Fig. 4 is after forming polysilicon lead-in wire loop by the technique of Fig. 3, the SEM figure of noresidue polysilicon under grid abutment wall.

Embodiment

Understanding more specifically for having technology contents of the present invention, feature and effect, existing in SiGe BiCMOS processing procedure, being applied as example with the present invention, in conjunction with illustrated execution mode, to technical scheme of the present invention, details are as follows:

In this SiGe BiCMOS processing procedure, source and drain polysilicon and polysilicon lead-in wire loop employ same layer polysilicon.After the manufacture craft completing source and drain polysilicon, the present embodiment carries out the etching of polysilicon lead-in wire according to following steps:

Step 1, etching bottom anti-reflecting layer.Etching gas adopts with Cl ₂(chlorine), CF ₄(carbon tetrafluoride) or HBr (hydrogen bromide) are main mist, and adopting low pressure (1 ~ 15 millitorr), low upper electrode power (100 ~ 300 watts), low bottom electrode power (20 ~ 100 watts), etch period is the etch period of the time ruing out of bottom anti-reflection layer adding 30% ~ 50%.

Step 2, etching natural oxidizing layer.Etching gas is with CF ₄be main, also can add oxygen, to reduce the damage to polysilicon surface.Because natural oxidizing layer is very thin, etch period is very briefer, generally at about 5 ~ 20 seconds.Pressure lower (2 ~ 15 millitorr), upper electrode power 150 ~ 300 watts, lower electrode power is 90 ~ 200 watts.

When the etching gas of step 1 is also with CF ₄when being main, can step 2 be omitted, namely carry out the etching of bottom anti-reflection layer and natural oxidizing layer simultaneously.

Step 3, carries out the main etching of polysilicon with the etching condition that anisotropy is stronger, form the profile in polysilicon lead-in wire loop.

The etching of this step generally adopts low pressure (5 ~ 20 millitorr), higher upper electrode power (300 ~ 600 watts) and lower lower electrode power (30 ~ 90 watts).Etching gas adopts with Cl ₂mist with HBr is main, is aided with CF sometimes ₄, N ₂or O ₂in one or any two kinds of gases improve homogeneity and micro loading effect.Etch period is determined by the polysilicon thickness of deposit, generally etches into polysilicon and also remains about 300 ~ 500 Ethylmercurichlorendimides.

If the etching selection ratio of this step to the oxide-film (i.e. silicon dioxide film, comprises natural oxidizing layer) of general heat growth is less than 4, then also can omit above-mentioned steps 2.

Step 4, the over etching of polysilicon, falls the etching polysilicon in region beyond recess under grid abutment wall.

The etching gas of this step is with HBr and O ₂be main, assist gas N can be mixed simultaneously ₂adopt high pressure 50 ~ 150 millitorr, high upper electrode power (250 ~ 650 watts), lower electrode power is 80 ~ 120 watts, and to the etching selection ratio of oxide-film very high (being generally greater than 100), namely a lot of soon to the etch rate of the etch rate comparison oxide-film of polysilicon.Etch period is clean for polysilicon (except the polysilicon in the recess under grid abutment wall) etching residual for step 3, additionally add the time of 10% ~ 25% more simultaneously, etch period can not be oversize, otherwise can be too thin because of oxide-film, and cause the etching technics window of step 5 too small.

Step 5, the isotropism over etching of polysilicon, the remaining polycrystalline silicon under removing grid abutment wall in recess, as shown in Figure 4.

This step etching is high to the selection and comparison of oxide-film, and between 25 ~ 35, pressure is at about 50 ~ 200MT, and the power of lower electrode is 0 ~ 15 watt, and upper electrode power is lower 50 ~ 200 watts.Etching gas is with SF ₆(sulphur hexafluoride) and O ₂be main, to increase the lateral etching to polysilicon; A large amount of helium (He) can be added dilute, to improve the Selection radio of etching.Etch period was at about 5 ~ 30 seconds, and because this walks the Selection radio of etching to oxide-film lower than step 4, therefore, etch period can not be long, otherwise oxide-film can be etched away.

In order to improve homogeneity further, after step 5, then the polysilicon over etching of a step 4 can be repeated.

Because isotropism over etching is horizontal or longitudinal etch rate to polysilicon is all high than the common over etching of step 4 a lot, therefore, add a step isotropism over etching in the polysilicon lead-in wire loop etching technics of routine after, the time of common over etching (i.e. step 4) can be shortened, thus significantly can increase production capacity.

Claims

1. remove the dry etching method of residual polycrystalline silicon below grid side wall, it is characterized in that, step comprises:

1) etching bottom anti-reflecting layer;

2) natural oxidizing layer is etched;

3) anisotropically etch polysilicon, forms polysilicon lead-in wire;

4) polysilicon over etching, the etching polysilicon that region beyond recess under grid abutment wall is residual falls;

5) the isotropism over etching of polysilicon, falls etching polysilicon residual in the recess under grid abutment wall.

2. method according to claim 1, is characterized in that, described isotropism over etching adopts the etching gas based on sulphur hexafluoride and oxygen.

3. method according to claim 2, is characterized in that, also containing helium in described etching gas.

4. method according to claim 1, is characterized in that, the pressure of described isotropism over etching is 50 ~ 200MT, and lower electrode power is 0 ~ 15 watt, and upper electrode power is 50 ~ 200 watts.

5. method according to claim 1, is characterized in that, the etch period of described isotropism over etching is 5 ~ 30 seconds.

6. method according to claim 1, is characterized in that, described isotropism over etching is 25 ~ 35 to the Selection radio of silicon dioxide film.

7. method according to claim 1, is characterized in that, after described isotropism over etching step completes, try again polysilicon over etching.

8. method according to claim 7, is characterized in that, the etching gas of described polysilicon over etching, based on hydrogen bromide and oxygen, is greater than 100 to the etching selection ratio of silicon dioxide film.