CN103137595A - System-level encapsulation module part and manufacturing method thereof - Google Patents
System-level encapsulation module part and manufacturing method thereof Download PDFInfo
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- CN103137595A CN103137595A CN2011103801614A CN201110380161A CN103137595A CN 103137595 A CN103137595 A CN 103137595A CN 2011103801614 A CN2011103801614 A CN 2011103801614A CN 201110380161 A CN201110380161 A CN 201110380161A CN 103137595 A CN103137595 A CN 103137595A
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- substrate
- package module
- ground connection
- via hole
- dielectric layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a system-level encapsulation module part and a manufacturing method thereof. According to the system-level encapsulation module part and the manufacturing method, a substrate is provided, the substrate comprises circuit layers, welding pads and medium layers, a cutting way is formed on the substrate, grounding buried holes which correspond to the cutting way are formed on at least one medium layers and circuit layers adjacent to medium layers, an electronic assembly is arranged on the substrate, an encapsulating rubber body which coats the electronic assembly is formed on the substrate, then the substrate is cut along the cutting way to expose grounding buried holes, and finally, shielding layers are formed on the encapsulating rubber body and side walls of the substrate, so that all system-level encapsulation module parts can be obtained, the interference of electromagnetic radiation can be prevented, and a little space on the top face of the substrate and a little space on the bottom face of the substrate are not occupied.
Description
Technical field
The present invention is about a kind of technology of package module spare, particularly about a kind of system in package (System in Package; Be called for short SiP) modular member and manufacture method thereof.
Background technology
In scientific and technological industry now, Electro Magnetic Compatibility (Electromagnetic Compatibility; Be called for short EMC) always be considerable research theme in the electromagnetism field, be also one of important issue of facing of the manufacturer of package module spare and how to avoid electromagnetic interference.
On the manufacturing technology of existing package module spare, normally after the manufacturing of package module spare is completed, install screening cover (Shielding Lid) additional in package module spare periphery, with the interference that prevents electromagnetic radiation, package module spare is impacted, but it is larger that this has the package module spare of screening cover required space, the space of reducing line pattern.
In addition, in the manufacture process of system-in-package module spare, some manufacturer can require sealing in package module spare (Molding), makes package module spare have integrated circuit (Integrated Circuit; Abbreviation IC) profile.But, after the sealing of package module spare, just can't install screening cover on package module spare, therefore also can't prevent the interference of electromagnetic radiation.
Therefore, in order to address the above problem, some manufacturer can the system after this package module spare manufacturing is completed on design one can be corresponding to the groove of package module spare, wherein, this groove prevents thus that corresponding to the position of package module spare package module spare is subject to the interference of electromagnetic radiation.
Although above-mentioned mode has solved the problem of the electromagnetic interference of package module spare, yet need to design extra member in system, therefore increased design complexities and manufacturing cost.In addition, due to the position of groove corresponding to package module spare, so the position of groove and package module spare is limited each other, elasticity more not on design as a whole.
In addition, some manufacturer attempts to install member and is subject to the interference of electromagnetic radiation to prevent package module spare on the substrate of package module spare, yet but can take the more space on the substrate, has affected the placing space of other electronic building bricks.
Summary of the invention
The purpose of this invention is to provide a kind of system-in-package module spare and manufacture method thereof, it can avoid package module spare to be subject to the interference of electromagnetic radiation.
Another object of the present invention is to provide a kind of system-in-package module spare and manufacture method thereof, it does not more occupy the end face of substrate and the space on the bottom surface, and does not more affect the placing space of other electronic building bricks.
Reach in order to achieve the above object other purpose, the present invention comprises substrate, electronic building brick, packing colloid and screen in being to provide a kind of system-in-package module spare.Substrate includes line layer, is formed at weld pad and dielectric layer on this line layer, and be formed with Cutting Road on this substrate, and at least one dielectric layer in this dielectric layer and the line layer of adjacent this dielectric layer are formed with ground connection buried via hole that should Cutting Road, and contiguous this ground connection buried via hole of this weld pad; Electronic building brick and packing colloid are formed at respectively on this substrate, and wherein, this packing colloid coats this electronic building brick; Screen coats the sidewall of this packing colloid and this substrate.
Moreover, the present invention also provides a kind of manufacture method of system-in-package module spare, it comprises the following steps: (1) preparation one substrate, this substrate comprises line layer, forms weld pad and dielectric layer on this line layer, and be formed with Cutting Road in this substrate, and at least one dielectric layer in this dielectric layer and the line layer of adjacent this dielectric layer are formed with ground connection buried via hole that should Cutting Road, contiguous this ground connection buried via hole of this weld pad; (2) provide at least one electronic building brick, this electronic building brick is arranged on this substrate; (3) form the packing colloid that coats this electronic building brick on substrate; (4) cut this substrate along this Cutting Road, to expose this ground connection buried via hole; (5) sidewall in this packing colloid and this substrate forms screen, to get each system-in-package module spare.
Therefore, by screen being formed on the sidewall of substrate, so that electromagnetic radiation is by screen and ground connection, avoiding the problem of electromagnetic interference, thereby replace the screening cover that prior art is used fully.And the structure of system-in-package module spare of the present invention does not more occupy the end face of substrate and the space on the bottom surface, and does not more affect the placing space of other electronic building bricks.
Description of drawings
Fig. 1 is the constructed profile of system-in-package module spare of the present invention;
Fig. 2 is the constructed profile of one deck line layer and dielectric layer wherein in Fig. 1; And
Fig. 3 to Fig. 8 is the step schematic diagram of the manufacture method of system-in-package module spare of the present invention
In figure,
1, system-in-package module spare;
11, substrate;
111, dielectric layer;
112, line layer;
113, insulating barrier;
114, end face;
115, the bottom surface;
116, supporting region;
117, Cutting Road;
118, sidewall;
12, electronic building brick;
13, weld pad;
131, upper surface;
132, cutting zone;
14, screen;
15, packing colloid;
16, the ground connection buried via hole.
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, the personage who is familiar with this skill can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
It should be noted that, in the present invention, the graphic upper shown ratio of each assembly is exaggerated slightly, its objective is for the convenience on narrating, and for graphic being easy to read and identification, be not to limit the present invention yet.
Please consult simultaneously Fig. 1 and Fig. 2, Fig. 1 is the constructed profile of system-in-package module spare of the present invention, and Fig. 2 is the constructed profile of one deck line layer 112 and dielectric layer 111 wherein in Fig. 1.System-in-package module spare 1 of the present invention comprises substrate 11, electronic building brick 12, screen 14 and packing colloid 15.What specify is, system-in-package module spare 1 of the present invention also can be applicable to the package module spare of other kinds, and at electronic building brick 12 of the present invention take chip as example, but not as limit.Because its detailed structure of chip of the present invention is identical with existing chip, therefore only presents in the mode of illustrating in graphic, and no longer given unnecessary details for the structure of chip.In addition, in Fig. 1, although the upper surface of general line layer 112 is laid with weld pad, yet for convenience of description, it is omitted weld pad unrelated to the invention.Moreover, in Fig. 2, because the circuit that the upper surface of line layer 112 is laid is too complicated, and be not emphasis of the present invention, therefore for the graphic clear convenience that is easy to identification and explanation is omitted it.
See also Fig. 1, substrate 11 is by one deck dielectric layer 111 and the mutual storehouse of at least one sandwich circuit layer 112 form at least, and the end face 114 at substrate 11 is formed with respectively insulating barrier 113 with bottom surface 115, wherein, line layer 112 is in order to lay circuit (namely forming circuit by pattern etched), dielectric layer 111 causes short circuit, electronic building brick 12 to be arranged on the end face 114 of this substrate 11 in order to prevent adjacent lines layer 112 from contacting with each other, and contacts with a line layer 112.In addition, the end face and the insulating barrier on the bottom surface 113 that are positioned at substrate 11 form with coating method, and form circuit due to this line layer 112 by pattern etched, therefore insulating barrier 113 part can be formed on the surface of line layer 112, and flow into some etched and be not formed with on the surface of dielectric layer 111 of line layer 112.In addition, in one embodiment, this insulating barrier 113 is green enamelled coating.
It should be noted that, although present four sandwich circuit layers 112 in graphic, such presentation mode only is used for explanation.When in fact implementing, line layer 112 with even level for better, especially take more than four layers as best.
As shown in Figure 2, the upper surface 131 of line layer 112 is formed with at least one weld pad 13 and dielectric layer 111, this weld pad 13 is arranged at the cutting zone of reserving in the upper surface 131 of this line layer 112, wherein, this cutting zone be positioned at this upper surface 131 around, and ground connection buried via hole 16 is formed in the line layer 112 of this dielectric layer 111 and adjacent this dielectric layer 111, and each weld pad 13 is respectively adjacent to corresponding ground connection buried via hole 16, wherein, this weld pad 13 surrounds regional surface area and is slightly larger than the surface area that this ground connection buried via hole 16 surrounds the zone.In addition, in one embodiment, be electroplate with metallic conductor in this ground connection buried via hole 16, and this metallic conductor contacts this weld pad 13.
See also back Fig. 1, this ground connection buried via hole 16 is not to be formed in all dielectric layers 111.As shown in the figure, this ground connection buried via hole 16 is not formed in the superiors and the most undermost dielectric layer, and only is formed in the line layer of dielectric layer between the superiors and undermost dielectric layer and adjacent this dielectric layer.
in addition, packing colloid 15 is formed on this substrate 11 and coats all sides and the end face of electronic building brick 12, and screen 14 further coats the sidewall 118 of packing colloid 15 and substrate 11, wherein, screen 14 is metal level, can splash or the mode of plated film coat all sides of packing colloid 15 and the sidewall 118 of end face and substrate 11, can prevent that thus the electromagnetic interference that external electronic components produces (can be described as Electronmagnetic Stamina, EMS), simultaneously, prevent that this electronic building brick 12 electromagnetic noise that is unfavorable for other system that produces in the process of carrying out proper function [can be described as electromagnetic interference, EMI].It should be noted that, every material with metallic character, for example silver or copper, all can be used as screen 14, and coat packing colloid 15 and substrate 11 and sidewall 118, but not as limit.
By above-mentioned content as can be known, each sandwich circuit layer 112 and upper surface 131 are equipped with at least one weld pad 13, and each sandwich circuit layer 112 and upper surface 131 and 13 alignment of at least one weld pad arrange, and each weld pad 13 is contiguous to be arranged corresponding to this ground connection buried via hole 16 respectively, wherein, this ground connection buried via hole 16 only is formed in the line layer of dielectric layer between the superiors and orlop and dielectric layer and adjacent this dielectric layer.
Please consult simultaneously Fig. 1 to Fig. 2 and Fig. 3 to Fig. 8, wherein, Fig. 3 to Fig. 8 is manufacture method ground, system-in-package module spare ground, the present invention ground step schematic diagram.
As shown in Figure 3, in step S1, in the preparation basal plate making process, to one deck dielectric layer 111 and the mutual storehouse of at least one sandwich circuit layer 112 at least, and in top layer and the bottom sequentially arrange respectively an insulating barrier 113, line layer 112 with the dielectric layer 111 that does not have ground connection buried via hole 16 to form substrate 11, wherein, each line layer 112 has respectively at least one weld pad 13, and the end face of substrate 11 has between a plurality of supporting regions 116 and adjacent two supporting regions 116 and is formed with Cutting Road 117.Then proceed to step S2.In addition, in one embodiment, this insulating barrier 113 is green enamelled coating.
Further, see also Fig. 4 and Fig. 5, be the step-by-step procedures of preparation basal plate making process.
At first, as shown in Figure 4, be provided with at least one weld pad 13 on the upper surface of a line layer 112, wherein, line layer 112 is reserved with cutting zone 132 in forming process, and at least one weld pad 13 is arranged in the cutting zone 132 that line layer 112 is reserved.
Then, as shown in Figure 5, form ground connection buried via hole 16 in the cutting zone 132 of line layer 112 and the regional extent that surrounds corresponding to Cutting Road 117 and corresponding each weld pad 13, and this ground connection buried via hole 16 must run through the line layer 112 of middle dielectric layer 111 with adjacent this middle dielectric layer 111, wherein, can use machine drilling, or form this ground connection buried via hole 16 with bore modes such as laser hot melting ways, and contiguous this ground connection buried via hole 16 of this weld pad 13.What specify is, be positioned at due to weld pad 13 on the upper surface of line layer 112, and ground connection buried via hole 16 is arranged in dielectric layer 111, and therefore in Fig. 4 and Fig. 5, weld pad 13 and ground connection buried via hole 16 are represented by dotted lines.In addition, in one embodiment, be electroplate with metallic conductor in this ground connection buried via hole 16, and this metal guide system contacts this weld pad 13.
It should be noted that, because the manufacture process of each line layer 112 is identical, therefore, in the present invention only with the explanation of a line layer 112 as execution mode, and the position of the cutting zone 132 reserved of each line layer 112 is identical, therefore, and weld pad 13 alignment mutually that each line layer 112 is set, and the Cutting Road 117 that is positioned at the end face of substrate 11 also can corresponding to the cutting zone 132 of each line layer 112, make the set weld pad of cutting zone 132 also corresponding to Cutting Road 117.
In addition, separately it should be noted that, in fact, cutting zone 132 is reserved on line layer 112, be not to draw out this cutting zone 132 by any sign, in Fig. 3 for need on narrating and make graphic be easy to identification and explanation and select especially a cutting zone 132 be drawn on graphic in.
As shown in Figure 3, in step S2, provide at least one electronic building brick 12, this electronic building brick 12 is arranged on this substrate.Then proceed to step S3.
See also Fig. 6, in step S3, carry out encapsulation procedure, namely after forming substrate 11, then the set a plurality of electronic building bricks 12 of substrate 11 are carried out respectively sealing, wherein, during sealing, formed packing colloid 15 coats all sides and the end face of electronic building brick 12.Then proceed to step S4.
See also Fig. 7, in step S4, cut processing procedure, namely after encapsulation is complete, then the Cutting Road 117 along substrate 11 cuts, make substrate 11 be cut into a plurality of substrates, and a plurality of substrates that form after cut carry electronic building brick 12 and packing colloid 15 separately, and expose this ground connection buried via hole 16, wherein, due to the cutting zone 132 that Cutting Road 117 positions are reserved corresponding to each line layer 112, therefore, Cutting Road 117 can be aligned in the cutting zone 132 of each line layer 112.Then proceed to step S5.
See also Fig. 8, in step S5, after cutting is complete, then in the sidewall 118 formation screens 14 of packing colloid 15 with substrate, to get each system-in-package module spare.
Be noted that, screen 14 is metal level, and can splash or the mode of plated film coat the sidewall 118 of this packing colloid 15 and substrate, with the metallic character by screen 14, make this system-in-package module spare have good Electro Magnetic Compatibility (ElectroMagnetic Compatibility, EMC).
In sum, be subject to the interference of electromagnetic radiation except preventing electronic building brick, the structure of system-in-package module spare of the present invention does not more occupy the end face of substrate and the space on the bottom surface, and does not more affect the placing space of other electronic building bricks.
Yet above-described embodiment is in order to illustrative principle of the present invention and effect thereof, but not is used for restriction the present invention.Any personage who has the knack of this skill all can under spirit of the present invention and category, modify to above-described embodiment.So the scope of the present invention, claim is listed as described later.
Claims (11)
1. a system-in-package module spare, is characterized in that, comprising:
Substrate, it comprises at least one line layer, at least one weld pad and at least one dielectric layer that is formed on this line layer, and be formed with Cutting Road on this substrate, and the wherein at least one dielectric layer in this dielectric layer and the line layer of adjacent this dielectric layer are formed with ground connection buried via hole that should Cutting Road, contiguous this ground connection buried via hole of this weld pad;
Electronic building brick, it is arranged on this substrate;
Packing colloid, it is formed on this substrate and coats this electronic building brick; And
Screen, it coats the sidewall of this packing colloid and this substrate.
2. the system as claimed in claim 1 level package module spare, is characterized in that, wherein, the surface area that described weld pad surrounds the zone surrounds the surface area in zone greater than this ground connection buried via hole.
3. the system as claimed in claim 1 level package module spare, is characterized in that, wherein, is to be electroplate with metallic conductor in this ground connection buried via hole.
4. the system as claimed in claim 1 level package module spare, is characterized in that, wherein, this screen is metal level.
5. the system as claimed in claim 1 level package module spare, is characterized in that, wherein, these shielding series of strata coat the sidewall of this packing colloid and this substrate in the mode of splash or plated film.
6. the system as claimed in claim 1 level package module spare, it is characterized in that, wherein, this substrate is the dielectric layer that includes at least one insulating barrier, at least one line layer and do not have this ground connection buried via hole, this line layer is formed on this dielectric layer, and this insulating barrier is formed at end face and the bottom surface of this substrate.
7. the manufacture method of a system-in-package module spare, is characterized in that, comprises the following steps:
(1) preparation one substrate, this substrate comprises at least one line layer, forms at least one weld pad and at least one dielectric layer on this line layer, and be formed with Cutting Road in this substrate, and the wherein at least one dielectric layer in this dielectric layer and the line layer of adjacent this dielectric layer are formed with ground connection buried via hole that should Cutting Road, contiguous this ground connection buried via hole of this weld pad;
(2) provide at least one electronic building brick, this electronic building brick is arranged on this substrate;
(3) carry out encapsulation procedure, to form the packing colloid that coats this electronic building brick on this substrate;
(4) cut this substrate along this Cutting Road, for exposing this ground connection buried via hole; And
(5) sidewall in this packing colloid and this substrate forms screen, to get each system-in-package module spare.
8. the manufacture method of system-in-package module spare as claimed in claim 7 is characterized in that, wherein, in this step (1), this ground connection buried via hole is formed with machine drilling or laser hot melting way.
9. the manufacture method of system-in-package module spare as claimed in claim 7 is characterized in that, wherein, in this step (5), this screen is coated the sidewall of this packing colloid and this substrate in the mode of splash or plated film.
10. the manufacture method of system-in-package module spare as claimed in claim 7 is characterized in that, wherein, in this step (1), further is electroplate with metallic conductor in this ground connection buried via hole.
11. the manufacture method of system-in-package module spare as claimed in claim 7 is characterized in that, wherein, this substrate is to be formed with at least one insulating barrier, and these insulation series of strata are formed on the end face and bottom surface of this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103801614A CN103137595A (en) | 2011-11-25 | 2011-11-25 | System-level encapsulation module part and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103801614A CN103137595A (en) | 2011-11-25 | 2011-11-25 | System-level encapsulation module part and manufacturing method thereof |
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| CN103137595A true CN103137595A (en) | 2013-06-05 |
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| CN2011103801614A Pending CN103137595A (en) | 2011-11-25 | 2011-11-25 | System-level encapsulation module part and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110099509A (en) * | 2019-04-08 | 2019-08-06 | Oppo广东移动通信有限公司 | Circuit board and electronic equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100032815A1 (en) * | 2008-08-08 | 2010-02-11 | An Jaeseon | Semiconductor device packages with electromagnetic interference shielding |
| CN101814484A (en) * | 2009-02-19 | 2010-08-25 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN102054821A (en) * | 2009-10-30 | 2011-05-11 | 日月光半导体制造股份有限公司 | Packaging structure with internal shield and manufacturing method thereof |
| CN102064141A (en) * | 2010-04-29 | 2011-05-18 | 日月光半导体制造股份有限公司 | Semiconductor device package for shielding electromagnetic interference |
| CN102074551A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing method thereof |
| CN102074552A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing methods thereof |
-
2011
- 2011-11-25 CN CN2011103801614A patent/CN103137595A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100032815A1 (en) * | 2008-08-08 | 2010-02-11 | An Jaeseon | Semiconductor device packages with electromagnetic interference shielding |
| CN101814484A (en) * | 2009-02-19 | 2010-08-25 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN102054821A (en) * | 2009-10-30 | 2011-05-11 | 日月光半导体制造股份有限公司 | Packaging structure with internal shield and manufacturing method thereof |
| CN102074551A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing method thereof |
| CN102074552A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing methods thereof |
| CN102064141A (en) * | 2010-04-29 | 2011-05-18 | 日月光半导体制造股份有限公司 | Semiconductor device package for shielding electromagnetic interference |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110099509A (en) * | 2019-04-08 | 2019-08-06 | Oppo广东移动通信有限公司 | Circuit board and electronic equipment |
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Application publication date: 20130605 |