CN102064141A - Semiconductor device package for shielding electromagnetic interference - Google Patents
Semiconductor device package for shielding electromagnetic interference Download PDFInfo
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- CN102064141A CN102064141A CN 201010564617 CN201010564617A CN102064141A CN 102064141 A CN102064141 A CN 102064141A CN 201010564617 CN201010564617 CN 201010564617 CN 201010564617 A CN201010564617 A CN 201010564617A CN 102064141 A CN102064141 A CN 102064141A
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- Prior art keywords
- base board
- board unit
- semiconductor device
- remnants
- grounding assembly
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Images
Classifications
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
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- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
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- H01L2924/30—Technical effects
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- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Described are a semiconductor device package for shielding electromagnetic interference and a related method. In one embodiment, the semiconductor device package includes a grounding element which is disposed adjacent to the periphery of a substrate unit and at least partially extends between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an electromagnetic interference shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.
Description
Technical field
The invention relates to a kind of device of semiconductor device packages part, and particularly relevant for a kind of device that covers the semiconductor device packages part of electromagnetic interference.
Background technology
Be subjected to promoting the demand of process speed and size downsizing, semiconductor device becomes and gets over complexity.When process speed promotes and size is dwindled benefit obviously increased, the characteristic of semiconductor subassembly also went wrong.Especially, higher operating frequency (clock speed) causes more frequent transition (transition) between signal level (signal level), when higher frequency or shorter wavelength, these signal levels can cause the electromagnetic radiation (electromagnetic emission) of a more high-grade intensity.Electromagnetic radiation can be emitted by semiconductor device source, and can be incident to contiguous semiconductor device.If under the sufficiently high situation of grade strength of the electromagnetic radiation of a contiguous semiconductor device, these radiation will have influence on the operation of semiconductor device unfriendly.This situation be commonly called be electromagnetic interference (electromagnetic interference, EMI).In a whole electronic system highdensity semiconductor device is arranged, the semiconductor device of this smaller szie will make the effect of electromagnetic interference worsen more, therefore, have one not wish the electromagnetic radiation of the more high-grade intensity that produces on adjoining semiconductor device.
A kind of method that reduces electromagnetic radiation is exactly that the whole semiconductor device of organizing in the semiconductor device packaging part is covered shielding (shield).Specifically, this shielding can be via comprising that an outside of being close to packaging part makes the electrical conduction housing or the lid of ground connection and reach.When the inner surface of this housing was attacked in the electromagnetic radiation that comes from packaging part inside, the electromagnetic radiation of at least a portion can be by short circuit electrically (short), therefore reduced by the width of cloth of housing and penetrated strength grade and to the adverse effect of contiguous semiconductor device.Similarly, when attacking the outer surface of this housing from the electromagnetic radiation of a contiguous semiconductor device, similarly electrically short-circuit conditions also can produce, to reduce the electromagnetic interference to semiconductor device in the packaging part.
Can reduce electromagnetic interference though one electrically conducts housing, this housing can run into some shortcomings in the use.Especially, this housing generally is adjacent to the outside of semiconductor device packages part via an adhesive agent.Unfortunately, because the adhesive properties of adhesive agent is subjected to adverse influences such as temperature, moisture and other ambient conditions, make housing be easy to peel off or come off.Similarly, when being close to housing on the packaging part, the size and dimension of housing and the size and dimension of packaging part should mate under the less grade of tolerance.Coupling on the size and dimension of housing and packaging part, and housing and the combination accuracy of packaging part on relevant position will cause manufacturing cost and temporal consumption.Consider the coupling of size and shape, the semiconductor device packages part of different size and shape can need different housings, and these different housings that are used for holding different packaging parts can further increase manufacturing cost and time.
In order to overcome this situation, a kind of semiconductor device packages part and relevant method thereof explain at this.
Summary of the invention
The present invention is relevant for a kind of semiconductor device packages part that covers electromagnetic interference.In one embodiment, semiconductor device packaging part comprises: (1) one base board unit, comprise (a) upper surface, (b) a lower surface, (c) lateral surface, be provided be adjacent to base board unit around, and fully extend between the upper surface and lower surface of base board unit, and (d) grounding assembly, be provided be adjacent to base board unit around, and extend to small part between the upper surface and lower surface of base board unit; (2) semiconductor device is provided with and is adjacent to the upper surface of base board unit, and is electrically connected to base board unit; (3) one packaging bodies are provided with the upper surface that is adjacent to base board unit, and cover semiconductor device, and packaging body comprises several outer surfaces, and these a little outer surfaces comprise a lateral surface; And (4) one the setting of electromagnetic interference covering be adjacent to the lateral surface of the outer surface and the base board unit of packaging body, this electromagnetic interference covering is electrically connected to grounding assembly, and inside recessed adjoining farmland neighbour is connected to the sunk part of grounding assembly.
In another embodiment, the semiconductor device packages part comprises: (1) one base board unit, comprise (a) first surface, (b) one second apparent surface, and (c) extend the first surface of base board unit and the grounding assembly between second apparent surface to small part, this grounding assembly comprises the tabular channel remnants of defeated troops and a filler, this tabular passage remnants of defeated troops inside concave type ground is to hold filler, and these tabular passage remnants of defeated troops and filler define a lateral surface that is adjacent to base board unit grounding assembly on every side is set; (2) semiconductor device is provided with and is adjacent to the first surface of base board unit, and is electrically connected to base board unit; (3) one packaging bodies are provided with the first surface that is adjacent to base board unit, and cover semiconductor device, and this packaging body comprises several outer surfaces; (4) one electromagnetic interference coverings, setting is adjacent to the outer surface of packaging body, and be electrically connected to the lateral surface of grounding assembly, wherein the lateral profile of semiconductor device is essentially a plane, and is essentially the right angle with respect to second apparent surface of base board unit.
According to a further aspect in the invention, the method that the semiconductor device packages part of electromagnetic interference is covered in a kind of formation is proposed.In one embodiment, a method comprises: (1) provides a substrate that comprises a ground hole and a core component, and ground hole to small part extends between the upper surface and lower surface of substrate, the through hole channel that ground hole definition one is filled with core component in fact; (2) electrically connect the upper surface of semiconductor device to substrate; (3) impose the upper surface that an adhesive material is put substrate, to form the glue sealing structure of a covering semiconductor device; (4) form the joint-cutting that several extend through glue sealing structure and substrate fully, these joint-cuttings and base plate alignment, make: (a) substrate is cut apart to form one again and is cut apart base board unit; (b) glue sealing structure is cut apart to form the packaging body of cutting apart that a setting is adjacent to base board unit again; And (c) the corresponding grounding assembly that is adjacent to around the base board unit that is provided with of the remnants of defeated troops of the remnants of defeated troops of ground hole and core component, grounding assembly comprises a joint face that exposes; And (5) impose an electromagnetic interference coating to the outer surface of packaging body and the joint face of grounding assembly, to form an electromagnetic interference covering after forming joint-cutting.
Others of the present invention and embodiment are taken into account too.Above-mentioned summary of the invention and following detailed description are not in order to limiting the present invention to arbitrary certain embodiments, but in order to some embodiment of explanation this case.
Description of drawings
Fig. 1 illustrates the semiconductor device packaging part schematic diagram according to one embodiment of the invention.
Fig. 2 illustrates the profile of the semiconductor device packaging part that is intercepted along Figure 1A-A line.
Fig. 3 A illustrates a local amplification profile of the semiconductor device packages part of Fig. 1.
Fig. 3 B illustrate Fig. 1 the semiconductor device packages part one execute real enlarged diagram.
Fig. 3 C illustrates another of semiconductor device packages part of Fig. 1 and executes real enlarged diagram.
Fig. 4 A illustrates a profile of semiconductor device packages part according to another embodiment of the present invention.
Fig. 4 B illustrates a profile of semiconductor device packages part according to another embodiment of the present invention.
Fig. 4 C illustrates a profile of semiconductor device packages part according to another embodiment of the present invention.
Fig. 5 A～5E illustrates the method according to the semiconductor device packages part of formation Fig. 1 of one embodiment of the invention.
Fig. 6 illustrates the method for the semiconductor device packages part of formation Fig. 4 A according to another embodiment of the present invention.
The primary clustering symbol description:
100,400,460,480: the semiconductor device packages part
102,102 ': base board unit
104,504,516,616: upper surface
106,524: lower surface
108a, 108b, 108c, 408b: semiconductor device
110a, 110b, 110c: electrical contact
112: bonding wire
114: packaging body
118a, 118b, 418a, 418b, 462a, 462b, 482a, 482b: grounding assembly
120,122,142,144: lateral surface
124: the electromagnetic interference covering
126: top
128: sidepiece
146a, 146b, 446a, 446b, 466a, 466b, 486a, 486b: go up the via pad remnants of defeated troops
148a, 148b, 448a, 448b, 468a, 468b, 488a, 488b: the lower through-hole pad remnants of defeated troops
150a, 150b, 450a, 450b, 470a, 470b, 490a, 490b: the tabular passage remnants of defeated troops
300: internal layer
302: skin
304: filler
452,464,484a, 484b: electrical conducting shell
500,600: substrate
502a, 502b, 502c, 502d, 502e: ground hole
506,606: adhesive tape
518,618: cast-cutting saw
520a, 520b, 620a, 620b: joint-cutting
522: electromagnetic interference coating
546a, 546b: go up via pad
548a, 548b: lower through-hole pad
550a, 550b: tabular passage
514,614: adhesive material
C
1, C
2: width of slit
H
1, H
2, H
B, H
C: the height of grounding assembly
L
1: the spacing of nearest neighbor ground hole
L
2: the spacing between ground hole and exclusion area
S1, S2, S1 ', S2 ', S1 ", S2 ": joint face
W
1, W
2, W
B, W
C: width
W
3, W
4: lateral extent
W
5: clear size of opening
W
6: the via pad size
Embodiment
The application note of following definition some embodiment of the present invention on some viewpoint.These definition similarly elaborate in this.
Unless indicate clearly in the interior literary composition, otherwise comprised several denoted objects in this used singular item " a ", " an " and " the ".So for instance, unless indicate clearly in the interior literary composition, when mentioning a grounding assembly, this grounding assembly can comprise several grounding assemblies.
Set in the one or more assemblies of this used project " group (set) " expression.So for instance, one deck group can comprise single layer or a plurality of layer.It is the part (members of the set) of this group that one group assembly (components of a set) also can be called.One group assembly can be identical or different.In some example, one group assembly can be shared one or more common features.
In the close or adjacency of this used project " in abutting connection with (adjacent) " expression.Several assemblies of adjacency can separate or directly contact in fact each other each other.In some example, several assemblies of adjacency can be interconnected with one another or be integrally formed.
Used in this for example is " inner (inner) ", " inboard (interior) ", " outside (outer) ", " outside (exterior) ", " top (top) ", " bottom (bottom) ", " preceding (front) ", " back (back) ", " go up (upper) ", " go up ground (upwardly) mutually ", " (lower) down ", " down (downwardly) ", " vertical (vertical) ", " vertically (vertically) ", " (lateral) of side direction ", " laterally (laterally) ", " in ... on (above) " and " in ... under (below) " relevant item represent the direction of a component groups with respect to another component groups, for example be as shown in graphic, but these a little assemblies do not need to be confined to specific direction in manufacture process or in using.
In this used project " connection (connect) ", " being connected (connected) " and " connecting (connection) " the operational coupling of expression or binding.Several coupling assemblings can directly be coupled each other, or coupling indirectly each other, for example couple indirectly each other and reach via the assembly of another group.
In this used project " (substantially) in fact " and " (substantial) in fact " expression one should consider etc. stage or scope.When above-mentioned project connects same incident or situation and uses together, above-mentioned project can presentation of events or the example that takes place exactly of situation, and can presentation of events or the example that under situation very closely, takes place of situation, for example similarly be tolerance progression in the general manufacture process of this explanation.
In the ability of this used project " electrically conduction (electrically conductive) " and " conductivity (electrical conductivity) " expression one current delivery, and lack the ability of current delivery in this used project " non-electrical conduction (electrically non-conductive) " and " non-conductive (electrical non-conductivity) " expression.Normally those show minimum or do not revolt the material of current flowing electric conducting material, and non-conducting material normally those show minimum or are not inclined to the material of conduction current circulation.Every meter several Siemens (Siemens per meter, " Sm
-1") be a kind of linear module of conductivity.In general, an electric conducting material has greater than 10
4Sm
-1Conductibility, for example be minimumly to be about 10
5Sm
-1Perhaps minimumly be about 10
6Sm
-1, and a non-conducting material has less than 10
4Sm
-1Conductibility, for example be to be not more than 10
3Sm
-1Perhaps be not more than 10
2Sm
-1The conductivity of one material can change with temperature sometimes.Unless expressly stated otherwise,, the conductivity of a material is to define in room temperature is following.
At first please refer to Fig. 1 and Fig. 2.Fig. 1 and Fig. 2 illustrate the stereogram according to one embodiment of the invention semiconductor device packaging part 100.Wherein, Fig. 1 illustrates the schematic diagram of semiconductor device packages part 100, and Fig. 2 illustrates along the profile of Figure 1A-semiconductor device packages part 100 that the A line is intercepted.
In this embodiment, several limits of semiconductor device packages part 100 are essentially the plane, and have a substantial right angle orientation to define a lateral profile, and this lateral profile centers on the entire circumference of semiconductor device packages part 100 in fact.Advantageously, the lateral profile at this right angle can be via the pin zone of reducing semiconductor device packages part 100, or the pin zone of semiconductor device packages part 100 minimized and reduces the size of overall package part.Yet in general, the lateral profile of semiconductor device packages part 100 can be an arbitrary shape, as curved, skewed, stepped or coarse structure (roughly textured).Though following illustrated position is inwardly recessed in one group of position of the side profile of semiconductor device packages part 100, yet side profile in fact also can be the plane.
Please refer to Fig. 2, semiconductor device packages part 100 comprises a base board unit 102, and this base board unit 102 comprises a upper surface 104, a lower surface 106 and lateral surface 142 and 144.Wherein, lateral surface 142 and 144 is provided with and is adjacent to the side of base board unit 102, and extends between upper surface 104 and the lower surface 106.In this embodiment, lateral surface 142 and 144 is essentially the plane, and has a substantial right angle orientation with respect to upper surface 104 or lower surface 106.Yet in other was implemented, lateral surface 142 and 144 shape and direction can change to some extent.Base board unit 102 can be implemented with certain methods, and comprises that the electric connection part is to provide electrical path between the upper surface 104 and lower surface 106 of base board unit 102.For example, this electric connection part can comprise the one group of electrical conducting shell that is incorporated in one group of dielectric layer.These a little electrically conducting shells can be connected to each other via interior bone, and be used for clamping by the formed core component of an appropriate resin resin that this resin for example is made up of two Maleimides (bismaleimide) and triazine (triazine) or the resin of being formed by epoxy resin (epoxy) and PPOX (polyphenylene oxide) as sandwich-like.For instance, base board unit 102 can comprise a flat in fact core component, this core component is adjacent to the electrical conducting shell of core component upper surface by one group of setting, and the electrical conducting shell that another group setting is adjacent to the core component lower surface is clamped up and down in the sandwich mode.With some embodiment, the thickness of base board unit 102, be the upper surface 104 of base board unit 102 and the distance between the lower surface 106, can be at about 0.1 millimeter (millimeter, " mm ") to about 2 millimeters scope, for example be from about 0.2 centimetre to about 1.5 centimetres, or from about 0.4 millimeter to about 0.6 millimeter.Though be not illustrated among Fig. 2, a welding screen can be provided with the upper surface 104 that is adjacent to base board unit 102 and one of them person in the lower surface 106, or both.
As shown in Figure 2, base board unit 102 comprises that setting is adjacent to base board unit 102 grounding assembly 118a and 118b on every side.More specifically, grounding assembly 118a and 118b be arranged in fact base board unit 102 around, and be provided with respectively and be adjacent to lateral surface 142 and 144.Grounding assembly 118a and 118b are connected in other electric connection part in the base board unit 102, and as described below, and this grounding assembly 118a and 118b can provide several electrical path to reduce electromagnetic interference.In this embodiment, grounding assembly 118a and 118b are ground hole, and particularly the remaining part (remnant) of ground hole after one group of cutting technique forms, after this group cutting technique will be described in.Please refer to Fig. 2, each grounding assembly 118a and 118b comprise on one the 146a of the via pad remnants of defeated troops or 146b, the once 148a of the via pad remnants of defeated troops or 148b and a tabular passage 150a of the remnants of defeated troops or a 150b, wherein, last via pad 146a of the remnants of defeated troops or 146b are provided with the upper surface 104 that is adjacent to base board unit 102, lower through-hole pad 148a of the remnants of defeated troops or 148b are provided with the lower surface 106 that is adjacent to base board unit 102, and tabular passage 150a of the remnants of defeated troops or 150b extend between the 146a of the via pad remnants of defeated troops or 146b and lower through-hole pad 148a of the remnants of defeated troops or the 148b.Though grounding assembly 118a and 118b are between this is illustrated to the upper surface 104 and lower surface 106 that fully extend base board unit 102, yet in other was implemented, the scope of grounding assembly 118a and 118b can be to change to some extent.
Please refer to Fig. 2, grounding assembly 118a and 118b comprise joint face S1 and S2 respectively, and joint face S1 and S2 are the side of backside semiconductor device packaging part 100 inboards, and be provided be adjacent to base board unit 102 around.More specifically, joint face S1 and S2 in fact electrically be exposed to base board unit 102 around, and respectively electrically contact be adjacent to lateral surface 142 and 144.In this embodiment, joint face S1 and S2 are corresponding to the electrical contact-making surface of the last via pad 146a of the remnants of defeated troops and 146b, the lower through-hole pad 148a of the remnants of defeated troops and 148b and tabular passage 150a of the remnants of defeated troops and 150b.Advantageously, joint face S1 that area is bigger and S2 can increase reliability and the usefulness that electrically connects part, to reduce electromagnetic interference.Grounding assembly 118a and 118b have material or another the suitable electrical conductive material that a metal or a metal alloy intersperse among wherein by a metal, a metal alloy, and are formed.Concerning some is implemented, the height H of grounding assembly 118a and 118b
1Be the vertical range of grounding assembly 118a and 118b, can be equal to the thickness of base board unit 102 in fact, and can be about 0.1 millimeter to about 2 millimeters scope, for example be from about 0.2 millimeter to about 1.5 millimeters, or from about 0.4 millimeter to about 0.6 millimeter.The width W 1 of grounding assembly 118a and 118b, an i.e. lateral extent that is adjacent to upper surface 104 or lower surface 106, can be about 75 microns (micrometer, " μ m ") to about 275 microns scope, for example be from about 100 microns to about 250 microns, or from about 125 microns to about 225 microns.
As shown in Figure 2, semiconductor device packages part 100 also comprises semiconductor device 108a, 108b and 108c, and electrical contact 110a, 110b and 110c.Wherein semiconductor device 108a, 108b and 108c are provided with the upper surface 104 be adjacent to base board unit 102, and electrically contact 110a, 110b and 110c are provided with the lower surface 106 that is adjacent to base board unit 102.Semiconductor device 108b by one group by gold or other formed bonding wire 112 wire bonds of suitable electrical conductive material (wire-bonded) to base board unit 102, and semiconductor device 108a and 108c surface are fixed on the base board unit 102.In this embodiment, semiconductor device 108b is the semiconductor chip, and semiconductor device 108a and 108c are passive component, for example are resistor, capacitor or inductor.Electrically contact 110a, 110b and 110c provide the input and output electric connection for semiconductor device packages part 100, and at least a portion is electrically connected to semiconductor device 108a, 108b and 108c by the electric connection part in the base board unit 102 among electrical contact 110a, 110b and the 110c.In this embodiment, electrically contact 110a, 110b and 110c wherein at least one is the electrical contact of a ground connection, and be electrically connected to grounding assembly 118a and 118b by the electric connection part in the base board unit 102.Though illustrated three semiconductor devices among Fig. 2, yet in other is implemented, can have in more or less semiconductor device is included in, and in general, semiconductor device can be any driving component, passive component or it makes up arbitrarily arbitrarily.Similarly, the electrical contact number that is illustrated among Fig. 2 can change to some extent.
Please refer to Fig. 2, semiconductor device packages part 100 also comprises the packaging body 114 that the upper surface 104 that is adjacent to base board unit 102 is set.This packaging body 114 is connected in base board unit 102; and cover grounding assembly 118a and 118b, semiconductor device 108a, 108b and 108c and bonding wire 112 in fact or with component package such as above-mentioned in inside; so that mechanical stability to be provided, and protect these assemblies in case the influence of oxidation, moisture and other ambient conditions.Packaging body 114 is formed by adhesive material, and packaging body 114 comprises several outer surfaces, and these outer surfaces comprise the lateral surface 120 and 122 that is adjacent to packaging body 114 sides is set.In this embodiment, lateral surface 120 and 122 is essentially the plane, and has a substantial right angle orientation with respect to upper surface 104 or lower surface 106.Yet in other was implemented, lateral surface 120 and 122 can be curved, skewed, stepped or coarse structure (roughly textured).In addition, lateral surface 120 and 122 is aimed at lateral surface 142 and 144 in fact respectively, or and lateral surface 142 and 144 be copline.More specifically, when carrying out this aligning, can be for example via the coverage rate of minimizing or minimized packaging body 114 and joint face S1 and S2, allowing joint face S1 and S2 is (the electrically exposed) that electrically exposes.In other is implemented, be electrical exposure at least in part as long as allow joint face S1 and S2, lateral surface 120 and 122 shape, and lateral surface 120 and 122 and the aligning of lateral surface 142 and 144 can be to be different from Fig. 2.
As depicted in figs. 1 and 2, semiconductor device packages part 100 more comprises an electromagnetic interference covering 124.This electromagnetic interference covering 124 is provided with the joint face S1 of several outer surfaces, grounding assembly 118a and the 118b that are adjacent to packaging body 114 and the lateral surface 142 and 144 of S2 and base board unit 102.Electromagnetic interference covering 124 is formed by electrical conductive material, and semiconductor device 108a, 108b and the 108c in the semiconductor device packages part 100 in fact, so that the protection to electromagnetic interference to be provided.In this embodiment, electromagnetic interference covering 124 comprises a top 126 and a sidepiece 128, its in fact extended loop and define the right-angled side faces profile of semiconductor device packages part 100 around the entire circumference of packaging body 114.As shown in Figure 2, sidepiece 128 extends downwards by top 126 and along the lateral surface 142 and 144 of base board unit 102, sidepiece 128 comprises a lower end, this lower end in fact align substrates unit 102 lower surface 106 or and this lower surface 106 be copline.Yet, in other is implemented, the scope of sidepiece 128 with and the aligning of lower end and lower surface 106 can change to some extent.
As shown in Figure 2, electromagnetic interference covering 124 is electrically connected to joint face S1 and the S2 of grounding assembly 118a and 118b.When electromagnetic radiation when semiconductor device packaging part 100 internal emission come out to attack electromagnetic radiation covering 124, at least a portion of these a little radiation can be by grounding assembly 118a and 118b by ground connection effectively, thereby reduce the grade strength of the radiation can pass electromagnetic interference covering 124, and reduce adverse effect to contiguous semiconductor device.Similarly, when this electromagnetic interference covering 124 is attacked in an electromagnetic radiation that comes from contiguous semiconductor device, similar ground connection effect can take place, with semiconductor device 108a, 108b in the minimizing semiconductor device packages part 100 and the electromagnetic interference of 108c.In technical process, semiconductor device packages part 100 can be set on the printed circuit board (PCB) (PCB), and electrically connects printed circuit board (PCB) so far via electrical contact 110a, 110b and 110c.As previously mentioned, electrically at least one among contact 110a, 110b and the 110c is the electrical contact of a ground connection, and the electrical contact of this ground connection is electrically connected to one by a earthed voltage that printed circuit board (PCB) provided.Can produce ground connection to the electromagnetic radiation that is incident on the electromagnetic interference covering 124 by an electrical path, this electrical path can include grounding assembly 118a and 118b, be included in other electric connection part and the electrical contact of ground connection in the base board unit 102.Because the lower end of this electromagnetic interference covering 124 is aimed at the lower surface 106 of base board unit 102 in fact, this lower end also can be electrically connected to an earthed voltage that is provided by printed circuit board (PCB), the electrical path that provides other to be used for the electromagnetic radiation ground connection of will not wish to produce by this.Perhaps, in this syndeton, lower through-hole pad 148a of the remnants of defeated troops and 148b can be electrically connected to one by a earthed voltage that printed circuit board (PCB) provided.
In this embodiment, electromagnetic interference covering 124 forms the conformal covering of a cluster film (a set of layers or films).Advantageously, electromagnetic interference covering 124 need not used an adhesive agent, can form be adjacent to and directly contact semiconductor device packaging part 100 outside or and the outside of semiconductor device packages part 100 directly contact, strengthen reliability by this and to the resistance of temperature, moisture and other ambient conditions.The conformal nature of electromagnetic interference covering 124 allows similar electromagnetic interference to cover and similar technology, and be easy to be applied on the semiconductor device packages part of different size and shape, thereby can reduce the manufacturing cost and the time of different semiconductor device packages parts.Concerning some is implemented, the thickness of electromagnetic interference covering 124 can be about 1 micron to about 500 microns scope, for example be from about 1 micron to about 100 microns, from about 1 micron to about 50 microns, or from about 1 micron to 10 microns.Another advantage of this embodiment is that with respect to general housing (casing), the thickness that electromagnetic interference covering 124 is reduced can allow the reduction of overall semiconductor device package size.
Then please refer to Fig. 3 A.Fig. 3 A illustrates the amplification profile of a part of the semiconductor device packages part 100 of Fig. 1 and Fig. 2.More specifically, Fig. 3 A illustrates the specifically enforcement that a setting is adjacent to the electromagnetic interference covering 124 of packaging body 114.
As shown in Figure 3A, electromagnetic interference covering 124 is (multi-layered) of multilayer, and comprises an internal layer 300 and a skin 302.Internal layer 300 is provided with and is adjacent to packaging body 114.Outer 302 are provided with the outside that is adjacent to internal layer 300 and is exposed to semiconductor device packages part 100.In general, each in the internal layer 300 and outer 302 can have material or another the suitable electrical conductive material that a metal or a metal alloy intersperse among wherein by a metal, a metal alloy, and formed.For instance, each in the internal layer 300 and outer 302 can be formed by aluminium, copper, chromium, titanium, gold, silver, nickel, stainless steel or its composition.Internal layer 300 is formed by identical electrical conductive material or different electrical conductive materials with outer 302.For instance, a metal for example is a nickel, and can be selected to be used as is internal layer 300 and outer 302.In some instances, it is internal layer 300 and skin 302 that different electrical conductive materials can selectedly be used as, so that complementary function to be provided.For instance, one has the high electrically metal of conductivity, for example is aluminium, copper, gold or silver, and the function of internal layer 300 to provide electromagnetic interference to cover can selectedly be provided.On the other hand, one has the metal of low electrical conductivity, for example is nickel, can selectedly be used as outer 302 to protect internal layer 300 to avoid being subjected to the influence of oxidation, moisture and other ambient conditions.In this case, outer 302 also can contribute the function that electromagnetic interference is covered, and the effect of protection is provided simultaneously.Though in Fig. 3 A, illustrate two layers, yet in other is implemented, can be to include more or less layer.
Then, please refer to Fig. 3 B and Fig. 3 C.Fig. 3 B and Fig. 3 C have illustrated the amplification profile of a part of the semiconductor device packages part 100 of Fig. 1 and Fig. 2.More specifically, Fig. 3 B illustrates the specific embodiment of a grounding assembly 118b, and Fig. 3 C illustrates another specific embodiment of a grounding assembly 118b.In order clearly to express, following feature explains with reference to the grounding assembly 118b that setting is adjacent to the lateral surface 144 of base board unit 102, yet what need consideration is that these features can be applied on the grounding assembly of other semiconductor device packages part 100 similarly, for example is grounding assembly 118a.
Please refer to Fig. 3 B, grounding assembly 118b ground hole forms through the remaining part after one group of cutting technique, and comprises the 146b of the via pad remnants of defeated troops, the lower through-hole pad 148b of the remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops.The tabular passage 150b of the remnants of defeated troops is corresponding to the sunk part of grounding assembly 118b, and is inwardly recessed with respect to the lateral surface 144 of base board unit 102.More specifically, this tabular passage 150b of the remnants of defeated troops is for inwardly recessed to define a pattern trench (cutout or groove), it comprises a curved lateral surface, wherein, this curved lateral surface is essentially the pattern of a concave surface, and for electrically being exposed to allow to be electrically connected to electromagnetic interference covering 124.Shown in Fig. 3 B, the last via pad 146b of the remnants of defeated troops, the lower through-hole pad 148b of the remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops comprise the lateral surface that is essentially the plane, and aim in fact or copline in the lateral surface 144 of base board unit 102, and the joint face S2 of grounding assembly 118b comprises the lateral surface of the concave surface in fact of the tabular passage 150b of the remnants of defeated troops, and the lateral surface that goes up the plane in fact of the 146b of the via pad remnants of defeated troops, the lower through-hole pad 148b of the remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops.Advantageously, the inwardly recessed tabular passage 150b of the remnants of defeated troops provide area bigger to joint face S2, therefore increased the reliability and the efficient that electrically connect, to reduce electromagnetic interference.Please still with reference to figure 3B, although electromagnetic interference covering 124 is inwardly recessed at one group of specific position, the formation of electromagnetic interference covering 124 has obtained being essentially the right angle lateral profile of the semiconductor device packages part 100 on plane.Concrete, electromagnetic interference covering 124 conformally covers joint face S2, joint face S2 comprise the tabular passage remnants of defeated troops 150 concave surface to the surface, make the sidepiece 128 of electromagnetic interference covering 124 inwardly recessed be adjacent to the tabular passage remnants of defeated troops 150.
Please refer to Fig. 3 C, grounding assembly 118b is formed by the remaining part of ground hole after one group of cutting technique, and comprises the 146b of the via pad remnants of defeated troops, the lower through-hole pad 148b of the remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops.In herein, grounding assembly 118b also comprises a filler (filler or plug member) 304.Filler 304 is filled the pattern trench that is defined by the tabular passage 150b of the remnants of defeated troops in fact.As described below, filler 304 forms remnants of defeated troops of a core component, and it fills the through-hole passage by ground hole defined.Carry out one group of cutting technique and can obtain a lateral surface of this filler 304, this lateral surface is essentially the plane and for electrically exposing, to allow to be electrically connected to electromagnetic interference covering 124.More specifically, the lateral surface of filler 304 be essentially aim at or copline in the lateral surface 144 of base board unit 102.Filler 304 can have material or another the suitable electrical conductive material that a metal or a metal alloy intersperse among wherein by a metal, a metal alloy, and be formed, and in this case, the joint face S2 of grounding assembly 118b comprises filler 304 lateral surface on plane in fact, and the lateral surface that goes up the plane in fact of the lateral surface on plane in fact of lateral surface, the lower through-hole pad 148b of the remnants of defeated troops on the plane in fact of the 146b of the via pad remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops.Advantageously, filler 304 contains an inclusion of electrically conducting, and therefore provides area sizable joint face S2, and has promoted the structural rigidity of grounding assembly 118b, strengthens reliability and the efficient that electrically connects by this, to reduce electromagnetic interference.Filler 304 also can be formed by non-electrical conductive material, and in this case, the joint face S2 of grounding assembly 118b comprises the 146b of the via pad remnants of defeated troops, the lower through-hole pad 148b of the remnants of defeated troops and the tabular passage 150b of the remnants of defeated troops lateral surface on plane in fact.Filler 30 also can contain the inclusion of a non-electrical conduction, can promote the structural rigidity of grounding assembly 118b, strengthens reliability and the efficient that electrically connects by this, to reduce electromagnetic interference.Please remain unchanged with reference to figure 3C, the formation of electromagnetic interference covering 124 has obtained being essentially the right angle lateral profile of the semiconductor device packages part 100 on plane, and it is essentially the plane, and inwardly recessed in sidepiece 128 in fact.
Though the grounding assembly 118b that is illustrated in Fig. 3 B and Fig. 3 C is the thickness that fully extends through base board unit 102, yet in other was implemented, the scope of grounding assembly 118b can change to some extent.Specifically, as described below, grounding assembly 118b can partly extend through the thickness of base board unit 102, for instance, may be embodied as remnants of defeated troops of an interior ground hole (internal grounding via) or a hidden ground hole (blind grounding via).
Fig. 4 A illustrates a profile of semiconductor device packaging part 400 according to another embodiment of the present invention.Some aspect of this semiconductor device packages part 400 is with a semiconductor device packages part 100 that is similar to earlier figures 1 to Fig. 3 C, so the part that repeats will no longer explain in this.
Please refer to Fig. 4 A, semiconductor device packages part 400 comprises grounding assembly 418a and the 418b that is arranged in fact around the base board unit 102.In this embodiment, the remnants of defeated troops of grounding assembly 418a and the hidden ground hole of 418b extend between the upper surface 104 and an electrical conducting shell 452 of base board unit 102.This electrical conducting shell 452 is set between the upper surface 104 and lower surface 106 of base board unit, and quilt is as an internal grounded layers.Specifically, each grounding assembly 418a and 418b comprise on one the 446a of the via pad remnants of defeated troops or 446b, the once 448a of the via pad remnants of defeated troops or 448b and a tabular passage 450a of the remnants of defeated troops or a 450b.Wherein, last via pad 446a of the remnants of defeated troops or 446b are provided with the upper surface 104 that is adjacent to base board unit 102; Lower through-hole pad 448a of the remnants of defeated troops or 448b be electrically connected to electrical conducting shell 452 and be arranged at base board unit 102 lower surface 106 the top and separate a certain distance; Tabular passage 450a of the remnants of defeated troops or 450b extend between the 446a of the via pad remnants of defeated troops or 446b and lower through-hole pad 448a of the remnants of defeated troops or the 448b.Though between upper surface 104 and lower surface 106 that grounding assembly 418a that this illustrated and 418b partly extend base board unit 102, yet in other was implemented, the scope of grounding assembly 418a and 418b can change.In this embodiment, grounding assembly 418a and 418b comprise joint face S1 ' and S2 ' respectively, and joint face S1 ' is abutted to lateral surface 142 and 144 with electrical respectively contact of S2 '.Advantageously, sizable joint face S1 ' of area and S2 ' can strengthen the reliability and the efficient of electric connection, to reduce electromagnetic interference.In some is implemented, the height H of grounding assembly 418a and 418b
2Can be slightly less than the thickness of base board unit 102, and about 0.1 millimeter to about 1.8 millimeters scope, for example be from about 0.2 millimeter to about 1 millimeter, or from about 0.3 millimeter to about 0.5 millimeter.The width W of grounding assembly 418a and 418b
2, promptly be abutted to a lateral extent of upper surface 104, can in about 75 microns to 275 microns scope, for example be from about 100 microns to about 250 microns, or from about 125 microns to about 225 microns.
Shown in Fig. 4 A, semiconductor device packages part 400 also comprises semiconductor device 408b.This semiconductor device 408b is the semiconductor chip that a setting is adjacent to the upper surface 104 of base board unit 102.In this embodiment, semiconductor device 408b is connected to base board unit 102 via a bond pads projection to cover crystal type (Flip Chip).Semiconductor device 408b also can other method, for example is electrically connected to base board unit 102 with bonding wire.
Fig. 4 B illustrates the profile of semiconductor device packaging part 460 according to another embodiment of the present invention.Some aspect of this semiconductor device packages part 460 is similar to the semiconductor device packages part 100 of earlier figures 1 to Fig. 3 C and the semiconductor device packages part 400 of Fig. 4 A, so similarly part will not illustrate at this one by one.
Please refer to Fig. 4 B, semiconductor device packages part 460 comprises grounding assembly 462a and the 462b that is arranged in fact around the base board unit 102.In this embodiment, the remnants of defeated troops of grounding assembly 462a and the hidden ground hole of 462b extend between the lower surface 106 and an electrical conducting shell 464 of base board unit 102.This electrical conducting shell 464 is set between the upper surface 104 and lower surface 106 of base board unit 102, and quilt is as an internal grounded layers.Specifically, each grounding assembly 462a and 462b comprise on one the 466a of the via pad remnants of defeated troops or 466b, the once 468a of the via pad remnants of defeated troops or 468b and a tabular passage 470a of the remnants of defeated troops or a 470b.Wherein, last via pad 466a of the remnants of defeated troops or 466b are electrically connected to electrical conducting shell 464, and be arranged at base board unit 102 upper surface 104 the below and separate a certain distance; Lower through-hole pad 468a of the remnants of defeated troops or 468b are provided with the lower surface 106 that is adjacent to base board unit 102; The tabular passage remnants of defeated troops 470 extend between the 466a of the via pad remnants of defeated troops or 466b and lower through-hole pad 468a of the remnants of defeated troops or the 468b.Advantageously, the position of grounding assembly 462a and 462b is lower than the upper surface 104 of base board unit 102 and has kept the useful zone of upper surface 104, it not only has the electromagnetic interference shielding function, and allows via the pin zone of reducing or minimizing semiconductor device packages part 460 to obtain the packaging part that an overall dimensions dwindles.Yet in other was implemented, the position of grounding assembly 462a and 462b and scope can change.In this embodiment, grounding assembly 462a and 462b comprise joint face S1 respectively " and S2 ", and joint face S1 " and S2 " electrically exposure is abutted to lateral surface 142 and 144 respectively.Advantageously, the sizable joint face S1 of area " and S2 " can strengthen the reliability and the efficient of electric connection, to reduce electromagnetic interference, reach the target that reduces overall package part size simultaneously.In some is implemented, the height H of grounding assembly 462a and 462b
BCan be slightly less than the thickness of base board unit 102, and about 0.1 millimeter to about 1.8 millimeters scope, for example be from about 0.2 millimeter to about 1 millimeter, or from about 0.3 millimeter to about 0.5 millimeter.The width W of grounding assembly 462a and 462b
B, promptly be abutted to a lateral extent of lower surface 106, can in about 75 microns to 275 microns scope, for example be from about 100 microns to about 250 microns, or from about 125 microns to about 225 microns.
The profile of the semiconductor device packaging part 480 that Fig. 4 C illustrates according to another embodiment of the present invention to be illustrated.Some aspect of this semiconductor device packages part 480 is similar to the semiconductor device packages part 100 of earlier figures 1 to Fig. 3 C, the semiconductor device packages part 400 of Fig. 4 A and the semiconductor device packages part 460 of Fig. 4 B, so similarly part will not illustrate at this one by one.
Please refer to Fig. 4 C, semiconductor device packages part 480 comprises grounding assembly 482a and the 482b that is arranged in fact around the base board unit 102.In this embodiment, grounding assembly 482a and 482b are implemented as the remnants of defeated troops that imbed ground hole or the remnants of defeated troops of inner ground hole, extend between the electrical conducting shell 484a and 484b of 106 of a pair of upper surface 104 that is arranged at base board unit 102 and lower surfaces, electrically conducting shell 484a and 484b are taken as and are a pair of internal grounded layers.Specifically, each grounding assembly 482a and 482b comprise on one the 486a of the via pad remnants of defeated troops or 486b, the once 488a of the via pad remnants of defeated troops or 488b and a tabular passage 490a of the remnants of defeated troops or a 490b.Wherein, last via pad 486a of the remnants of defeated troops or 486b are electrically connected to electrical conducting shell 484a, and be arranged at base board unit 102 upper surface 104 the below and separate a certain distance; Lower through-hole pad 488a of the remnants of defeated troops or 488b be electrically connected to electrical conducting shell 484b and be arranged at base board unit 102 lower surface 106 the top and separate a certain distance; Tabular passage 490a of the remnants of defeated troops or 490b extend between the 486a of the via pad remnants of defeated troops or 486b and lower through-hole pad 488a of the remnants of defeated troops or the 488b.Advantageously, the position that grounding assembly 482a and 482b are positioned at 106 of the upper surface 104 of base board unit 102 and lower surfaces has kept the useful zone of upper surface 104 and lower surface 106, it not only has the electromagnetic interference shielding function, and allows via the pin zone of reducing or minimizing semiconductor device packages part 480 to obtain the packaging part that an overall dimensions dwindles.Yet in other was implemented, the position of grounding assembly 482a and 482b and scope can change.In this embodiment, grounding assembly 482a and 482b comprise joint face S1 respectively " ' and S2 " ', and joint face S1 " ' and S2 " ' electrically exposure is abutted to lateral surface 142 and 144 respectively.Advantageously, the sizable joint face S1 of area " ' and S2 " ' can strengthen the reliability and the efficient of electric connection, to be used for reducing electromagnetic interference, reaches the target that reduces overall package part size simultaneously.In some is implemented, the height H of grounding assembly 482a and 482b
CCan be slightly less than the thickness of base board unit 102, and about 0.1 millimeter to about 1.6 millimeters scope, for example be from about 0.2 millimeter to about 0.8 millimeter, or from about 0.2 millimeter to about 0.4 millimeter.The width W of grounding assembly 482a and 482b
C, promptly be abutted to the lateral extent of electrical conducting shell 484a or 484b, can in about 75 microns to 275 microns scope, for example be from about 100 microns to about 250 microns, or from about 125 microns to about 225 microns.
Fig. 5 A to Fig. 5 E illustrates the method according to the formation semiconductor device packaging part of one embodiment of the invention.For simple expression, following technology explains according to the semiconductor device packages part 100 of Fig. 1 to Fig. 3 C.Yet, be noted that, this technology can for example be the semiconductor device packages part 400 of Fig. 4 A, the semiconductor device packages part 460 of Fig. 4 B and the semiconductor device packages part 480 of Fig. 4 C by similarly as carrying out to form other semiconductor device packages part.
At first please refer to Fig. 5 A and Fig. 5 B.One substrate 500 is provided, and in order to increase the manufacturing production capacity, substrate 500 comprises a plurality of base board units, comprises a base board unit 102 and an abuts substrate unit 102 ', can positively allow by this technology easily in a parallel manner or continuous mode carry out.Substrate 500 can be band shape (strip), and a plurality of base board units are arranged in a linear continuously.Perhaps, a plurality of base board units are arranged in array (array) form along two-dimensional directional.For simple expression, following technology mainly explains with reference to base board unit 102 and associated component thereof, yet these a little technologies can similarly be applied to other base board unit and associated component is carried out.
Shown in Fig. 5 A and Fig. 5 B, several ground hole settings be adjacent to each base board unit around.Specifically, ground hole 502a, 502b, 502c, 502d and 502e are provided with the side that is adjacent to base board unit 102.In this embodiment, each ground hole comprises via pad on, for example is to go up via pad 546a or 546b, via pad once, for example is via pad 548a or a 548b and a tabular passage, for example is a tabular passage 550a or a 550b.Ground hole 502a, 502b, 502c, 502d and 502e can several different methods formation arbitrarily, method for example comprises yellow light lithography, chemical etching, laser drill or machine drilling forming several openings, and the coating of these openings uses a metal, a metal alloy, a metal or metal alloy to intersperse among one of them material or other suitable electrical conductive material.The coating of these a little openings is formed on about 1 micron thickness to about 20 micrometer ranges, for example be from about 5 microns to about 20 microns, or from about 10 microns to about 15 microns, it extends across the vertical range of ground hole 502a, 502b, 502c, 502d and 502e in fact to stay through-hole passage simultaneously.In some is implemented, can impose in an electrical conductive material and the receiving through-hole passage to form the core component of electrical conduction, these a little core components are placed in these a little through-hole passage, and fill up this a little through-hole passage in fact.For instance, electrically conductive material can comprise electrically conduction adhesion of a metal, a scolder or, wherein, metal for example is a copper, scolder for example is that arbitrarily some have the solder metal alloy of fusing point between 90 ℃ to 450 ℃, and electrically to conduct adhesion for example be elargol, contain the epoxides of copper filler material or contain an electrical conductive fillers thing more arbitrarily intersperses among wherein resin.In other is implemented, can impose a non-electrical conductive material and be placed in the through-hole passage to form the core component of non-electrical conduction, these a little core components are placed in these a little through-hole passage, and fill up this a little through-hole passage in fact.For instance, non-electrical conductive material can comprise a welding shielding, a non-electrical conduction solid or other appropriate resin more arbitrarily, and wherein, non-electrical conduction solid for example is not contain the electrical epoxides of conduction filler in fact.Fill these a little through-hole passage and can allow several joint faces that generate obtain bigger zone, strengthen structural rigidity, therefore can strengthen reliability and the effect that electrically connects part, to reduce electromagnetic interference.Although ground hole 502a, 502b, 502c, 502d and 502e that this place illustrates fully extend between the upper surface 504 and a lower surface 524 of substrate 500, yet in other was implemented, the scope of ground hole 502a, 502b, 502c, 502d and 502e can change.For instance, at least one among ground hole 502a, 502b, 502c, 502d and the 502e can be embodied as a hidden ground hole or an inner ground hole.
In this embodiment, having a via pad of an annular shape, for example is to go up via pad 546a or 546b, and a tabular passage, for example be tabular passage 550a or 550b, define a through hole channel, the profile of this through hole channel is one cylindrical, comprises a circular in fact cross section.In general, the profile of a via pad and a through-hole passage can be more any shapes.For instance, a through-hole passage can have the column or the non-column of other type, and column can for example be an oval column, a square column or a rectangle column, and non-column can for example be a taper, a funnel-form or other tapered shape.Several lateral surface of one through-hole passage can be curved or coarse structures.Concerning some is implemented, a lateral extent W of each through-hole passage
3(being also sometimes referred to as is a clear size of opening) can be one about 50 microns to about 350 microns scope, for example be from about 100 microns to about 300 microns, or from about 150 microns to about 250 microns, and the lateral extent W of each via pad
4(being also sometimes referred to as is a via pad size) can be one about 150 microns to about 550 microns scope, for example be from about 200 microns to about 500 microns, or from about 250 microns to about 450 microns.If it is one irregularly shaped that a through-hole passage or a via pad have, then lateral extent W
3Or W
4Can for example be average corresponding to along several lateral extent of several right angle orientation.
For strengthening reliability and the effect that electrically connects part, to reduce electromagnetic interference, several ground hole settings are adjacent to all four sides of each base board unit, yet these a little ground holes also can be provided with a son group that is adjacent to four sides.Ground hole also can be provided with a son group that is adjacent to four all corners of each base board unit or four corners.Concerning some is implemented, the spacing L between the most adjoining ground hole of a base board unit
1(being also sometimes referred to as is a through-hole spacing) can be one about 0.1 millimeter to about 3 millimeters scope, for example be from about 0.2 millimeter to about 2 millimeters, or from about 0.5 millimeter to about 1.5 millimeters.Please refer to Fig. 5 B, dashed boundaries definition one " not entering " district (" keep-out " portion) in each base board unit, its inside is provided with several semiconductor devices.For the unfavorable impact in the technology of semiconductor device being reduced or minimizing, the ground hole of several base board units can be set, these a little ground holes and the exclusion area spacing L of being separated by
2(also can be described as sometimes be one do not enter the distance (" keep-out " distance)).Concerning some is implemented, spacing L
2Can be about 50 microns to about 300 microns scope, for example be from about 50 microns to about 200 microns, or from about 100 microns to 150 microns.Yet, the number of the ground hole in the substrate 500 with the position is set can be different from Fig. 5 A and Fig. 5 B and changes to some extent.Number row's ground holes also can be provided be adjacent to each base board unit around.The hidden ground hole or the case of inner ground hole that are arranged under the upper surface 504 do not need disposition interval L
2Specifically, hidden ground hole of this kind or inner ground hole can partly or wholly be arranged in the exclusion area and be arranged under the semiconductor device, the unfavorable impact in the technology of semiconductor device being reduced or minimize, and reach the target that reduces by an overall semiconductor device package size.
In case substrate 500 is provided, semiconductor device 108a, 108b and 108c are provided with and are adjacent to the upper surface 504 of substrate 500, and are electrically connected to base board unit 102.Specifically, to base board unit 102, and semiconductor device 108a and 108c surface fixing (surface mounted) is in base board unit 102 via bonding wire 112 wire bonds for semiconductor device 108b.Please refer to Fig. 5 A, the lower surface 524 of substrate 500 is provided with and is adjacent to an adhesive tape 506, and this adhesive tape 506 can be the adhesive tape of paste of a single or double.Advantageously, adhesive tape 506 is the base board unit of base board unit 102 and relative adjacency firmly, and allows to be provided with these assemblies that are adjacent to adhesive tape 506 and can carry out various continuous processings, and need not be inverted or transfer to another carrier.
Then, shown in Fig. 5 C, an adhesive material 514 is applied in the upper surface 504 of substrate 500, to cover or to encase ground hole 502a and 502b, semiconductor device 108a, 108b and 108c and bonding wire 112 in fact.For instance, adhesive material 514 can comprise a phenolic group resin (Novoac-based regin), an epoxy (epoxy-based region), a silicone (silicon-based resin) or other suitable encapsulant.Suitable filler also can comprise similarly being Powdered silicon dioxide.Adhesive material 514 some sealing technology arbitrarily applies, and for example is the compression sealing, injects sealing and change sealing.In case after being applied in, sclerosis or curing adhesive material 514 for example are via reducing temperature to a fusing point of adhesive material 514, forming a glue sealing structure 526 by this.In order continuously to help substrate 500 to find appropriate position in the cutting technique, can for example be to use laser labelling that telltale mark is formed among the glue sealing structure 526.Perhaps, in connection, telltale mark can be formed be adjacent to substrate 500 one around.
Then a upper surface 516 of glue sealing structure 526 is carried out cutting technique.The method of this kind cutting technique front end (" the front-side ") cutting technique of can being known as.Please refer to Fig. 5 C and Fig. 5 D, end-grain cutting is before this cut technology utilization one cast-cutting saw 518 and is carried out, and to form several joint-cuttings, comprises joint-cutting 520a and 520b.Specifically, joint-cutting 520a and 520b extend downwards, and fully by glue sealing structure 526 and substrate 500, and, by this glue sealing structure 526 and substrate 500 are divided into separative element partly by adhesive tape 506, comprise packaging body 114 and base board unit 102.The mode of this kind cutting technique complete cutting technique (" full-cut " singulation) of can being known as, this is to cut and can produce via a cutting technology because of glue sealing structure 526 and substrate 500 at each diverse location, and do not need a plurality of cutting techniques, for example be several hemisect technologies (" half-cut " singulation).Advantageously, use this complete cutting technique, but not use hemisect technology, can and reduce the required time of these a little technologies and increase the manufacturing production capacity via the number of times that reduces cutting technique.Also can make manufacturing cost reduce via a utilization rate that increases substrate 500, and also can increase by an overall productivity by the defective probability that miscut caused via reducing.Shown in Fig. 5 D, in complete cutting technique, adhesive tape 506 is base board unit 102 and the base board unit of packaging body 114 and relative adjacency and the safety of packaging body firmly.
Please continue D with reference to Fig. 5, cast-cutting saw 518 is for laterally being provided with and aiming at each ground hole in fact, thus, the joint-cutting that is produced can remove the volume or weight percentage of a certain degree of ground hole, for example is to volume or weight about 90%, from about 30% to 70% or from about 40% to about 60% from about 10%.If in core component was included in, the joint-cutting that is produced also can remove the volume or weight percentage of a certain degree of each core component, for example be to volume or weight about 90%, from about 30% to 70% or from about 40% to about 60% from about 10%.In the method, can form grounding assembly 118a and 118b, and grounding assembly 118a and 118b comprise joint face S1 and the S2 that is exposed to base board unit 102 surrounding environment respectively.In cutting technique, cast-cutting saw 518 to will definitely helping aim at via telltale mark, this telltale mark can provide cast-cutting saw 518 appropriate position when forming joint-cutting 520a and 520b.In some is implemented, the width C of each joint-cutting 520a and 520b
1(the complete cutting width of also can being known as, or fully Cutting Road) can one about 100 microns to about 600 microns scope, for example be from about 200 microns to about 400 microns, or from about 250 microns to about 350 microns.
Then please refer to Fig. 5 E, form the surface that an electromagnetic interference coating 522 is adjacent to several exposures, the contact surface of these exposures comprises the joint face S1 of outer surface, grounding assembly 118a and 118b of packaging body 114 and the lateral surface 142 and 144 of S2 and base board unit 102.Electromagnetic interference coating 522 can be utilized some coating techniques formation arbitrarily, for example is chemical vapour deposition (CVD), electroless-plating, plating, printing, spraying, sputter or vacuum moulding machine.For instance, electromagnetic interference coating 522 can comprise one by the formed individual layer of nickel, and it utilizes electroless-plating to form, and has one at least about five microns thickness, for example is from about 5 microns to about 50 microns, or from about 5 microns to about 10 microns.If electromagnetic interference coating 522 is the coating of multilayer, then different layers can utilize identical coating technique or different coating techniques to form.For instance, one can utilize electroless-plating to form by the formed internal layer of copper, and can utilize electroless-plating or electroplate in the two any one form by the formed skin of nickel.As another example, utilize any one in the two of sputter or electroless-plating to form by the formed internal layer of copper (can be taken as is a basic unit), and it has one at least about 1 micron thickness, for example be from about 1 micron to about 50 microns, or from 1 micron to about 10 microns, and utilize sputter to form by the formed skin of stainless steel, nickel or copper (can be taken as is an anti oxidation layer), and it has one and is no more than 1 micron thickness, for example be from about 0.01 micron to about 1 micron, or from about 0.01 micron to about 0.1 micron.In these examples, can carry out some pretreating process to help internal layer and outer field formation to the surface that electromagnetic interference coating 522 is imposed.The example of this type of pretreating process comprises the formation of a surface roughening and a crystal seed layer, and surface roughening for example is via due to chemical etching or the mechanical fretting corrosion.Utilize a for example pick-place techniques, base board unit 102 and associated component thereof are separated from adhesive tape 506, and form the semiconductor device packages part 100 that includes ELECTROMAGNETIC OBSCURANT spare 124.
Fig. 6 illustrates the method that forms semiconductor device packaging part according to another embodiment of the present invention.Be simple expression, following technology explains with reference to the semiconductor device packages part 400 of figure 4A.Yet, be noted that, this technology can for example be the semiconductor device packages part 100 of Fig. 1 to Fig. 3 C, the semiconductor device packages part 460 of Fig. 4 B and the semiconductor device packages part 480 of Fig. 4 C by similarly as carrying out to form other semiconductor device packages part.Some aspect of technology also can a mode that be similar to aforesaid Fig. 5 A to Fig. 5 E be implemented, so similarly part will not illustrate at this one by one.
Please refer to Fig. 6, the adhesive material 614 of sclerosis is provided with substrate 600 and is adjacent to an adhesive tape 606, and this adhesive tape 606 can be implemented as the adhesive tape of paste of a single or double.Then, the upper surface 616 of adhesive material 614 to sclerosis carries out cutting technique.As shown in Figure 6, this cutting technique utilizes a cast-cutting saw 618 to carry out, to form joint-cutting 620a and 620b.Wherein, joint-cutting 620a and 620b down extend, and pass through the adhesive material 614 and the substrate 600 of sclerosis fully, and partly by adhesive tape 606, so the adhesive material 614 and the substrate 600 of sclerosis are divided into several separative elements again, and separative element comprises packaging body 114 and base board unit 102.Specifically, cast-cutting saw 618 laterally is provided with and aims at each ground hole in fact, and thus, the joint-cutting of gained is divided into two grounding assemblies again with ground hole, and this two grounding assembly is separated from one another, and setting is adjacent to the opposing substrates unit.If in core component was included in, then the joint-cutting of a gained also can be divided into two fill assemblies again with each core component.In this way, form grounding assembly 418a and 418b, and grounding assembly 418a and 418b comprise joint face S1 ' and S2 ' respectively, this joint face S1 ' and S2 ' around be contacted with base board unit 102 around.Advantageously, the cutting technique mode that is illustrated in Fig. 6 is via the number of times that further reduces cutting technique and reduce the required time of those technologies, makes production capacity to increase; Via a utilization rate that further increases substrate 600 to reduce manufacturing cost; And increase by an overall productivity via the defective probability that further reduces miscut and caused.Concerning some is implemented, a clear size of opening W of each ground hole
5Can in about 100 microns to 700 a microns scope, for example be from about 200 microns to 600 microns, or from about 300 microns to 500 microns, and a via pad size W of each ground hole
6Can one about 300 microns to about 1100 microns scope, for example be from about 400 microns to about 1000 microns, or from about 500 microns to about 900 microns.The width C of each joint-cutting 620a and 620b
2With the width C among Fig. 5 D of above-mentioned reference
1Can be essentially identical, and width C
2Can one about 100 microns to about 600 microns scope, for example be from about 200 microns to about 400 microns, or from about 250 microns to about 350 microns.Yet in other is implemented, width C
2Can change, and can be with respect to the clear size of opening W of a ground hole
5Or the via pad size W of a ground hole
6Adjust, be divided into several grounding assemblies again to allow it.For instance, general width C 2 can be represented as: C2＜W
5＜W
6
In sum, though the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention is in the spirit and scope that do not break away from claims of the present invention and defined, when being used for a variety of modifications and variations.In addition, more correction can be brought enforcement, in order to adapt to special circumstances of the present invention, material, material composition, method or process goal, spirit and scope.In the scope that all this type of correction all is covered by claims to be defined.Especially describe out in this disclosed method with the contrast special process, these technologies can with merged, segmentation is opened or rearrange and form a same procedure and do not break away from instruction of the present invention.Therefore, unless this special pointing out, the arrangement of technology or classification do not limit the present invention.
Claims (20)
1. semiconductor device packages part comprises:
One base board unit comprises
One upper surface,
A lower surface,
One lateral surface, be provided be adjacent to this base board unit one around, and fully extend between this lower surface of this upper surface of this base board unit and this base board unit, and
One grounding assembly, setting is adjacent to around being somebody's turn to do of this base board unit, and extend to small part between this lower surface of this upper surface of this base board unit and this base board unit, this grounding assembly comprises a sunk part, and this sunk part setting is adjacent to this lateral surface of this base board unit;
The semiconductor device is provided with and is adjacent to this upper surface of this base board unit, and is electrically connected to this base board unit;
One packaging body is provided with and is adjacent to this upper surface of this base board unit, and covers this semiconductor device, and this packaging body comprises several outer surfaces, and those outer surfaces comprise a lateral surface; And
One electromagnetic interference covering, setting is adjacent to this lateral surface of those outer surfaces and this base board unit of this packaging body, and this electromagnetic interference covering is electrically connected to this grounding assembly, and inside recessed adjoining farmland neighbour is connected to this sunk part of this grounding assembly.
2. semiconductor device packages part as claimed in claim 1, wherein this grounding assembly comprises tabular channel remnants of defeated troops, these tabular passage remnants of defeated troops are corresponding to this sunk part of this grounding assembly, and this electromagnetic interference covering conformally covers this tabular passage remnants of defeated troops, makes the inside recessed adjoining farmland neighbour of this electromagnetic interference covering be connected to this tabular passage remnants of defeated troops.
3. semiconductor device packages part as claimed in claim 2, wherein these tabular passage remnants of defeated troops comprise a joint face, for inwardly recessed, and this electromagnetic interference covering conformally covers this joint face of these tabular passage remnants of defeated troops to this joint face with respect to this lateral surface of this base board unit.
4. semiconductor device packages part as claimed in claim 1, wherein this grounding assembly partly extends between this lower surface of this upper surface of this base board unit and this base board unit, and a height of this grounding assembly is less than a thickness of this base board unit.
5. semiconductor device packages part as claimed in claim 4, wherein this base board unit comprises a pair of internal grounded layers, and this grounding assembly extends this between the internal grounded layers.
6. semiconductor device packages part as claimed in claim 1, wherein this lateral surface of this base board unit is essentially a plane, and this lateral surface of this packaging body is aimed at this lateral surface of this base board unit in fact.
7. semiconductor device packages part as claimed in claim 1, wherein this electromagnetic interference covering comprises a lower end of side direction part and this side direction part, this side direction part is extended along this lateral surface of this base board unit, and this lower end of this side direction part is in fact in alignment with this lower surface of this base board unit.
8. semiconductor device packages part comprises:
One base board unit comprises
One first surface,
One second apparent surface, and
One grounding assembly, extend to small part between this second apparent surface of this first surface of this base board unit and this base board unit, this grounding assembly comprises the tabular channel remnants of defeated troops and a filler, these tabular passage remnants of defeated troops are inwardly recessed holding this filler, these tabular passage remnants of defeated troops and this filler define be provided be adjacent to this base board unit one around a lateral surface of this grounding assembly;
The semiconductor device is provided with and is adjacent to this first surface of this base board unit, and is electrically connected to this base board unit;
One packaging body is provided with and is adjacent to this first surface of this base board unit, and covers this semiconductor device, and this packaging body comprises several outer surfaces; And
One electromagnetic interference covering is provided with and is adjacent to those outer surfaces of this packaging body, and this lateral surface that is electrically connected to this grounding assembly,
Wherein a lateral profile of this semiconductor device packages part is essentially a plane, and is essentially the right angle with respect to this second apparent surface of this base board unit.
9. semiconductor device packages part as claimed in claim 8, wherein this lateral surface of grounding assembly is essentially the plane.
10. semiconductor device packages part as claimed in claim 9, wherein this filler has electrical conducting power.
11. semiconductor device packages part as claimed in claim 9, wherein this base board unit more comprises a lateral surface, this lateral surface fully extends between this second apparent surface of this first surface of this base board unit and this base board unit, this lateral surface of this base board unit is essentially the plane, and this second apparent surface with respect to this base board unit is the right angle in fact, and this lateral surface of this grounding assembly contacts this lateral surface that is adjacent to this base board unit electrically.
12. semiconductor device packages part as claimed in claim 11, wherein those outer surfaces of this packaging body comprise a lateral surface, and this lateral surface of this packaging body is aimed at this lateral surface of this base board unit in fact.
13. semiconductor device packages part as claimed in claim 8, wherein this grounding assembly more comprises the one first via pad remnants of defeated troops and the one second via pad remnants of defeated troops, and these tabular passage remnants of defeated troops extend between these first via pad remnants of defeated troops and this second via pad remnants of defeated troops.
14. semiconductor device packages part as claimed in claim 13, wherein this base board unit comprises that a more electrical conducting shell is arranged between this second apparent surface of this first surface of this base board unit and this base board unit, these first via pad remnants of defeated troops are provided with this electrical conducting shell that is adjacent to this base board unit, and these second via pad remnants of defeated troops are provided with this second apparent surface who is adjacent to this base board unit.
15. semiconductor device packages part as claimed in claim 8, wherein this electromagnetic interference covering is a conformal covering, and this conformal covering comprises a ground floor and a second layer, and this second layer setting is adjacent to this ground floor.
16. semiconductor device packages part as claimed in claim 15, wherein this ground floor and this second layer comprise different electrically conductive materials.
17. the formation method of a semiconductor device packages part comprises:
A substrate that comprises a ground hole and a core component is provided, this ground hole extends between a lower surface of a upper surface of this substrate and this substrate at least in part, this ground hole defines a through hole channel, and this through hole channel is filled by this core component in fact;
Electrically connect semiconductor device this upper surface to this substrate;
Impose an adhesive material covers this semiconductor device with formation in this upper surface of this substrate a glue sealing structure;
Form several joint-cuttings, those joint-cuttings are fully by this glue sealing structure and this substrate, and those joint-cuttings are in alignment with this substrate, so: (a) this substrate is cut apart to form a base board unit of cutting apart again; (b) this glue sealing structure is cut apart form to be provided with again and is adjacent to the packaging body that one of this base board unit is cut apart, and this packaging body comprises several outer surfaces; And (c) remnants of defeated troops of the remnants of defeated troops of this ground hole and this core component corresponding be provided be adjacent to this base board unit one around a grounding assembly, this grounding assembly comprises a joint face that exposes; And
After forming those joint-cuttings, impose an electromagnetic interference coating in this joint face of those outer surfaces of this packaging body and this grounding assembly to form an electromagnetic interference covering.
18. semiconductor device packages part as claimed in claim 17, wherein provide this substrate to comprise to impose an electrical conductive material to through-hole passage to form this core component.
19. semiconductor device packages part as claimed in claim 17 wherein forms those joint-cuttings, makes this joint face be essentially the plane.
20. this semiconductor device packages part as claimed in claim 17, wherein this base board unit comprises a lateral surface, those outer surfaces of this packaging body comprise a lateral surface, and form those joint-cuttings and make this lateral surface of this packaging body in fact in alignment with this lateral surface of this base board unit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/770,645 US8212339B2 (en) | 2008-02-05 | 2010-04-29 | Semiconductor device packages with electromagnetic interference shielding |
| US12/770,645 | 2010-04-29 |
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|---|---|
| CN102064141A true CN102064141A (en) | 2011-05-18 |
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| TW (1) | TWI420644B (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102064141B (en) | 2012-07-04 |
| TW201138050A (en) | 2011-11-01 |
| TWI420644B (en) | 2013-12-21 |
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