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CN102956575A - 封装结构及制造方法 - Google Patents

封装结构及制造方法 Download PDF

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Publication number
CN102956575A
CN102956575A CN2011102473294A CN201110247329A CN102956575A CN 102956575 A CN102956575 A CN 102956575A CN 2011102473294 A CN2011102473294 A CN 2011102473294A CN 201110247329 A CN201110247329 A CN 201110247329A CN 102956575 A CN102956575 A CN 102956575A
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electronic component
substrate
metallic supports
encapsulating structure
height
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肖俊义
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
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Priority to CN2011102473294A priority Critical patent/CN102956575A/zh
Priority to TW100130971A priority patent/TW201310589A/zh
Priority to US13/280,359 priority patent/US20130048351A1/en
Publication of CN102956575A publication Critical patent/CN102956575A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
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    • Y10T29/00—Metal working
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Abstract

一种封装结构，包括基板、电子元件及封胶体，所述基板设有多个焊盘以电连接所述电子元件。所述焊盘与所述电子元件之间设置有金属支撑件，所述电子元件与所述基板之间形成高度为所述焊盘的高度与所述金属支撑件的高度叠加的间隙。所述封胶体包覆于所述电子元件与所述基板之上并得以充分填充所述间隙。本发明提供的封装结构可以避免电子元件与基板之间形成空洞或气洞，提高产品的可靠度。本发明提供的封装结构制造方法，制程简单，制造成本低。

Description

封装结构及制造方法
技术领域
本发明涉及封装结构及制造方法，尤其涉及包括金属支撑件的封装结构及制造方法。
背景技术
大尺寸电子元件，如过滤器、晶振是封装模组中常用的电子元件。所述电子元件通常采用陶瓷封装，当采用表面贴装技术(Surface Mounting Technology，SMT)将所述电子元件固定于基板时，锡膏融化后电子元件底部与基板之间空隙大约在10微米左右。在注塑成型时，由于电子元件与基板之间的间隙非常小，封胶体不易流入所述空隙，从而使电子元件的底部容易形成空洞或气洞。因为空洞或气洞的存在，产品在回流焊时容易发生短路失效。同时，空洞或气洞会发生热胀冷缩，使产品出现裂缝，降低了产品的可靠度。
发明内容
有鉴于此，需提供一种封装结构及制造方法，可避免电子元件与基板之间形成空洞或气洞，提高产品的可靠度。
本发明提供的封装结构包括基板、电子元件及封胶体，所述基板设有多个焊盘以电连接所述电子元件。所述焊盘与所述电子元件之间设置有金属支撑件，所述电子元件与所述基板之间形成高度为所述焊盘之高度与所述金属支撑件之高度叠加的间隙。所述封胶体包覆于所述电子元件与所述基板之上并得以充分填充所述间隙。
优选地，所述金属支撑件为铜凸柱。
优选地，所述金属支撑件为金凸柱。
优选地，所述金属支撑件为铝凸柱。
优选地，所述金属支撑件的高度为30～70微米。
优选地，所述金属支撑件表面包覆锡膏，所述金属支撑件与所述锡膏结合形成多个焊点以支撑并固定所述电子元件。
本发明提供的封装结构的制造方法包括：在基板上形成多个焊盘；将多个金属支撑件分别叠置于所述焊盘；将电子元件设于所述金属支撑件之上，从而在所述电子元件与所述基板之间形成高度为所述焊盘之高度与所述金属支撑件之高度叠加的间隙；及利用注胶成型技术固定所述电子元件于所述基板以形成封胶体，所述封胶体得以充分填充所述间隙。
优选地，所述封装结构的制造方法还包括在所述金属支撑件表面包覆锡膏，所述金属支撑件与所述锡膏结合形成多个焊点以支撑并固定所述电子元件。
优选地，所述金属支撑件通过半导体绑定技术形成于所述基板之上。
本发明提供的封装结构，在电子元件与基板之间设置金属支撑件，使电子元件与基板之间形成高度为焊盘之高度与金属支撑件之高度叠加的间隙，所述间隙不会因为电子元件在表面贴装时锡膏融化而改变。在注胶成型时，封胶体可以充分填充所述间隙，从而避免电子元件与基板之间形成空洞或气洞，提高产品的可靠度。本发明提供的封装结构制造方法，制程简单，制造成本低。
附图说明
图1是本发明一具体实施方式的封装结构截面示意图。
图2是将金属支撑件固定于基板的焊盘的示意图。
图3是于金属支撑件的表面印刷锡膏的示意图。
图4是将电子元件固定于金属支撑件之上的示意图。
主要元件符号说明
封装结构        100
基板            10
焊盘            11
金属支撑件      20
电子元件        30
封胶体          40
固定间隙        50
锡膏            60
焊点        70
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
请参照图1。本发明提供的封装结构100包括基板10、多个金属支撑件20、电子元件30及封胶体40。基板10包括多个焊盘11以电连接所述电子元件30。所述焊盘11与所述电子元件30之间设置有金属支撑件20，所述电子元件30与所述基板10之间形成高度h为所述焊盘11之高度h1与所述金属支撑件20之高度h2叠加的间隙50，如图4所示。封胶体40包覆于所述电子元件30与所述基板10之上并得以充分填充所述间隙50。本实施方式中，封胶体40的材质为环氧树脂。
由于金属支撑件20支撑电子元件30，使得电子元件30与基板10之间形成间隙50。当电子元件30通过表面贴装技术(SMT)固定于基板10时，所述间隙50不会因为锡膏融化而改变。在注塑成型时，环氧树脂会充分填充所述间隙50，从而避免了电子元件30与基板10之间形成空洞或气洞，大大提高了产品的性能。本实施方式中，金属支撑件20的高度为30～70微米，所述高度可保证环氧树脂充分流入间隙50，以避免电子元件30与基板10之间形成空洞或气洞。
本实施方式中，金属支撑件20为铜凸柱，当然，在其它实施方式中，金属支撑件20亦可以为金凸柱或铝凸柱。
作为本发明的进一步改进，所述金属支撑件20的表面包覆锡膏60，金属支撑件20与锡膏60结合形成焊点70以支撑并固定电子元件30。当环氧树脂填充于固定间隙50时，锡膏60可确保电子元件30与基板10之间充分电连接。
本发明的封装结构制造方法包括如下步骤。
在基板10上形成多个焊盘11以电连接电子元件30。
请参阅图2，将多个金属支撑件20分别迭置于基板10的焊盘11。本实施方式中，金属支撑件20利用半导体绑定技术形成于基板10，可大大提高生产效率。金属支撑件20的高度为30～70微米，所述高度可保证环氧树脂充分流入间隙50，以避免电子元件30与基板10之间形成空洞或气洞。
请参阅图3，在金属支撑件20的表面印刷锡膏60使金属支撑件20与锡膏60结合形成焊点70。金属支撑件20与锡膏60的结合可有效支撑电子元件30，使电子元件30与基板10之间保持固定间隙50。
请参阅图4，将电子元件30利用表面贴装技术(SMT)固定于所述金属支撑件20之上，从而在所述电子元件30与所述基板10之间形成高度h为所述焊盘11的高度h1与所述金属支撑件20的高度h2叠加的间隙50。本实施方式，电子元件30固定于金属支撑件20与锡膏60结合形成的焊点70之上。由于金属支撑件20的设置，当锡膏60融化后，电子元件30与基板10之间的间隙50的高度h保持不变。
请参阅图1，利用注胶成型技术固定所述电子元件30以形成封胶体40。在成型过程中，环氧树脂充分填充电子元件30与基板10之间形成的间隙50，可有效避免电子元件30与基板10之间形成空洞或气洞。
本发明的内埋封装结构制造方法利用半导体绑定技术将金属支撑件20形成于基板10，表面贴装技术(SMT)及注胶成型技术将电子元件30固定于基板并内埋于封胶体内，制程简单，制造成本低。

Claims (9)

1.一种封装结构，包括基板、电子元件及封胶体，所述基板设有多个焊盘以电连接所述电子元件，其特征在于，所述焊盘与所述电子元件之间设置有金属支撑件，所述电子元件与所述基板之间形成高度为所述焊盘之高度与所述金属支撑件之高度叠加的间隙，所述封胶体包覆于所述电子元件与所述基板之上并得以充分填充所述间隙。
2.如权利要求1所述的封装结构，其特征在于，所述金属支撑件为铜凸柱。
3.如权利要求1所述的封装结构，其特征在于，所述金属支撑件为金凸柱。
4.如权利要求1所述的封装结构，其特征在于，所述金属支撑件为铝凸柱。
5.如权利要求1所述的封装结构，其特征在于，所述金属支撑件的高度为30～70微米。
6.如权利要求1所述的封装结构，其特征在于，所述金属支撑件表面包覆锡膏，所述金属支撑件与所述锡膏结合形成多个焊点以支撑并固定所述电子元件。
7.一种封装结构的制造方法，其特征在于，包括：
在基板上形成多个焊盘；
将多个金属支撑件分别叠置于所述焊盘；
将电子元件设于所述金属支撑件之上，从而在所述电子元件与所述基板之间形成高度为所述焊盘置高度与所述金属支撑件之高度叠加的间隙；及
利用注胶成型技术固定所述电子元件于所述基板以形成封胶体，所述封胶体得以充分填充所述间隙。
8.如权利要求7所述的封装结构的制造方法，其特征在于，还包括在所述金属支撑件表面包覆锡膏，所述金属支撑件与所述锡膏结合形成多个焊点以支撑并固定所述电子元件。
9.如权利要求7所述的封装结构的制造方法，其特征在于，所述金属支撑件通过半导体绑定技术形成于所述基板之上。
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109587948A (zh) * 2018-12-28 2019-04-05 维沃移动通信有限公司 一种电路板装置及其加工方法
CN110752191A (zh) * 2019-10-29 2020-02-04 维沃移动通信有限公司 器件封装模块、器件封装模块的制备方法及电子设备
CN113498314A (zh) * 2020-03-20 2021-10-12 天芯互联科技有限公司 线路板上电子元器件的贴装方法
CN114158213A (zh) * 2021-11-30 2022-03-08 业成科技（成都）有限公司 粘合物、粘合方法及电子产品
CN114390805A (zh) * 2022-01-26 2022-04-22 深圳市潜力创新科技有限公司 一种双层电路板焊接方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214642B1 (en) * 1997-11-21 2001-04-10 Institute Of Materials Research And Engineering Area array stud bump flip chip device and assembly process
CN101901858A (zh) * 2004-04-28 2010-12-01 沃提科尔公司 垂直结构半导体器件
TW201101441A (en) * 2009-06-23 2011-01-01 Phoenix Prec Technology Corp Package substrate and base therefor and fabrication method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6214642B1 (en) * 1997-11-21 2001-04-10 Institute Of Materials Research And Engineering Area array stud bump flip chip device and assembly process
CN101901858A (zh) * 2004-04-28 2010-12-01 沃提科尔公司 垂直结构半导体器件
TW201101441A (en) * 2009-06-23 2011-01-01 Phoenix Prec Technology Corp Package substrate and base therefor and fabrication method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109587948A (zh) * 2018-12-28 2019-04-05 维沃移动通信有限公司 一种电路板装置及其加工方法
CN109587948B (zh) * 2018-12-28 2021-02-02 维沃移动通信有限公司 一种电路板装置及其加工方法
CN110752191A (zh) * 2019-10-29 2020-02-04 维沃移动通信有限公司 器件封装模块、器件封装模块的制备方法及电子设备
CN113498314A (zh) * 2020-03-20 2021-10-12 天芯互联科技有限公司 线路板上电子元器件的贴装方法
CN114158213A (zh) * 2021-11-30 2022-03-08 业成科技（成都）有限公司 粘合物、粘合方法及电子产品
CN114158213B (zh) * 2021-11-30 2023-09-22 业成科技（成都）有限公司 粘合物、粘合方法及电子产品
CN114390805A (zh) * 2022-01-26 2022-04-22 深圳市潜力创新科技有限公司 一种双层电路板焊接方法

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