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CN102810568A - Stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) device and preparation method - Google Patents

Stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) device and preparation method Download PDF

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CN102810568A
CN102810568A CN2012102444008A CN201210244400A CN102810568A CN 102810568 A CN102810568 A CN 102810568A CN 2012102444008 A CN2012102444008 A CN 2012102444008A CN 201210244400 A CN201210244400 A CN 201210244400A CN 102810568 A CN102810568 A CN 102810568A
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CN102810568B (en
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张鹤鸣
王海栋
胡辉勇
宋建军
宣荣喜
王斌
周春宇
郝跃
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Xidian University
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Abstract

The invention discloses a stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) integration device prepared by a micrometer level process and a preparation method. The method is characterized in that a PMOS device is formed through an epitaxial material preparation step, an isolator preparation step, a drain connecting region preparation step and a PMOS forming step; and finally a PMOS integration circuit with the length of a conducting channel of 22 to 45nm is formed through a step for forming the PMOS integration circuit. By utilizing the characteristic that the hole mobility of the stress Si is higher than that of relaxation Si, on the platform of a micrometer-level Si integration circuit processing technique, the stress Si vertical-channel PMOS integration device and the circuit with excellent performance are manufactured under low temperature.

Description

A kind of strain Si vertical-channel PMOS integrated device and preparation method
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of strain Si vertical-channel PMOS integrated device and preparation method.
Background technology
The modern technologies revolution is claimed in new technology revolution again, also has the people that it is called the third technical revolution after steam engine, electric power.With microelectric technique, electronic computer, laser, optical fiber communication, satellite communication and remote sensing technology is the frontier technology that the information technology of main contents becomes new technology revolution.New technology revolution results from mid-term 1940's; Its at first developed capitalist countries's rise in the west is progressively to other countries and regional radiation, until have swepting the globe; It is that the formation that is accompanied by contemporary science and technology grows up, and has expanded to various fields in science and technology.
Information technology is the core technology of scientific and technological revolution, and microelectric technique is the basis of information technology.The historical facts of development in science and technology show, the integrated circuit that occurred in 1958 is one of invention of tool influence of 20th century.The microelectronics that is born based on this invention has become the basis of existing modern technologies, quickens changing more educated, the IT application process of human society, has also changed the human mode of thinking simultaneously.It not only is the human instrument that strong nature remodeling is provided, but also has opened up a wide development space.
Industry development has an immense impact on to semiconductor " Moore's Law " pointed out: the transistor size on the IC chip, increased by 1 times in per approximately 18 months, and performance also promotes 1 times.Over more than 40 year, the world semiconductor industry constantly advances according to this law all the time.
Along with reducing of device size, especially progressively get into after the nanoscale, the development of microelectric technique more and more approaches the limit of material, technology, device, is faced with great challenge.After device feature size narrows down to 65 nanometers; See from device angles; Problems such as the influence of the short channel effect in the nanoscale devices, high-field effect, quantum effect, parasitic parameter, technological parameter fluctuation are more and more outstanding to Effect on Performance such as device leakage electric current, subthreshold characteristic, ON state/off-state currents, and the contradiction of circuit speed and power consumption will be more serious also.Along with integrated level and operating frequency increase, power dissipation density increases, and causes chip overheating, can cause circuit malfunction.On the other hand, behind the entering nanoscale, interconnection resistance and interconnection capacitance are not only more obvious to the influence of circuit speed, and can exert an influence to signal integrity, become the key factor that influences the final performance of circuit gradually.
Reducing of characteristic size needs the process equipment of a new generation, because still there is not to solve preferably at present the technology of on existing equipment, making chip of future generation, therefore can only improve technology level through the renewal of process equipment.Through accumulation for many years; The equipment of the whole world in microelectronic industry surpasses trillion dollars with technology input at present, if just obtain the lifting of technology through the update of equipment, with per 18 months superseded generation equipment; This will cause the huge resource and the waste of the energy; Cause production cost to rise, therefore, this present situation has seriously restricted the development of semicon industry.
Summary of the invention
The object of the present invention is to provide the existing micro process of a kind of usefulness to prepare the preparation method of strain Si vertical-channel PMOS device and integrated circuit; To be implemented under the condition that does not change existing equipment and increase cost, preparing conducting channel is strain Si vertical-channel PMOS device and the integrated circuit of 22～45nm.
The object of the present invention is to provide a kind of strain Si vertical-channel PMOS device, said device conducting channel is back type, and channel direction is vertical with substrate surface.
Another object of the present invention is to provide a kind of preparation method of strain Si vertical-channel PMOS integrated device, the conducting channel that the vertical PMOS device of the strain Si in the said integrated device has back type; Said preparation method comprises the steps:
The first step, to choose doping content be 10 15～10 16Cm -3N type Si substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, seven layer materials of on substrate, growing continuously: ground floor is that thickness is the P type Si epitaxial loayer of 200～400nm, and doping content is 10 15～10 16Cm -3The second layer is that thickness is the P type relaxation SiGe layer of 1～1.5 μ m, and doping content is 5～10 * 10 18Cm -3, the Ge content gradually variational, the Ge component at P type relaxation SiGe layer and P type Si epitaxial layer interface place is 0%, P type relaxation SiGe layer top Ge component is 15～25%; The 3rd layer is that thickness is the fixing SiGe layer of Ge component of P type of 200～300nm, and the Ge component is 15～25%, and consistent with the Ge component at gradual change SiGe layer top, doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; The 4th layer is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer; Layer 5 be thickness be the N type strain Si layer of 22～45nm as channel region, doping content is 5 * 10 16～5 * 10 17Cm -3Layer 6 is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer; Layer 7 is that thickness is the P type of the 300～400nm fixedly SiGe layer of Ge component that mixes, and the Ge component is 15～25%, and its doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region;
The 3rd step, photoetching deep trench isolation district utilize dry etch process, etch the deep trouth that the degree of depth is 2～3 μ m in isolated area;
The 4th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one SiO 2Layer all covers the deep trouth inner surface, and deposit polysilicon (Poly-Si) forms deep trench isolation with filling up in the deep trouth again;
The 5th step, photoetching shallow trench isolation region utilize dry etch process, above deep trouth, leak isolated area with the source and etch the shallow slot that the degree of depth is 0.4～0.5 μ m; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2At last,, remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 6th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away part Si N and SiO 2Form and leak the bonding pad window; Utilize dry etch process, etching the degree of depth is the leakage groove of 0.45～0.55 μ m; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at the substrate surface SiO that grows 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 5 * 10 in this groove 19～5 * 10 20Cm -3Polysilicon, this groove is filled up, remove the unnecessary polysilicon in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
The 7th goes on foot, etches away surface unnecessary SiN and SiO 2The barrier layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away SiN and SiO 2Form the grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.45～0.55 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 5 * 10 in substrate surface deposit doping content 19～5 * 10 20Cm -3N type polysilicon, and gate groove filled up, remove the surface portion polysilicon, form grid;
The 8th step, the unnecessary SiO of removal substrate surface 2, SiN and SiO 2The barrier layer forms the source region, finally forms the PMOS device;
The 9th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at the substrate surface SiO that grows 2The layer, and on grid, source and drain region lithography fair lead;
The tenth step, metallization, the photoetching lead-in wire forms drain electrode, source electrode and gate metal lead-in wire, and constituting conducting channel length is the PMOS integrated circuit of 22～45nm.
Another object of the present invention is to provide a kind of preparation method of strain Si vertical-channel PMOS integrated circuit, the conducting channel that the vertical PMOS device of the strain Si in the said integrated circuit has back type; Said preparation method comprises the steps:
Step 1, the epitaxial material preparation process:
(1a) choosing doping content is 5 * 10 16Cm -3About N type Si substrate slice;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type Si epitaxial loayer of 300nm on substrate, and doping content is 5 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe resilient coating of 1.25 μ m on the Si epitaxial loayer, the Ge content gradually variational, and the Ge component is distributed as from the bottom to top from 0% to 25%, and doping content is 10 19Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe epitaxial loayer growth one layer thickness be the P type SiGe layer of 250nm as the drain region, doping content is 5 * 10 20Cm -3, the Ge component is 25%;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer of 3nm on the SiGe epitaxial loayer, and doping content is 5 * 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the N type strain Si layer of 22nm as channel region, doping content is 5 * 10 17Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer of 3nm on the Si strained layer, and doping content is 5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the P type SiGe layer of 350nm as the source region, doping content is 5 * 10 20Cm -3, the Ge component is 25%;
Step 2, the isolation preparation step:
(2a) photoetching deep trench isolation district utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;
(2b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO 2Layer all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill polysilicon, form deep trench isolation at 800 ℃;
(2d) the photoetching shallow trench isolation region utilizes dry etch process, above deep trouth, leaks isolated area with the source and etches the shallow slot that the degree of depth is 0.45 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 3, leak the bonding pad preparation process:
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) etch away SiN and SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.5 μ m;
(3d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit concentration is 5 * 10 20Cm -3Polysilicon, fill up groove, remove the unnecessary polysilicon in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
Step 4, PMOS forms step:
(4a) etch away surface unnecessary SiN and SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(4c) etch away SiN and SiO 2Form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface deposition thickness 2Layer is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3Polysilicon, and gate groove filled up, remove the surface portion polysilicon, form grid;
(4g) remove the unnecessary SiO of substrate surface 2With the SiN barrier layer, form the source region, finally form the PMOS device;
Step 5 constitutes PMOS integrated circuit step:
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, and constituting conducting channel length is the PMOS integrated circuit of 22nm.
The present invention has following advantage:
1. the strain Si vertical-channel PMOS device channel direction of the present invention's preparation is the vertical direction of strain Si layer; Then channel length is strain Si layer thickness; This thickness can be controlled through Si material growth technique, thereby has avoided the small size photoetching, has reduced the input of lithographic equipment;
In the Si vertical-channel PMOS device of the present invention preparation because the fixing component of SiGe material growth one deck graded component regrowth earlier can reduce dislocation effectively, so the defect concentration in the Si material is low, the strain Si PMOS device performance of preparation is stablized;
3. the present invention utilizes the anisotropy of material strain; Tensile strain Si layer vertical direction lattice compresses, and causes the division of valence-band level, has reduced the effective mass and the scattering probability in hole; Improve mobility, thereby improved the current driving ability and the frequency characteristic of PMOS device;
4. the Si vertical-channel PMOS device channel of the present invention's preparation is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. in the Si vertical-channel PMOS device of the present invention's preparation,, introduce lightly-doped source drain region (LDD) technology, improved device performance in order effectively to suppress short-channel effect;
6. in the Si vertical-channel PMOS device architecture of the present invention's preparation, adopted the HfO of high K value 2As gate medium, improved the grid-control ability of device, strengthened the electric property of device;
7. to prepare the maximum temperature that relates in the strain Si vertical-channel PMOS device process be 800 ℃ in the present invention; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
8. because process proposed by the invention and existing micron order Si integrated circuit processing technology are compatible; Therefore; Can be under the situation that need not append any fund and equipment input; Preparing conducting channel is PMOS device and the integrated circuit of length 22-45nm, and the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, and realizes the great-leap-forward development of domestic integrated circuit working ability.
Description of drawings
Fig. 1 is the preparation method's of strain Si vertical-channel PMOS integrated device provided by the invention and circuit realization flow figure;
Fig. 2 is the process sketch map for preparing strain Si vertical-channel PMOS integrated device and circuit with method provided by the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain Si vertical-channel PMOS device, and this device conducting channel is back type, and channel direction is vertical with substrate surface.
As a prioritization scheme of the embodiment of the invention, the channel region of this device is a strain Si material, and is compressive strain at channel direction.
As a prioritization scheme of the embodiment of the invention, this device also comprises: a P type Si epitaxial loayer, the 2nd P type relaxation SiGe layer, the 3rd P type that on substrate, stacks gradually growth be the fixing SiGe layer of Ge component of SiGe layer, the 4th P type strain Si layer, the 5th N type strain Si layer, the 6th P type strain Si layer and the 7th of Ge component fixedly.
Prioritization scheme as the embodiment of the invention; The one P type Si epitaxy layer thickness is 200～400nm, and said the 2nd P type relaxation SiGe layer thickness is 1～1.5 μ m, and said the 3rd P type fixedly SiGe layer thickness of Ge component is 200～300nm; Said the 4th P type strain Si layer thickness is 3 ~ 5nm; Said the 5th N type strain Si layer thickness is 22～45nm, said the 6th P type strain Si layer, the said the 7th fixedly the SiGe layer thickness of Ge component be 300～400nm.
Following with reference to accompanying drawing 1 and accompanying drawing 2, the preparation method of strain Si vertical-channel PMOS integrated device of the present invention and circuit is described in further detail.
Embodiment 1: the preparation conducting channel is the strain Si vertical-channel PMOS integrated device circuit of 45nm, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 5 * 10 15Cm -3About N type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type Si epitaxial loayer 2 of 400nm on substrate, and doping content is 5 * 10 15Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type SiGe resilient coating 3 of 1.5 μ m on the Si epitaxial loayer, and the Ge content gradually variational is distributed as from the bottom to top from 0% to 15%, and doping content is 5 * 10 18Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on the SiGe epitaxial loayer growth one layer thickness be the P type SiGe layer 4 of 300nm as the drain region, doping content is 5 * 10 19Cm -3, the Ge component is 15%;
(1e) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type strain Si layer 5a of 5nm on the SiGe epitaxial loayer, and doping content is 5 * 10 17Cm -3, as the first lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on the Si strained layer growth one layer thickness be the N type strain Si layer 5 of 45nm as channel region, doping content is 5 * 10 16Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the P type strain Si layer 5b of 5nm on the Si strained layer, and doping content is 5 * 10 17Cm -3, as the second lightly-doped source drain region (LDD) layer;
(1h) utilize the method for chemical vapor deposition (CVD), at 600 ℃, on the Si strained layer growth one layer thickness be the P type SiGe layer 6 of 400nm as the source region, doping content is 5 * 10 19Cm -3, the Ge component is 15%.
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) photoetching deep trench isolation district utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m in isolated area;
(2b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer 7 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si8, form deep trench isolation 9 at 600 ℃;
(2d) the photoetching shallow trench isolation region utilizes dry etch process, above deep trouth, leaks isolated area with the source and etches the shallow slot that the degree of depth is 0.5 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 10 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) etch away SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.55 μ m;
(3d) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface growth SiO 2Layer 11 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit concentration is 10 20Cm -3Poly-Si12, fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, PMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) etch away surface unnecessary SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(4c) etch away SiN, SiO 2Form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.55 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of the high-k of 6nm at the substrate surface deposition thickness 2Layer 13 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 10 in substrate surface deposit doping content 20Cm -3Poly-Si14, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) remove the unnecessary SiO of substrate surface 2, the SiN barrier layer, form source region 15, finally form PMOS device 16.
Step 5 constitutes the PMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface growth SiO 2Layer 17;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, and constituting conducting channel length is the PMOS integrated circuit of 45nm.
Embodiment 2: the preparation conducting channel is strain Si vertical-channel PMOS integrated device and the circuit of 30nm, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 5 * 10 15Cm -3About N type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type Si epitaxial loayer 2 of 200nm on substrate, and doping content is 5 * 10 15Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type SiGe resilient coating 3 of 1 μ m on the Si epitaxial loayer, and the Ge content gradually variational is distributed as from the bottom to top from 0 to 20%, and doping content is 7 * 10 18Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on the SiGe layer growth one layer thickness be the P type SiGe layer 4 of 200nm as the drain region, doping content is 5 * 10 20Cm -3, the Ge component is 20%;
(1e) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type strain Si layer 5a of 4nm on the SiGe epitaxial loayer, and doping content is 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on the Si strained layer growth one layer thickness be the N type strain Si layer 5 of 30nm as channel region, doping content is 5 * 10 17Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the P type strain Si layer 5b of 4nm on the Si strained layer, and doping content is 5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer;
(1h) utilize the method for chemical vapor deposition (CVD), at 700 ℃, on the Si strained layer growth one layer thickness be the P type SiGe layer 6 of 300nm as the source region, doping content is 5 * 10 20Cm -3, the Ge component is 20%.
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) photoetching deep trench isolation district utilizes dry etch process, etches the deep trouth that the degree of depth is 2 μ m in isolated area;
(2b) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO 2Layer 7 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si8, form deep trench isolation 9 at 700 ℃;
(2d) the photoetching shallow trench isolation region utilizes dry etch process, above deep trouth, leaks isolated area with the source and etches the shallow slot that the degree of depth is 0.4 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 10 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) etch away SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.45 μ m;
(3d) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface growth SiO 2Layer 11 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit concentration is 5 * 10 19Cm -3Poly-Si12, fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, PMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) etch away surface unnecessary SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(4c) etch away SiN, SiO 2Form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.45 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of the high-k of 8nm at the substrate surface deposition thickness 2Layer 13 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 5 * 10 in substrate surface deposit doping content 19Cm -3Poly-Si14, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) remove the unnecessary SiO of substrate surface 2, the SiN barrier layer, form source region 15, finally form PMOS device 16.
Step 5 constitutes the PMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface growth SiO 2Layer 17;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, and constituting conducting channel length is the PMOS integrated circuit of 30nm.
Embodiment 3: the preparation conducting channel is strain Si vertical-channel PMOS integrated device and the circuit of 22nm, and concrete steps are following:
Step 1, the epitaxial material preparation is shown in Fig. 2 (a).
(1a) choosing doping content is 5 * 10 16Cm -3About N type Si substrate slice 1;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type Si epitaxial loayer 2 of 300nm on substrate, and doping content is 5 * 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe resilient coating 3 of 1.25 μ m on the Si epitaxial loayer, and the Ge content gradually variational is distributed as from the bottom to top from 0% to 25%, and doping content is 5 * 10 19Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe epitaxial loayer growth one layer thickness be the P type SiGe layer 4 of 250nm as the drain region, doping content is 5 * 10 20Cm -3, the Ge component is 25%;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer 5a of 3nm on the SiGe epitaxial loayer, and doping content is 5 * 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the N type strain Si layer 5 of 22nm as channel region, doping content is 5 * 10 17Cm -3;
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer 5b of 3nm on the Si strained layer, and doping content is 5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the P type SiGe layer 6 of 350nm as the source region, doping content is 5 * 10 20Cm -3, the Ge component is 25%.
Step 2, isolation preparation is shown in Fig. 2 (b) (left side is a profile, and the right is a vertical view).
(2a) photoetching deep trench isolation district utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;
(2b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO 2Layer 7 all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill Poly-Si8, form deep trench isolation 9 at 800 ℃;
(2d) the photoetching shallow trench isolation region utilizes dry etch process, above deep trouth, leaks isolated area with the source and etches the shallow slot that the degree of depth is 0.45 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation 10 with chemico-mechanical polishing (CMP) method.
Step 3 is leaked the bonding pad preparation, shown in Fig. 2 (c) (left side is a profile, and the right is a vertical view).
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) etch away SiN, SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.5 μ m;
(3d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer 11 forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit concentration is 5 * 10 20Cm -3Poly-Si12, fill up groove, remove the unnecessary Poly-Si in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad.
Step 4, PMOS forms, shown in Fig. 2 (d) (left side is a profile, and the right is a vertical view).
(4a) etch away surface unnecessary SiN, SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(4c) etch away SiN, SiO 2Form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface deposition thickness 2Layer 13 is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3Poly-Si14, and gate groove filled up, remove surface portion Poly-Si, form grid;
(4g) remove the unnecessary SiO of substrate surface 2, the SiN barrier layer, form source region 15, finally form PMOS device 16.
Step 5 constitutes the PMOS integrated circuit, shown in Fig. 2 (e) (left side is a profile, and the right is a vertical view).
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer 17;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire 18, source metal lead-in wire 19 and gate metal lead-in wire 20, and constituting conducting channel length is the PMOS integrated circuit of 22nm.
Strain Si vertical-channel PMOS integrated device and preparation method that the embodiment of the invention provides have following advantage:
1. the strain Si vertical-channel PMOS device channel direction of the present invention's preparation is the vertical direction of strain Si layer; Then channel length is strain Si layer thickness; This thickness can be controlled through Si material growth technique, thereby has avoided the small size photoetching, has reduced the input of lithographic equipment;
In the Si vertical-channel PMOS device of the present invention preparation because the fixing component of SiGe material growth one deck graded component regrowth earlier can reduce dislocation effectively, so the defect concentration in the Si material is low, the strain Si PMOS device performance of preparation is stablized;
3. the present invention utilizes the anisotropy of material strain; Tensile strain Si layer vertical direction lattice compresses, and causes the division of valence-band level, has reduced the effective mass and the scattering probability in hole; Improve mobility, thereby improved the current driving ability and the frequency characteristic of PMOS device;
4. the Si vertical-channel PMOS device channel of the present invention's preparation is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. in the Si vertical-channel PMOS device of the present invention's preparation,, introduce lightly-doped source drain region (LDD) technology, improved device performance in order effectively to suppress short-channel effect;
6. in the Si vertical-channel PMOS device architecture of the present invention's preparation, adopted the HfO of high K value 2As gate medium, improved the grid-control ability of device, strengthened the electric property of device;
7. to prepare the maximum temperature that relates in the strain Si vertical-channel PMOS device process be 800 ℃ in the present invention; Be lower than the technological temperature that causes strained Si channel stress relaxation; Therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;
8. because process proposed by the invention and existing micron order Si integrated circuit processing technology are compatible; Therefore; Can be under the situation that need not append any fund and equipment input; Preparing conducting channel is PMOS device and the integrated circuit of 22-45nm, and the manufacturing capacity of existing micron order Si integrated circuit technology platform is significantly improved, and realizes the great-leap-forward development of domestic integrated circuit working ability.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a strain Si vertical-channel PMOS device is characterized in that said device conducting channel is back type, and channel direction is vertical with substrate surface.
2. strain Si vertical-channel PMOS device according to claim 1 is characterized in that the channel region of said device is a strain Si material, and is compressive strain at channel direction.
3. strain Si vertical-channel PMOS device according to claim 1; It is characterized in that said device also comprises: a P type Si epitaxial loayer, the 2nd P type relaxation SiGe layer, the 3rd P type that on substrate, stacks gradually growth be the fixing SiGe layer of Ge component of SiGe layer, the 4th P type strain Si layer, the 5th N type strain Si layer, the 6th P type strain Si layer and the 7th of Ge component fixedly.
4. strain Si vertical-channel PMOS device according to claim 1; It is characterized in that; A said P type Si epitaxy layer thickness is 200～400nm, and said the 2nd P type relaxation SiGe layer thickness is 1～1.5 μ m, and said the 3rd P type fixedly SiGe layer thickness of Ge component is 200～300nm; Said the 4th P type strain Si layer thickness is 3 ~ 5nm; Said the 5th N type strain Si layer thickness is 22～45nm, said the 6th P type strain Si layer, the said the 7th fixedly the SiGe layer thickness of Ge component be 300～400nm.
5. the preparation method of a strain Si vertical-channel PMOS integrated device is characterized in that, the conducting channel that the vertical PMOS device of the strain Si in the said integrated device has back type; Said preparation method comprises the steps:
The first step, to choose doping content be 10 15～10 16Cm -3N type Si substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), and at 600～750 ℃, seven layer materials of on substrate, growing continuously: ground floor is that thickness is the P type Si epitaxial loayer of 200～400nm, and doping content is 10 15～10 16Cm -3The second layer is that thickness is the P type relaxation SiGe layer of 1～1.5 μ m, and doping content is 5～10 * 10 18Cm -3, the Ge content gradually variational, the Ge component at P type relaxation SiGe layer and P type Si epitaxial layer interface place is 0%, P type relaxation SiGe layer top Ge component is 15～25%; The 3rd layer is that thickness is the fixing SiGe layer of Ge component of P type of 200～300nm, and the Ge component is 15～25%, and consistent with the Ge component at gradual change SiGe layer top, doping content is 5 * 10 19～5 * 10 20Cm -3, as the drain region; The 4th layer is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer; Layer 5 be thickness be the N type strain Si layer of 22～45nm as channel region, doping content is 5 * 10 16～5 * 10 17Cm -3Layer 6 is that thickness is the P type strain Si layer of 3 ~ 5nm, and doping content is 5 * 10 17～5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer; Layer 7 is that thickness is the P type of the 300～400nm fixedly SiGe layer of Ge component that mixes, and the Ge component is 15～25%, and its doping content is 5 * 10 19～5 * 10 20Cm -3, as the source region;
The 3rd step, photoetching deep trench isolation district utilize dry etch process, etch the deep trouth that the degree of depth is 2～3 μ m in isolated area;
The 4th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one SiO 2Layer all covers the deep trouth inner surface, and deposit polysilicon (Poly-Si) forms deep trench isolation with filling up in the deep trouth again;
The 5th step, photoetching shallow trench isolation region utilize dry etch process, above deep trouth, leak isolated area with the source and etch the shallow slot that the degree of depth is 0.4～0.5 μ m; Utilize chemical vapor deposition (CVD) method again,, in shallow slot, fill SiO at 600～800 ℃ 2At last,, remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
The 6th the step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away part Si N and SiO 2Form and leak the bonding pad window; Utilize dry etch process, etching the degree of depth is the leakage groove of 0.45～0.55 μ m; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at the substrate surface SiO that grows 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, the deposit doping content is 5 * 10 in this groove 19～5 * 10 20Cm -3Polysilicon, this groove is filled up, remove the unnecessary polysilicon in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
The 7th goes on foot, etches away surface unnecessary SiN and SiO 2The barrier layer; Utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at substrate surface deposit one deck SiO 2And layer of sin, etch away SiN and SiO 2Form the grid window; Utilize dry etch process, etch the gate groove that the degree of depth is 0.45～0.55 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of the high-k of 6～10nm at the substrate surface deposition thickness 2Layer is as gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600～800 ℃, is 5 * 10 in substrate surface deposit doping content 19～5 * 10 20Cm -3N type polysilicon, and gate groove filled up, remove the surface portion polysilicon, form grid;
The 8th step, the unnecessary SiO of removal substrate surface 2, SiN and SiO 2The barrier layer forms the source region, finally forms the PMOS device;
The 9th step, utilize chemical vapor deposition (CVD) method, at 600～800 ℃, at the substrate surface SiO that grows 2The layer, and on grid, source and drain region lithography fair lead;
The tenth step, metallization, the photoetching lead-in wire forms drain electrode, source electrode and gate metal lead-in wire, and constituting conducting channel length is the PMOS integrated circuit of 22～45nm.
6. method according to claim 5 is characterized in that, channel length is confirmed according to the P type strain Si layer thickness of the second step deposit.
7. method according to claim 5 is characterized in that channel length is got 22～45nm.
8. method according to claim 5 is characterized in that, maximum temperature related among this preparation method is according to chemical vapor deposition (CVD) the technological temperature decision in second, four, five, six, seven and nine steps.
9. method according to claim 5 is characterized in that the maximum temperature among this preparation method is smaller or equal to 800 ℃.
10. the preparation method of a strain Si vertical-channel PMOS integrated circuit is characterized in that, the conducting channel that the vertical PMOS device of the strain Si in the said integrated circuit has back type; Said preparation method comprises the steps:
Step 1, the epitaxial material preparation process:
(1a) choosing doping content is 10 16Cm -3About N type Si substrate slice;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type Si epitaxial loayer of 300nm on substrate, and doping content is 10 16Cm -3
(1c) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type SiGe resilient coating of 1.25 μ m on the Si epitaxial loayer, the Ge content gradually variational, and the Ge component is distributed as from the bottom to top from 0 to 25%, and doping content is 10 19Cm -3
(1d) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the SiGe epitaxial loayer growth one layer thickness be the P type SiGe layer of 250nm as the drain region, doping content is 5 * 10 20Cm -3, the Ge component is 25%;
(1e) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer of 3nm on the SiGe epitaxial loayer, and doping content is 5 * 10 18Cm -3, as the first lightly-doped source drain region (LDD) layer;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the N type strain Si layer of 22nm as channel region, doping content is 5 * 10 17Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the P type strain Si layer of 3nm on the Si strained layer, and doping content is 5 * 10 18Cm -3, as the second lightly-doped source drain region (LDD) layer;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, on the Si strained layer growth one layer thickness be the P type SiGe layer of 350nm as the source region, doping content is 5 * 10 20Cm -3, the Ge component is 25%;
Step 2, the isolation preparation step:
(2a) photoetching deep trench isolation district utilizes dry etch process, etches the deep trouth that the degree of depth is 2.5 μ m in isolated area;
(2b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit SiO 2Layer all covers the deep trouth inner surface;
(2c) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill polysilicon, form deep trench isolation at 800 ℃;
(2d) the photoetching shallow trench isolation region utilizes dry etch process, above deep trouth, leaks isolated area with the source and etches the shallow slot that the degree of depth is 0.45 μ m;
(2e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2
(2f), remove unnecessary oxide layer, form shallow-trench isolation with chemico-mechanical polishing (CMP) method;
Step 3, leak the bonding pad preparation process:
(3a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(3b) etch away SiN and SiO 2Form and leak the bonding pad window;
(3c) utilize dry etch process, etching the degree of depth is the leakage groove of 0.5 μ m;
(3d) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer forms and leaks the trenched side-wall isolation, utilizes dry etch process, removes the SiO of drain region channel bottom 2Layer;
(3e) utilize chemical vapor deposition (CVD) method, at 800 ℃, deposit concentration is 5 * 10 20Cm -3Polysilicon, fill up groove, remove the unnecessary polysilicon in surface with chemico-mechanical polishing (CMP) method, form and leak the bonding pad;
Step 4, PMOS forms step:
(4a) etch away surface unnecessary SiN and SiO 2The barrier layer;
(4b) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface deposit one deck SiO 2And layer of sin;
(4c) etch away SiN and SiO 2Form the grid window;
(4d) utilize dry etch process, etch the gate groove that the degree of depth is 0.5 μ m;
(4e) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of the high-k of 10nm at the substrate surface deposition thickness 2Layer is as gate dielectric layer;
(4f) utilizing chemical vapor deposition (CVD) method, at 800 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3Polysilicon, and gate groove filled up, remove the surface portion polysilicon, form grid;
(4g) remove the unnecessary SiO of substrate surface 2With the SiN barrier layer, form the source region, finally form the PMOS device;
Step 5 constitutes PMOS integrated circuit step:
(5a) utilize chemical vapor deposition (CVD) method, at 800 ℃, at substrate surface growth SiO 2Layer;
(5b) lithography fair lead on grid, source and drain region;
(5c) metallization;
(5d) photoetching lead-in wire forms drain metal lead-in wire, source metal lead-in wire and gate metal lead-in wire, and constituting conducting channel length is the PMOS integrated circuit of 22nm.
CN201210244400.8A 2012-07-16 2012-07-16 Stress silicon (Si) vertical-channel P-channel metal-oxide semiconductor (PMOS) device and preparation method Expired - Fee Related CN102810568B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113889535A (en) * 2021-09-29 2022-01-04 西安电子科技大学 Surface channel MOSFET for wireless weak energy collection and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0829908B1 (en) * 1996-09-17 2002-03-20 Matsushita Electric Industrial Co., Ltd. Field-effect transistor and method of producing the same
CN1574253A (en) * 2003-06-17 2005-02-02 国际商业机器公司 Low leakage heterojunction vertical transistors and high performance devices thereof
CN1954439A (en) * 2004-06-24 2007-04-25 国际商业机器公司 Integration of strained Ge in advanced CMOS technology
CN101317252A (en) * 2005-12-29 2008-12-03 英特尔公司 A tensile strained NMOS transistor using group III-N source/drain regions

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0829908B1 (en) * 1996-09-17 2002-03-20 Matsushita Electric Industrial Co., Ltd. Field-effect transistor and method of producing the same
CN1574253A (en) * 2003-06-17 2005-02-02 国际商业机器公司 Low leakage heterojunction vertical transistors and high performance devices thereof
CN1954439A (en) * 2004-06-24 2007-04-25 国际商业机器公司 Integration of strained Ge in advanced CMOS technology
CN101317252A (en) * 2005-12-29 2008-12-03 英特尔公司 A tensile strained NMOS transistor using group III-N source/drain regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113889535A (en) * 2021-09-29 2022-01-04 西安电子科技大学 Surface channel MOSFET for wireless weak energy collection and preparation method thereof

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