CN102751292B

CN102751292B - A kind of strain BiCMOS integrated device of the mixing crystal face based on three polycrystal SiGe HBT and preparation method

Info

Publication number: CN102751292B
Application number: CN201210244312.8A
Authority: CN
Inventors: 张鹤鸣; 李妤晨; 胡辉勇; 宋建军; 王海栋; 宣荣喜; 舒斌; 郝跃
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2012-07-16
Filing date: 2012-07-16
Publication date: 2016-03-30
Anticipated expiration: 2032-07-16
Also published as: CN102751292A

Abstract

The invention discloses based on three polycrystal SiGes? the mixing crystal face strain BiCMOS integrated device of HBT and preparation method, its process is: preparation SOI substrate, and upper strata basis material is (100) crystal face, and underlying substrate material is (110) crystal face; Etching bipolar device active area, growth N-type Si extension, preparation collector region, then prepare base, emitter region, then form SiGe? HBT device; Nmos device region etch goes out deep trouth, and selective growth crystal face is the nmos device active area of (100), prepares strained Si channel nmos device; In PMOS device region, selective growth crystal face is the SiGe epitaxial loayer of (110), compressive strain SiGe channel PMOS device prepared by this layer; Do you form based on three polycrystal SiGes? the mixing crystal face strain BiCMOS integrated device of HBT and circuit.The present invention makes full use of strain Si material mobility higher than body Si material and the anisotropic feature of mobility, based on SOI substrate, prepared performance enhancement based on three polycrystal SiGes? the mixing crystal face strain BiCMOS integrated circuit of HBT.

Description

A kind of strain BiCMOS integrated device of the mixing crystal face based on three polycrystal SiGe HBT and preparation method

Technical field

The invention belongs to semiconductor integrated circuit technical field, particularly relate to a kind of mixing crystal face based on three polycrystal SiGe HBT strain BiCMOS integrated device and preparation method.

Background technology

The integrated circuit occurred for 1958 is one of invention of 20th century most impact.The microelectronics be born based on this invention has become the basis of existing modern technologies, accelerates more educated, the IT application process that change human society, have also been changed the mode of thinking of the mankind simultaneously.It not only provides the instrument of strong nature remodeling for the mankind, but also has opened up a wide development space.

Semiconductor integrated circuit has become the basis of electronics industry, and people, to the great demand of electronics industry, impel the development in this field very rapid.In the past few decades, the fast development of electronics industry creates tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very large share in world market, the output value has exceeded 10,000 hundred million dollars.

Silicon materials experienced by more than 50 year as semi-conducting material application, traditional SiCMOS and BiCMOS technology with advantages such as its low-power consumption, low noise, high input impedance, high integration, good reliabilitys in integrated circuit fields in occupation of leading position, and constantly to advance according to Moore's Law.At present, in the semi-conductor market in the whole world 90%, be all Si base integrated circuit.

But along with device feature size reduce, the enhancing of integrated level and complexity, there is a series of new problem relating to the aspects such as material, device physics, device architecture and technology.Particularly when IC chip feature sizes enters nanoscale, from device angles, the impact of the short channel effect in nanoscale devices, high-field effect, quantum effect, parasitic parameter, technique ginseng

The impacts of problem on performances such as device leakage current, subthreshold behavior, ON state/off-state currents such as number fluctuation are more and more outstanding, the contradiction of circuit speed and power consumption also will be more serious, on the other hand, along with the develop rapidly of wireless mobile communications, to the performance of device and circuit, as frequency characteristic, noise characteristic, package area, power consumption and cost etc. are had higher requirement, device prepared by the silica-based technique of tradition and integrated circuit are especially simulated and composite signal integrated circuits, more and more cannot meet demand that is novel, high-velocity electrons system.

In order to improve the performance of device and integrated circuit, researcher by novel semi-conducting material as GaAs, InP etc., to obtain the high speed device and integrated circuit that are suitable for wireless mobile communications development.Although GaAs and InP-base compound devices frequency characteristic superior, its preparation technology is higher than Si complex process, cost, and major diameter single crystal preparation difficulty, mechanical strength is low, and heat dispersion is bad, difficult compatible and lack and resemble SiO with Si technique ₂the factors such as such passivation layer limit its extensive use and development.

Because Si material carrier material mobility is lower, so adopt the performance of integrated circuits that SiBiCMOS technology manufactures, especially frequency performance, is greatly limited; And for SiGeBiCMOS technology, although bipolar transistor have employed SiGeHBT, the unipolar device promoted for restriction BiCMOS integrated circuit frequency characteristic still adopts SiCMOS, promote further so these all limit BiCMOS performance of integrated circuits ground.

For this reason, will when not reducing a kind of mobility of charge carrier of types of devices, improve the mobility of the charge carrier of another kind of types of devices, this patent proposes one and utilizes strain gauge technique to prepare BiCMOS, namely based on the preparation of the mixing crystal face strain BiCMOS integrated device of three polycrystal SiGe HBT.

Summary of the invention

The object of the present invention is to provide the mixing crystal face strain BiCMOS integrated device based on three polycrystal SiGe HBT and preparation method, to realize based on SOI substrate, prepare the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device of performance enhancement.

The object of the present invention is to provide a kind of mixing crystal face based on three polycrystal SiGe HBT to strain BiCMOS integrated device, nmos device and PMOS device are strain Si MOS device, and bipolar device is SiGeHBT.

Further, the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling.

Further, the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel.

Further, nmos device is prepared in the SOI substrate that crystal face is (100), and PMOS device is prepared on the substrate of crystal face for (110).

Further, SiGeHBT device base is strain SiGe material.

Further, SiGeHBT device emitter, base stage and collector electrode all adopt polycrystalline silicon material.

Further, SiGeHBT device fabrication process adopts self-registered technology, and is whole plane structure.

Another object of the present invention is to provide a kind of mixing crystal face based on three polycrystal SiGe HBT to strain the preparation method of BiCMOS integrated device, this preparation method comprises the steps:

The first step, choose two panels N-type doping Si sheet, wherein a slice crystal face is (110), and a slice crystal face is (100), and two panels doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, be oxidized two panels Si sheet surface, oxidated layer thickness is 0.5 ~ 1 μm; Be the basis material of a slice as upper strata of (100) using crystal face, and in this basis material hydrogen injecting, be the basis material of a slice as lower floor of (110) using crystal face; Chemico-mechanical polishing (CMP) technique is adopted to carry out polishing to two oxide layer surfaces;

Second step, two panels Si sheet oxide layer is placed in ultra-high vacuum environment relatively at the temperature of 350 ~ 480 DEG C and realizes bonding; Si sheet temperature after bonding is raised 100 ~ 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100 ~ 200nm, and carry out chemico-mechanical polishing (CMP) at its break surface, form SOI substrate;

3rd step, be the SiO of 300 ~ 500nm in substrate surface thermal oxidation a layer thickness ₂layer, photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 ~ 5 μm; Utilize the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, in deep trouth, fill SiO ₂, by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

4th step, be 1 × 10 in substrate surface epitaxial growth one deck doping content ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 2 ~ 3 μm; Photoetching bipolar device active area, utilizes dry etch process, in bipolar device active area, etches the deep trouth that the degree of depth is 3.5 ~ 5 μm, the oxide layer of centre is carved thoroughly; At the N-type Si epitaxial loayer that bipolar device epitaxial growth a layer thickness is 3.5 ~ 5 μm, as collector region, this layer of doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

5th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 500 ~ 700nm in epitaxial si layer surface deposition a layer thickness ₂layer, photoetching collector contact district window, carries out phosphorus injection to substrate, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, then by substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

6th step, etch away the oxide layer of substrate surface, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit two layer material: ground floor is SiO ₂layer, thickness is 20 ~ 40nm; The second layer is P type Poly-Si layer, and thickness is 200 ~ 400nm, and doping content is 1 × 10 ²⁰~ 1 × 10 ²¹cm ^-3;

7th step, photoetching Poly-Si, form outer base area, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200 ~ 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

8th step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, deposit layer of sin layer, thickness is 50 ~ 100nm, photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer; Recycling chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 10 ~ 20nm, and dry etching falls emitter window SiN, forms side wall;

9th step, utilize wet etching, to SiO in window ₂layer carries out excessive erosion, forms region, base, utilizes chemical vapor deposition (CVD) method, and at 600 ~ 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 15 ~ 25%, and doping content is 5 × 10 ¹⁸~ 5 × 10 ¹⁹cm ^-3, thickness is 20 ~ 60nm;

Tenth step, photoetching collector electrode window, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit Poly-Si, thickness is 200 ~ 400nm, again phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

11 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, photoetching collector contact hole, and phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer;

12 step, utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit SiO ₂layer, at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation; The method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 ~ 800 DEG C, deposit one SiO ₂layer;

13 step, photoetching PMOS device active area, in PMOS device active area, utilize dry etching, etches the deep trouth that the degree of depth is 3.4 ~ 5.3 μm, the oxide layer of centre carved thoroughly; Utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth seven layer material on the PMOS device active area of (110) crystal face substrate: ground floor is N-type Si resilient coating, thickness is 1.5 ~ 2.5 μm, deep trouth fills up by this layer, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3; The second layer to be thickness the be N-type SiGe graded bedding of 1.5 ~ 2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ × 10 ¹⁵cm ^-3; Third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ²⁰cm ^-3, as the drain region of PMOS device; 4th layer is thickness is 3 ~ 5nmP type strained si layer/, and doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer; Layer 5 to be thickness the be N-type strain Si of 22 ~ 45nm is as channel region, and doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3; The P type strained si layer/of layer 6 to be thickness be 3 ~ 5nm, doping content is 1 ~ 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer; Layer 7 is Ge component is 15 ~ 25%, and thickness is the P type SiGe of 200 ~ 400nm, and doping content is 5 ~ 10 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

14 step, photoetching nmos device active area, in nmos device active area, utilize dry etching, etch the deep trouth that the degree of depth is 2 ~ 3 μm, utilize chemical vapor deposition (CVD) method, at 600 ~ 750 DEG C, selective epitaxial growth four layer material on the nmos device active area of (100) crystal face substrate: the P type Si resilient coating of ground floor to be thickness be 200 ~ 400nm, doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, the second layer to be thickness the be P type SiGe graded bedding of 1.6 ~ 2.2 μm, bottom Ge component is 0%, and top Ge component is 15 ~ 25%, and doping content is 1 ~ 5 × 10 ¹⁵cm ^-3, third layer is Ge component is 15 ~ 25%, and thickness is the P type SiGe layer of 200 ~ 400nm, and doping content is 1 ~ 5 × 10 ¹⁶cm ^-3, the N-type strained si layer/of the 4th layer of to be thickness be 15 ~ 20nm, doping content is 5 × 10 ¹⁶~ 5 × 10 ¹⁷cm ^-3as the raceway groove of nmos device;

15 step, utilize chemical vapor deposition (CVD) method at substrate surface, at 600 ~ 800 DEG C, deposit one deck SiO ₂resilient coating and layer of sin, etch leakage trench openings, utilize dry etch process, and etching the degree of depth at PMOS device drain region is 0.3 ~ 0.7 μm of leakage groove; Utilize chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at substrate surface deposit one deck SiO ₂, form PMOS device and leak trenched side-wall isolation; Dry etching is utilized to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-SiGe beyond flute surfaces, formed and leak bonding pad;

16 step, utilize dry etch process, etching the degree of depth in PMOS device gate region is 0.5 ~ 0.9 μm of gate groove; Utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer; Utilizing chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, is 1 ~ 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10 ~ 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

17 step, etch nmos device active area, utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 ~ 400 DEG C, is the HfO of the high-k of 6 ~ 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer; Deposit one deck intrinsic Poly-SiGe again, thickness is 100 ~ 300nm, Ge component is 10 ~ 30%, etching N MOS device grid; Photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 ~ 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD); Be the SiO of 3 ~ 5nm at whole substrate deposit one thickness ₂layer, dry etching falls this layer of SiO ₂, as nmos device grid curb wall, form nmos device grid;

18 step, carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 ~ 5 × 10 ²⁰cm ^-3;

19 step, the source making PMOS device by lithography, leakage and grid lead window, sputter layer of metal nickel (Ni) alloy over the entire substrate, and autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms NMOS and PMOS device Metal Contact; By chemical vapor deposition (CVD) method, at 600 ~ 800 DEG C, at Grown SiO ₂layer, photoetching lead-in wire window, splash-proofing sputtering metal, photoetching goes between, and forms the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device that conducting channel is 22 ~ 45nm.

Further, wherein PMOS device channel length is determined according to the N-type strained si layer/layer thickness of the 13 step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

Further, maximum temperature involved in this preparation method determines to chemical vapor deposition (CVD) technological temperature in the 15 step and the 19 step according to the 9th step, and maximum temperature is less than or equal to 800 DEG C.

Another object of the present invention is to provide a kind of mixing crystal face based on three polycrystal SiGe HBT to strain the preparation method of BiCMOS integrated circuit, this preparation method comprises the steps:

Step 1, implementation method prepared by SOI substrate material is:

(1a) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as upper strata basis material, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 1 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.5 μm, as underlying substrate material;

(1c) adopt chemico-mechanical polishing (CMP) technique, respectively polishing is carried out to the upper strata substrate material surface after lower floor and hydrogen injecting;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 350 DEG C of temperature;

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure;

Step 2, implementation method prepared by isolated area is:

(2a) be the SiO of 300nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 3 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in deep trouth, fill SiO ₂;

(2d) by chemico-mechanical polishing (CMP) method, remove the oxide layer of excess surface, form deep trench isolation;

(2e) substrate surface thermal oxidation a layer thickness is the SiO of 300nm ₂layer;

Step 3, implementation method prepared by collector contact district is:

(3a) photoetching bipolar device active area;

(3b) utilize dry etch process, in bipolar device active area, etch the deep trouth that the degree of depth is 2 μm, the oxide layer of centre is carved thoroughly;

(3c) be 1 × 10 in bipolar device active area epitaxial growth one deck doping content ¹⁶cm ^-3si layer, thickness is 2 μm, as collector region;

(3d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, answer deposit a layer thickness to be the SiO of 500nm on epitaxial si layer surface ₂layer;

(3e) photoetching collector contact district window;

(3f) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ¹⁹cm ^-3, form collector contact area;

(3g) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation;

Step 4, implementation method prepared by base contact is:

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 600 DEG C, is the SiO of 20nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 200nm, and doping content is 1 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 600 DEG C, at substrate surface deposit SiO ₂layer, thickness is 200nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in substrate surface deposit one SiN layer, thickness is 50nm;

(4e) photoetching emitter window, etches away the SiN layer in emitter window and Poly-Si layer;

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm;

Step 5, implementation method prepared by base material is:

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5b) wet etching is utilized, to SiO in window ₂layer carries out excessive erosion, forms region, base;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm;

Step 6, implementation method prepared by emitter region is:

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 600 DEG C, at substrate surface deposit Poly-Si, thickness is 200nm;

(6b) phosphorus injection is carried out to substrate, and utilize chemico-mechanical polishing (CMP) to remove emitter and collector contact hole region with the Poly-Si of outer surface, form emitter and collector;

(6c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer;

Step 7, the implementation method that SiGeHBT is formed is:

(7a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit SiO ₂layer, anneal 120s at 950 DEG C of temperature, activator impurity, forms SiGeHBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer;

Step 8, implementation method prepared by PMOS device active area is:

(8a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 3.4 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.5 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(8d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(8e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 22nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of PMOS device;

(8f) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, be the P type strained si layer/of 3nm at Grown thickness, doping content is 1 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(8g) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device;

Step 9, implementation method prepared by nmos device active area is:

(9a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2 μm;

(9b) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 200nm, doping content is 1 × 10 ¹⁵cm ^-3;

(9c) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.6 μm, and bottom Ge component is 0%, and top is 15%, and doping content is 1 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 600 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 200nm, and Ge component is 15%, and doping content is 1 × 10 ¹⁶cm ^-3;

(9e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device;

Step 10, the implementation method that PMOS device leaks bonding pad preparation preparation is:

(10a) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(10b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.3 μm of leakage groove;

(10c) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(10d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad;

Step 11, implementation method prepared by PMOS grid bonding pad is:

(11a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.5 μm of gate groove;

(11b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(11c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device;

Step 12, implementation method prepared by nmos device is:

(12a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 300 DEG C, is the HfO of the high-k of 6nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(12b) chemical vapor deposition (CVD) method is utilized, at 600 DEG C, deposit one deck Poly-SiGe on gate dielectric layer, thickness is 100nm, Ge component is 10%;

(12c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(12d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 1 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(12e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, deposit one thickness is the SiO of 3nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(12f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device;

Step 13, implementation method prepared by formation BiCMOS integrated circuit is:

(13a) photoetching lead-in wire window;

(13b) sputter layer of metal nickel (Ni) alloy over the entire substrate, autoregistration forms metal silicide, the metal that clean surface is unnecessary, forms device Metal Contact;

(13c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, the final CMOS of formation conducting channel is that the mixing crystal face based on three polycrystal SiGe HBT of 22nm strains BiCMOS integrated device and circuit.

Tool of the present invention has the following advantages:

1. the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device that prepared by the present invention have employed mixing crystal face substrate technology, namely on same substrate slice, be distributed with (100) and (110) these two kinds of crystal faces, (110) crystal face is compressive strain for strain Si PMOS device, the mobility in its hole is higher than body Si material, and be tensile strain for strain Si nmos device on (100) crystal face, the mobility of its electronics is also higher than body Si material, therefore, this electric property such as device frequency and current driving ability is higher than the body SiCMOS device of same size,

2. the mixing crystal face based on three polycrystal SiGe HBT that prepared by the present invention strains BiCMOS integrated device, adopt selective epitaxial technology, respectively at nmos device and PMOS device active area selective growth strain Si material, improve the flexibility of device layout, enhance BiCMOS device and integrated circuit electric property;

3. have employed SOI substrate in the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device that prepared by the present invention, reduce power consumption and the cut-in voltage of device and circuit, improve the reliability of device and circuit;

4. the present invention's preparation is based in the mixing crystal face strain BiCMOS integrated device technique of three polycrystal SiGe HBT, adopt Poly-SiGe material as grid, its work function changes with the change of Ge component, by regulating Ge component in Poly-SiGe grid, realizing CMOS threshold voltage can continuous setup, decrease processing step, reduce technology difficulty;

5. the maximum temperature related in the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device process that prepared by the present invention is 800 DEG C, lower than the technological temperature causing strained Si channel stress relaxation, therefore this preparation method can keep strained Si channel stress effectively, improves the performance of integrated circuit;

6. the raceway groove that the mixing crystal face based on three polycrystal SiGe HBT that prepared by the present invention strains PMOS device in BiCMOS integrated device is hollow, namely grid can control raceway groove on four sides in the trench, therefore, this device adds the width of raceway groove in limited region, thus improve the current driving ability of device, add the integrated level of integrated circuit, reduce the manufacturing cost of lsi unit area;

7., in the strain of the mixing crystal face based on the three polycrystal SiGe HBT BiCMOS integrated device that prepared by the present invention, in order to effectively suppress short-channel effect in MOS device structure, introducing light dope source and drain (LDD) technique, improve device performance;

8. the present invention prepare based in the mixing crystal face BiCMOS integrated device structure of three polycrystal SiGe HBT, have employed the HfO of high-k ₂as gate medium, improve the grid-control ability of device, enhance the electric property of device;

9. the present invention prepare based in the mixing crystal face BiCMOS integrated device process of three polycrystal SiGe HBT, SiGeHBT adopts Fully self-aligned process, efficiently reduces dead resistance and electric capacity, improves electric current and the frequency characteristic of device;

10. the mixing crystal face BiCMOS integrated device based on three polycrystal SiGe HBT prepared of the present invention, the emitter of SiGeHBT, base stage and collector electrode all adopt polycrystalline, polycrystalline can partly be produced on above oxide layer, reduce the area of device active region, thus reduction device size, improve the integrated level of circuit.

Accompanying drawing explanation

Fig. 1 is provided by the invention based on the mixing crystal face BiCMOS integrated device of three polycrystal SiGe HBT and the realization flow figure of circuit preparation method.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

Embodiments provide a kind of mixing crystal face based on three polycrystal SiGe HBT strain BiCMOS integrated device, nmos device and PMOS device are strain Si MOS device, and bipolar device is SiGeHBT device;

As a prioritization scheme of the embodiment of the present invention, the conducting channel of nmos device is strain Si material, and the conducting channel of nmos device is strain Si material, and the conducting channel of nmos device is tensile strain Si material, and the conducting channel of nmos device is planar channeling;

As a prioritization scheme of the embodiment of the present invention, the conducting channel of PMOS device is strain Si material, and the conducting channel of PMOS device is compressive strain Si material, and the conducting channel of PMOS device is vertical-channel;

As a prioritization scheme of the embodiment of the present invention, nmos device is prepared in the SOI substrate that crystal face is (100), and PMOS device is prepared on the substrate of crystal face for (110);

As a prioritization scheme of the embodiment of the present invention, SiGeHBT device base is strain SiGe material;

As a prioritization scheme of the embodiment of the present invention, the emitter of SiGeHBT device, base stage and collector electrode all adopt polycrystalline silicon material;

As a prioritization scheme of the embodiment of the present invention, SiGeHBT device fabrication process adopts self-registered technology, and is whole plane structure.

Referring to accompanying drawing 1, technological process prepared by the mixing crystal face BiCMOS integrated device that the present invention is based on three polycrystal SiGe HBT is described in further detail.

Embodiment 1: preparation 22nm based on the mixing crystal face BiCMOS integrated device of three polycrystal SiGe HBT and circuit,

Concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1e) substrate temperature after bonding is raised 200 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 100nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2e) substrate surface thermal oxidation a layer thickness is the SiO of 300nm ₂layer.

Step 3, prepared by collector contact district.

(3a) photoetching bipolar device active area;

(3e) photoetching collector contact district window;

(3g) by substrate at 950 DEG C of temperature, annealing 120s, carry out impurity activation.

Step 4, prepared by base contact.

(4f) utilize chemical vapor deposition (CVD) method, at 600 DEG C, at substrate surface deposit layer of sin layer, thickness is 10nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 600 DEG C, in base regioselectivity growth SiGe base, Ge component is 15%, and doping content is 5 × 10 ¹⁸cm ^-3, thickness is 20nm.

Step 6, prepared by emitter region.

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, SiGeHBT is formed.

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 600 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area.

(8g) utilize chemical vapor deposition (CVD) method, at 600 DEG C, strained si layer/grow the P type SiGe layer that a layer thickness is 200nm, Ge component is 15%, and doping content is 5 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 9, prepared by nmos device active area.

(9e) utilize chemical vapor deposition (CVD) method, at 600 DEG C, regrowth a layer thickness is the P type strained si layer/of 15nm, and doping content is 5 × 10 ¹⁶cm ^-3, as the raceway groove of nmos device.

Step 10, PMOS device leaks bonding pad preparation preparation.

(10d) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, prepared by PMOS grid bonding pad.

(11c) utilizing chemical vapor deposition (CVD) method, at 600 DEG C, is 1 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 10%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 12, prepared by nmos device.

(12c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(12f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 1 × 10 ²⁰cm ^-3, form nmos device.

Step 13, forms the preparation of BiCMOS integrated circuit.

(13a) photoetching lead-in wire window;

Embodiment 2: preparation 30nm strains BiCMOS integrated device and circuit based on the mixing crystal face of three polycrystal SiGe HBT, and concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 3 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 0.75 μm, as the basis material of lower floor;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 400 DEG C of temperature;

(1e) substrate temperature after bonding is raised 150 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 150nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2a) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 4 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in deep trouth, fill SiO ₂;

(2e) be the SiO of 400nm in substrate surface thermal oxidation a layer thickness ₂layer.

Step 3, prepared by collector contact district.

(3a) photoetching bipolar device active area;

(3b) utilize dry etch process, in bipolar device active area, etch the deep trouth that the degree of depth is 2.5 μm, the oxide layer of centre is carved thoroughly;

(3c) be 5 × 10 in bipolar device active area epitaxial growth one deck doping content ¹⁶cm ^-3si layer, thickness is 2.5 μm, as collector region;

(3d) photoetching collector contact district window;

(3e) phosphorus injection is carried out to substrate, make collector contact district doping content be 5 × 10 ¹⁹cm ^-3, form collector contact area;

(3f) by substrate at 1000 DEG C of temperature, annealing 60s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 700 DEG C, is the SiO of 30nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 300nm, and doping content is 5 × 10 ²⁰cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 700 DEG C, at substrate surface deposit SiO ₂layer, thickness is 300nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in substrate surface deposit one SiN layer, thickness is 80nm;

(4f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, at substrate surface deposit layer of sin layer, thickness is 15nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 700 DEG C, in base regioselectivity growth SiGe base, Ge component is 20%, and doping content is 1 × 10 ¹⁹cm ^-3, thickness is 40nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 700 DEG C, at substrate surface deposit Poly-Si, thickness is 300nm;

(6c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 5 × 10 ¹⁹cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, SiGeHBT is formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit SiO ₂layer, anneal 60s at 1000 DEG C of temperature, activator impurity, forms SiGeHBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 700 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area.

(8a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 4.4 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2 μm along (110) crystal face, doping content is 3 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the N-type Ge component trapezoidal profile of 1.75 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the drain region of PMOS device;

(8e) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(8f) utilize chemical vapor deposition (CVD) method, at 700 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 30nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(8g) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, be the P type strained si layer/of 4nm at Grown thickness, doping content is 3 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(8h) utilize chemical vapor deposition (CVD) method, at 700 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 8 × 10 ¹⁹cm ^-3, as the source region of PMOS device.

Step 9, prepared by nmos device active area.

(9a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 2.4 μm;

(9b) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 300nm, doping content is 3 × 10 ¹⁵cm ^-3;

(9c) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 1.75 μm, and bottom Ge component is 0%, and top is 20%, and doping content is 3 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 700 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 300nm, and Ge component is 20%, and doping content is 3 × 10 ¹⁶cm ^-3;

(9e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, regrowth a layer thickness is the P type strained si layer/of 17nm, and doping content is 1 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 10, PMOS device leaks bonding pad preparation.

(10a) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(10b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.5 μm of leakage groove;

(10c) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(10d) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, prepared by PMOS device grid bonding pad.

(11a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.7 μm of gate groove;

(11b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(11c) utilizing chemical vapor deposition (CVD) method, at 700 DEG C, is 3 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 20%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 12, prepared by nmos device.

(12a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 350 DEG C, is the HfO of the high-k of 8nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(12b) chemical vapor deposition (CVD) method is utilized, at 700 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 200nm, Ge component is 20%;

(12c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(12d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 3 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(12e) utilize chemical vapor deposition (CVD) method, at 700 DEG C, deposit one thickness is the SiO of 4nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device grid curb wall, form nmos device grid;

(12f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 3 × 10 ²⁰cm ^-3, form nmos device.

Step 13, forms BiCMOS integrated circuit.

(13a) lead-in wire window is made by lithography;

(13c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole metal lead wire, base metal lead-in wire, collector electrode metal lead-in wire, final formation conducting channel is the strain BiCMOS integrated device of the mixing crystal face based on three polycrystal SiGe HBT and the circuit of 30nm.

Embodiment 3: preparation 45nm strains BiCMOS integrated device and circuit based on the mixing crystal face of three polycrystal SiGe HBT, and concrete steps are as follows:

Step 1, prepared by SOI substrate material.

(1a) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (100), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material on upper strata, and in this basis material hydrogen injecting;

(1b) choosing N-type doping content is 5 × 10 ¹⁵cm ^-3si sheet, crystal face is (110), is oxidized its surface, and oxidated layer thickness is 1 μm, as the basis material of lower floor's active layer;

(1d) be close to relative with upper strata substrate material surface oxide layer for the lower floor after polishing, be placed in ultra-high vacuum environment and realize bonding at 480 DEG C of temperature;

(1e) substrate temperature after bonding is raised 100 DEG C, make the hydrogen place fracture that upper strata basis material is injecting, the part unnecessary to upper strata basis material is peeled off, and retains the Si material of 200nm, and carry out chemico-mechanical polishing (CMP) at this break surface, form soi structure.

Step 2, prepared by isolated area.

(2a) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer;

(2b) photoetching area of isolation, utilizes dry etch process, goes out at deep trench isolation region etch the deep trouth that the degree of depth is 5 μm;

(2c) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in deep trouth, fill SiO ₂;

(2e) be the SiO of 500nm in substrate surface thermal oxidation a layer thickness ₂layer.

Step 3, prepared by collector contact district.

(3a) photoetching bipolar device active area;

(3b) utilize dry etch process, in bipolar device active area, etch the deep trouth that the degree of depth is 3 μm, the oxide layer of centre is carved thoroughly;

(3c) be 1 × 10 in bipolar device active area epitaxial growth one deck doping content ¹⁷cm ^-3si layer, thickness is 3 μm, as collector region;

(3d) photoetching collector contact district window;

(3e) phosphorus injection is carried out to substrate, make collector contact district doping content be 1 × 10 ²⁰cm ^-3, form collector contact area;

(3f) by substrate at 1100 DEG C of temperature, annealing 15s, carry out impurity activation.

Step 4, prepared by base contact.

(4a) etching away substrate surface oxide layer, utilize chemical vapor deposition (CVD) method, at 800 DEG C, is the SiO of 40nm in substrate surface deposit a layer thickness ₂layer;

(4b) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit one deck P type Poly-Si layer, as base contact district, this layer thickness is 400nm, and doping content is 1 × 10 ²¹cm ^-3;

(4c) photoetching Poly-Si, forms outer base area, at 800 DEG C, at substrate surface deposit SiO ₂layer, thickness is 400nm, utilizes the method for chemico-mechanical polishing (CMP) to remove the SiO on Poly-Si surface ₂;

(4d) utilize chemical vapor deposition (CVD) method, at 800 DEG C, in substrate surface deposit one SiN layer, thickness is 100nm;

(4f) utilize chemical vapor deposition (CVD) method, at 800 DEG C, at substrate surface deposit layer of sin layer, thickness is 20nm.

Step 5, prepared by base material.

(5a) utilize dry method, etch away emitter window SiN, form side wall;

(5c) utilize chemical vapor deposition (CVD) method, at 750 DEG C, in base regioselectivity growth SiGe base, Ge component is 25%, and doping content is 5 × 10 ¹⁹cm ^-3, thickness is 60nm.

Step 6, prepared by emitter region.

(6a) photoetching collector electrode window, utilizes chemical vapor deposition (CVD) method, and at 800 DEG C, at substrate surface deposit Poly-Si, thickness is 400nm;

(6c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer;

(6d) photoetching collector contact hole, and again phosphorus injection is carried out to this contact hole, to improve the doping content of the Poly-Si in contact hole, make it reach 1 × 10 ²⁰cm ^-3, finally remove the SiO on surface ₂layer.

Step 7, SiGeHBT is formed.

(7a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit SiO ₂layer, anneal 15s at 1100 DEG C of temperature, activator impurity, forms SiGeHBT device;

(7b) method of chemical vapor deposition (CVD) is utilized at substrate surface, at 800 DEG C, deposit one SiO ₂layer.

Step 8, prepared by PMOS device active area.

(8a) photoetching PMOS device active area, in PMOS device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 5.3 μm, oxide layer is carved thoroughly;

(8b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, in deep trouth, grow the N-type Si resilient coating that a layer thickness is 2.5 μm along (110) crystal face, doping content is 5 × 10 ¹⁵cm ^-3;

(8c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe5 that a layer thickness is the N-type Ge component trapezoidal profile of 2 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(8d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the drain region of PMOS device;

(8e) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as P type lightly-doped source drain structure (P-LDD) layer;

(8f) utilize chemical vapor deposition (CVD) method, at 750 DEG C, drain region grows the N-type strained si layer/that a layer thickness is 45nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of PMOS device;

(8g) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, be the P type strained si layer/of 5nm at Grown thickness, doping content is 5 × 10 ¹⁸cm ^-3, as the 2nd P type lightly-doped source drain structure (P-LDD) layer;

(8h) utilize chemical vapor deposition (CVD) method, at 750 DEG C, strained si layer/grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 1 × 10 ²⁰cm ^-3, as the source region of PMOS device.

Step 9, prepared by nmos device active area.

(9a) photoetching nmos device active area, in nmos device active area, utilizes dry etching, etches the deep trouth that the degree of depth is 3 μm;

(9b) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, grow at nmos device active area (100) crystal face the P type Si resilient coating that a layer thickness is 400nm, doping content is 5 × 10 ¹⁵cm ^-3;

(9c) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, Si resilient coating grows the SiGe that a layer thickness is the P type Ge component trapezoidal profile of 2.2 μm, and bottom Ge component is 0%, and top is 25%, and doping content is 5 × 10 ¹⁵cm ^-3;

(9d) utilize the method for chemical vapor deposition (CVD), at 750 DEG C, the SiGe layer of Ge component trapezoidal profile grows the P type SiGe layer that a layer thickness is 400nm, and Ge component is 25%, and doping content is 5 × 10 ¹⁶cm ^-3;

(9e) utilize chemical vapor deposition (CVD) method, at 750 DEG C, regrowth a layer thickness is the P type strained si layer/of 20nm, and doping content is 5 × 10 ¹⁷cm ^-3, as the raceway groove of nmos device.

Step 10, PMOS device leaks bonding pad preparation.

(10a) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface consecutive deposition one deck SiO ₂and layer of sin;

(10b) etch PMOS device and leak trench openings, utilize dry etch process, etching the degree of depth at PMOS device drain region is 0.7 μm of leakage groove;

(10c) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, at substrate surface deposit one deck SiO ₂, utilize dry etching to remove the SiO of plane ₂layer, only retains PMOS device and leaks trenched side-wall SiO ₂layer, forms PMOS device and leaks trenched side-wall isolation;

(10d) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-Si, PMOS device is leaked groove and fills up, then get rid of PMOS device and leak Poly-Si beyond flute surfaces, formed and leak bonding pad.

Step 11, prepared by PMOS device grid bonding pad.

(11a) utilize dry etch process, going out the degree of depth at PMOS device drain-gate region etch is 0.9 μm of gate groove;

(11b) utilizing atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as PMOS device gate dielectric layer;

(11c) utilizing chemical vapor deposition (CVD) method, at 800 DEG C, is 5 × 10 in substrate surface deposit doping content ²⁰cm ^-3p type Poly-SiGe, Ge component is 30%, is filled up by PMOS device gate groove, then gets rid of Poly-SiGe and SiO beyond PMOS device gate groove surface ₂layer, as grid region, forms PMOS device.

Step 12, prepared by nmos device.

(12a) etching nmos device active area, utilize atomic layer chemical vapor deposit (ALCVD) method, at 400 DEG C, is the HfO of the high-k of 10nm at substrate surface deposition thickness ₂layer, as nmos device gate dielectric layer;

(12b) chemical vapor deposition (CVD) method is utilized, at 800 DEG C, deposit one deck intrinsic Poly-SiGe on gate dielectric layer, thickness is 300nm, Ge component is 30%;

(12c) Poly-SiGe, HfO is etched ₂layer, forms grid;

(12d) photoetching nmos device active area, carries out N-type ion implantation to nmos device, and forming doping content is 5 × 10 ¹⁸cm ^-3n-type lightly-doped source drain structure (N-LDD);

(12e) utilize chemical vapor deposition (CVD) method, at 800 DEG C, deposit one thickness is the SiO of 5nm over the entire substrate ₂layer, dry etching falls this layer of SiO ₂, retain nmos device gate lateral wall, form nmos device grid;

(12f) carry out the injection of N-type phosphonium ion in nmos device active area, autoregistration generates source region and the drain region of nmos device, makes source region and drain region doping content reach 5 × 10 ²⁰cm ^-3, form nmos device.

Step 13, forms BiCMOS integrated circuit.

(13a) photoetching lead-in wire window;

(13c) splash-proofing sputtering metal, photoetching goes between, form the source of nmos device, grid, the leakage of drain electrode and PMOS device, source, gate electrode respectively, bipolar transistor emitter pole, base stage, collector electrode metal lead-in wire, final formation conducting channel is the strain BiCMOS integrated device of the mixing crystal face based on three polycrystal SiGe HBT and the circuit of 45nm.

The strain BiCMOS integrated device of the mixing crystal face based on three polycrystal SiGe HBT that the embodiment of the present invention provides and preparation method's tool have the following advantages:

9. the present invention prepare based in the mixing crystal face BiCMOS integrated device process of three polycrystal SiGe HBT, SiGeHBT device adopt Fully self-aligned process, efficiently reduce dead resistance and electric capacity, improve electric current and the frequency characteristic of device;

10. the mixing crystal face BiCMOS integrated device based on three polycrystal SiGe HBT prepared of the present invention, the emitter of SiGeHBT device, base stage and collector electrode all adopt polycrystalline, polycrystalline can partly be prepared in above oxide layer, reduce the area of device active region, thus reduction device size, improve the integrated level of circuit.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1., based on a preparation method for the mixing crystal face strain BiCMOS integrated device of three polycrystal SiGe HBT, it is characterized in that, this preparation method comprises the steps:

4th step, be 1 × 10 in substrate surface epitaxial growth one deck doping content ¹⁶~ 1 × 10 ¹⁷cm ^-3si layer, thickness is 2 ~ 3 μm; Photoetching bipolar device active area, utilizes dry etch process, in bipolar device active area, etches the deep trouth that the degree of depth is 3.5 ~ 5 μm, the oxide layer of centre is carved thoroughly; At the N-type Si epitaxial loayer that bipolar device surfaces of active regions epitaxial growth a layer thickness is 3.5 ~ 5 μm, as collector region, this layer of doping content is 1 × 10 ¹⁶~ 1 × 10 ¹⁷cm ^-3;

5th step, utilizing the method for chemical vapor deposition (CVD), at 600 ~ 800 DEG C, is the SiO of 500 ~ 700nm in N-type Si epi-layer surface deposit a layer thickness ₂layer, photoetching collector contact district window, carries out phosphorus injection to substrate, makes collector contact district doping content be 1 × 10 ¹⁹~ 1 × 10 ²⁰cm ^-3, form collector contact area, then by substrate at 950 ~ 1100 DEG C of temperature, annealing 15 ~ 120s, carries out impurity activation;

2. method according to claim 1, wherein PMOS device channel length is determined according to the N-type strained si layer/layer thickness of the 13 step deposit, and get 22 ~ 45nm, nmos device channel length is controlled by photoetching process.

3. preparation method according to claim 1, maximum temperature involved in this preparation method determines to chemical vapor deposition (CVD) technological temperature in the 15 step and the 19 step according to the 9th step, and maximum temperature is less than or equal to 800 DEG C.