CN102780485B

CN102780485B - Configurable D latch for chaos computing

Info

Publication number: CN102780485B
Application number: CN201210265306.0A
Authority: CN
Inventors: 姜小波; 黎红源; 袁群
Original assignee: South China University of Technology SCUT
Current assignee: South China University of Technology SCUT
Priority date: 2012-07-27
Filing date: 2012-07-27
Publication date: 2014-07-16
Anticipated expiration: 2032-07-27
Also published as: CN102780485A

Abstract

The invention discloses a configurable D latch for chaos computing. The configurable D latch for the chaos computing comprises an alternative data strobe device and a configurable logic gate. According to the alternative data strobe device, input signals are a first input signal and a feedback signal respectively, a control signal is a strobe signal, and an output signal is a signal after strobe. According to the configurable logic gate, input signals are a signal after strobe and a second input signal, control signals are a control signal Ctra and a control signal Ctrb respectively, and output signals are an output signal Vout and an out signal NVout. The output signal Vout of the configurable logic gate is the input signal, namely the feedback signal of the alternative data strobe device. By configuration of the two control signals and the other input signal of the configurable logic gate, the D latch can achieve different functions so as to achieve dynamic computing.

Description

Configurable D latch for chaotic calculation

Technical Field

The invention relates to the field of electronic technology and dynamic operation, in particular to a configurable D latch for chaotic calculation.

Background

A latch is a pulse level sensitive memory cell circuit that changes state under a particular input pulse level. Typically, the pulse level has only two states, high and low. When the pulse level is active high, the output of the latch will follow the input of the latch if the input pulse level is high, and will remain unchanged if the input pulse level is low. Conversely, when the pulse level is active low, if the input pulse level is low, the output of the latch will follow the input of the latch, and if the input pulse level is high, the output of the latch will remain unchanged.

Latches are the main blocks of the arithmetic part in microprocessors, while D-latches are typical logic circuits thereof. However, conventional D-latches are static in nature and cannot be rewired or configured during operation. For example, a hardware component such as an 8-bit D-type latch cannot be changed in its function because its circuit structure cannot be reconnected or configured once it is successfully manufactured.

With the development of electronic technology and computer technology, the current electronic design has begun to develop into the field of dynamic computing. Research on reconfigurable dynamic logic computation is a relatively new direction in the fields of physics, communication, control, and integrated circuits.

Disclosure of Invention

The invention provides a configurable D latch for chaotic calculation, which aims to overcome the defects in the prior art. The invention realizes dynamic operation by different configurations of signals under the condition of not changing the circuit structure.

The technical scheme adopted by the invention is as follows:

a configurable D latch for chaotic operation comprises an alternative data gate, a configurable logic gate;

the alternative data strobe: the input signals are respectively a first input signal and a feedback signal, the control signal is a gating signal, and the output signal is a gated signal;

the configurable logic gate: the input signals are respectively a gated signal and a second input signal, the control signals are respectively a control signal Ctra and a control signal Crb, and the output signals are respectively an output signal Vout and an output signal NVout;

the output signal Vout of the configurable logic gate is the input signal of the one-out-of-two data strobe, i.e., the feedback signal.

The alternative data strobe comprises two transmission gates and a CMOS NOT gate.

The configurable logic gate comprises a CMOS NAND gate, a CMOS NOR gate, three CMOS NOR gates, a CMOS XOR gate, a pseudo NMOS and NOR gate and a pseudo NMOS NAND gate;

the gated signal and the second input signal are simultaneously input to a CMOS NAND gate and a CMOS NOR gate to generate output signals which are respectively an output signal Vnand and an output signal Vnor;

the control signals Ctra and Ctrb respectively pass through a CMOS NOT gate to generate output signals NCtra and NCtrb;

taking the output signals Vnand, Vnor and NCtrb and the control signals Ctra and Ctrb as input signals of a pseudo NMOS and a NOR gate to generate an output signal NX 1;

taking the output signals Vnor, NCtra and the control signal Ctrb as input signals of a pseudo NMOS NAND gate to generate an output signal NX 2;

the output signals NX1 and NX2 pass through a CMOS exclusive-OR gate to generate an output signal Vout, and the output signal Vout passes through a CMOS NOT gate to generate an output signal NVout.

The invention has the beneficial effects that: on the same hardware circuit, different logic functions can be realized through different combinations of control signals, so that the dynamically configurable D latch is realized, and the dynamically configurable D latch is used in the dynamic operation fields of chaotic calculation and the like.

Drawings

FIG. 1 shows a configurable D-latch for chaotic computation;

FIG. 2 is a block diagram of the configurable logic gate of FIG. 1;

fig. 3 is a block diagram of the alternative data selector of fig. 1.

Detailed Description

The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited to these examples.

Examples

FIG. 1 shows a configurable D latch for chaotic computation, which includes an alternative data gate, a configurable logic gate;

the output signal Vout is an input signal, i.e., a feedback signal, of the one-out-of-two data strobe.

As shown in figure 2 is a block diagram of a configurable logic gate,

the configurable logic gate comprises a CMOS NAND gate, a CMOS NOR gate, three CMOS NOR gates, a CMOS exclusive-OR gate, a pseudo-NMOS and NOR gate and a pseudo-NMOS NAND gate.

And the gated signal and the second input signal are simultaneously input to a CMOS NAND gate and a CMOS NOR gate to generate output signals which are respectively an output signal Vnand and an output signal Vnor.

The control signals Ctra and Ctrb pass through the CMOS NOT gate to generate output signals NCtra and NCtrb, respectively.

The output signals vnind, Vnor, NCtrb and the control signals Ctra, Ctrb are used as input signals of the dummy NMOS and nor gates to generate an output signal NX 1.

Wherein,

<math> <mrow> <mi>NX</mi> <mn>1</mn> <mo>=</mo> <mover> <mrow> <mi>Ctrb</mi> <mo>·</mo> <mi>Vnand</mi> <mo>+</mo> <mi>Ctra</mi> <mo>·</mo> <mi>Vnor</mi> <mo>·</mo> <mi>NCtrb</mi> </mrow> <mo>&OverBar;</mo> </mover> </mrow> </math>

the output signals Vnor, NCtra and the control signal Ctrb are used as input signals of the pseudo NMOS nand gate, and an output signal NX2 is generated.

<math> <mrow> <mi>NX</mi> <mn>2</mn> <mo>=</mo> <mover> <mrow> <mi>NCtra</mi> <mo>·</mo> <mi>Ctrb</mi> <mo>·</mo> <mi>Vnor</mi> </mrow> <mo>&OverBar;</mo> </mover> </mrow> </math>

The configurable logic gate realizes the logic functions of AND, NAND, OR, NOR, XOR, XNOR, all-OR, all-high, all-low and the like through different configuration combinations of the two control signals of the configurable logic gate.

The method comprises the following specific steps:

when the control signals Ctra and Ctrb are respectively a logic low voltage and a logic low voltage, no matter what the input signal of the configurable logic gate is, the output signal Vout is a logic low voltage, and the output signal NVout is a logic high voltage;

when the control signals Ctra and Ctrb are respectively logic low voltage and logic high voltage, the configurable logic gate realizes the functions of exclusive OR and exclusive OR, namely

When the control signals Ctra, Ctrb are logic high voltage, logic low voltage, respectively, the configurable logic gate implements a NOR, OR function, i.e.

NVout = gated signal + second input signal

When the control signals Ctra and Ctrb are logic high voltage and logic high voltage respectively, the configurable logic gate realizes the functions of NAND and AND, namely

NVout = gated signal second input signal

The CMOS XOR with XOR function in the configurable logic gate represents the non-linear characteristic, because when the two input signals of the XOR gate are respectively logic low voltage, logic low voltage or logic high voltage and logic high voltage, the result after XOR is logic low voltage, and when the two input signals of the XOR gate are respectively logic low voltage, logic high voltage or logic high voltage and logic low voltage, the result after XOR is logic high voltage, the relation between the input signals and the output signals of the XOR gate represents the non-linear characteristic.

As shown in fig. 3, which is a block diagram of an alternative data strobe, the alternative data strobe includes two transmission gates and a CMOS not gate. The gating signal generates an output signal NSel through the CMOS not gate. The feedback signal, the gating signal and the NSel signal are used as input signals of the transmission gate 1, and the first input signal, the gating signal and the NSel signal are used as input signals of the transmission gate 2 to generate a gated signal.

When the gating signal of the one-of-two data gating device is logic high voltage, the one-of-two data gating device outputs a first input signal, and when the gating signal is logic low voltage, the one-of-two data gating device outputs a feedback signal.

When the control signals Ctra and Ctrb of the configurable logic gate are respectively set to logic high voltage and logic low voltage, the configurable logic gate realizes the nor or function, and at the moment, the second input signal is set to logic low voltage, so that the function of the D latch is realized.

The function of a D latch is realized, the selected signal is logic high voltage, and the D latch allows a first input signal to pass through the latch to an output end; when the strobe signal is a logic low voltage, the D-latch blocks transmission of the first input signal.

And when the control signal Ctrb is changed from the logic low voltage to the logic high voltage, the circuit realizes a zero clearing function for the NVout output end, and realizes a set 1 function for the Vout output end.

The control signal Ctrb in the holding circuit is logic low voltage, and the control signal Ctra is changed from logic high voltage to logic low voltage; or the control signals Ctra and Ctrb in the holding circuit are respectively logic high voltage and logic low voltage, and the second input signal is changed into logic high voltage from logic low voltage; the circuit can realize the function of setting 1 for the NVout output end and the function of clearing zero for the Vout output end.

When two control signals Ctra and Ctrb of the configurable logic gate are respectively set to be logic high voltage and logic high voltage, the configurable logic gate realizes the functions of NAND and AND, and at the moment, when the second input signal is set to be logic high voltage, the D latch function is realized.

And realizing the function of a D latch, wherein the D latch allows the first input signal to pass through the latch to the output end when the strobe signal is logic high voltage, and prevents the transmission of the first input signal when the strobe signal is logic low voltage.

The control signals Ctra and Ctrb in the holding circuit are respectively logic high voltage and logic high voltage, the second input signal is changed from the logic high voltage to the logic low voltage, the circuit realizes the zero clearing function for the NVout output end, and the 1 setting function is realized for the Vout output end.

The control signals Ctra and Crb are simultaneously changed from a logic high voltage to a logic low voltage; or the control signal Ctra in the holding circuit is logic high voltage, the second input signal is logic high voltage, and the control signal Crbb is changed from logic high voltage to logic low voltage; the circuit can realize the function of setting 1 for the NVout output end and the function of clearing zero for the Vout output end.

The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims

1. A configurable D latch for chaotic operation is characterized by comprising an alternative data gate, a configurable logic gate;

the output signal Vout of the configurable logic gate is an input signal of the alternative data gate, namely a feedback signal;

2. The configurable D-latch for chaotic operations of claim 1, wherein the one-of-two data strobe comprises two transmission gates and one CMOS not gate.